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Ajay Abraham
ajayabraham001@yahoo.com, 9962647238
Thiruvalla-689542, Kerala
Career Objective
To secure a position in an apex organization to enhance my skill and growth in career as a Full
Custom Layout Engineer
Core Competancy
Basic knowledge on CMOS concepts
Basic knowledge on design of area and route efficient layouts.
Basic knowledge on DRC and LVS.
Worked on Standard Cell Layouts in 28nm and 90nm process.
Worked on Analog Layout in 180nm process.
Basic knowledge on Matching Techniques such as Common Centroid and Interdigitization.
Worked on SRAM Leaf Cells Layout in 28nm process.
Basic knowledge on Latch-up,ESD,Antenna Effect,Electromigration and how to fix them.
Basic knowledge on Well Proximity Effect
Basic knowledge on parasitics reduction in layouts
Education Details
PG Diploma in Advanced Diploma in ASIC Design - Full Custom 2016
RV-VLSI Design Center
Master Degree in Vlsi Design 2015
Srm Institute Of Science And Technology, with 7.72 CGPA
Bachelor Degree in Electronics and Communication 2012
College Of Engineering Adoor, with 65.81 %
PUC / 12th 2008
Mar Thoma Residential School, with 78.83 %
SSLC 2006
Mar Thoma Residential School, with 79.33 %

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Domain Specific Project
RV-VLSI Design Centre,Banglore
Standard Cell Layout Engineer Sep-2015 to Sep-2015
9 Track Standard Cell Layout in 90nm process
Description
To draw the layouts of Combinational Circuits such as NAND,NOR,XOR,MUX,HALF
ADDER,Sequential Circuits such as D-FLIPFLOP,S-R LATCH and make them clean from
DRC,LVS and Compatability errors(such as pin placement,height of Standard Cell and N well).
Tools
Mentor Graphics : Layout Design - Pyxis Layout Editor , Physical Verification - Calibre
Challenges
1) Since the area of the standard cell was given,the layout has to be fitted within the pr
boundary.Therefore floor-planning was difficult for large and complex layout.
2 ) Missing/incorrect instances ( If the transistors drawn in the layout are missing or
connected wrongly).
3) Missing/incorrect nets ( If the connections between the transistors in the layout are missing
or connected wrongly).
4) Missing/incorrect ports ( If the input and output ports in the layout are missing or
connected wrongly).
RV-VLSI Design Centre,Banglore
Analog Layout Engineer Oct-2015 to Oct-2015
Analog Layout of 2 Stage Opamp in 180nm process
Description
To draw the layout of a 2 stage Opamp in 180nm technology and make it clean from DRC and
LVS errors. Responsibilities during project execution include employing centroid matching,
transistor folding and drawing layouts efficient in area and routing.
Tools
Mentor Graphics: Layout Design - Pyxis Layout Editor , Physical Verification - Calibre
Challenges
1) The floor-planning has to be optimized to avoid matching issues.
2) Routing issues (The transistors have to be carefully connected so as to get an error free
layout).
3) Since the area is a constraint we have to draw the layout within the given area by using
minimum DRC rules.
4) Placement of dummy transistors.

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RV-VLSI Design Centre,Banglore
Standard Cell Layout Engineer Nov-2015 to Nov-2015
9 Track Standard Cell Layout in 28nm process
Description
To draw the layouts of Combinational Circuits such as
INV1X1,INV1X2,INV1X3,NAND2X1,NAND3X1,NOR2X1 ,NOR3X1 and make them clean from
DRC and LVS errors.Area and route efficient layouts had to be drawn.Transistor folding had to
be used.
Tools
Mentor Graphics: Layout design - Pyxis Layout Editor, Physical Verification - Calibre
Challenges
1) Poly and contact must be placed in grid at a distance of 0.162um.
2) When channel length is more than 80nm, we have to skip one grid to put the next poly.
3) Placement of dummy poly's.
4) Horizontal poly is not allowed in this process.
RV-VLSI Design Centre,Banglore
Memory Layout Engineer Nov-2015 to Jan-2016
SRAM Leaf Cells Layout in 28nm process
Description
To draw the layout of SRAM leaf cells in 28nm technology and make them clean from DRC and
LVS errors.Responsibilities during project execution were to draw area and route efficient
layouts,employ well sharing,transistor folding and centroid matching.
Tools
Mentor Graphics: Layout Design- Pyxis Layout Editor , Physical Verification- Calibre
Challenges
1) Poly and contact must be placed in grid at a distance of 0.162um.
2) When channel length is more than 80nm we have to skip one grid to put the next poly.
3) Placement of dummy poly's
4) Routing using minimum metal and maintaining minimum distance between them.

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B.E / B.Tech Academic Project
College Of Engineering Adoor
Face Recognition Using Vhdl
Description
The project uses vhdl in a face recognition circuit which has applications in security areas
where unauthorized entry is not allowed.
Tools
Software- VHDL, Hardware- Xilinx Vertex 2 FPGA Development Kit
Challenges
In authorized access,the facial image of a person taken by camera is matched with the list of
persons in the database.If the person did not directly face the camera or if it is partially
illuminated in light then facial recognition becomes difficult.
M.E / M.Tech Academic Project
Srm Institute Of Science And Technology
Optimized Design Of An Add Multiply Operator Using Modified Booth Recoder
Description
The normal design of add multiply operation where output of adder is allocated to multiplier
increases both area and delay.Inthis project the adder and multiplier are fused using Sum To
Modified Booth Recoding Technique which reduces area and delay.
Tools
Software - Model-Sim 6.4c, Xilinx ISE 9.1i
Challenges
More time was taken to manually calculate the theoretical output of an add multiply operation
practically given by the software.