1. Z i a d I b r a h i m A b d e l a t i
Phone: (+02)01119140077
Email: ziadibrahim2016@gmail.com
LinkedIn: https://eg.linkedin.com/pub/ziad-ibrahim/6b/96a/b60
E D U C A T I O N
2011 TO PRESENT FACULTY OF ENGENEERING-CAIRO UNIVERSITY
Electronics and Electrical communications-Fourth year
Cumulative Grade: Distinct (91.83%) Cumulative Rank: 6th
E X P E R I E N C E
JUL.2015-SEP.2015 MENTOR GRAPHICS
Intern at GRD Egypt Calibre Team
Modeling equivalent circuits for transmission lines and
junctions. Then Optimizing models with reference data to
support full library of equivalent circuits for any stack.
SEP.2014-OCT.2014 MENTOR GRAPHICS
Intern at GRD Egypt ESD Engineering Team
Configuring and running code bench with physical/virtual
boards.
AUG.2014-SEP.2014 MOBINIL
Intern at Technology Department
Mobistep -Summer Internship
GSM and 3G construction, monitoring errors of the system
from HLR to BTS and take the required actions for these
errors.
JUN.2014-NOV.2014 MENTOR GRAPHICS COMPETITION
Third place
The 8th annual design contest for students (design contest
2014)
E X T R A - C U R R I C U L AR A C T I V I T I E S
2015 TO PRESENT President of Embedded System Lab (ESL)
Student lab with full fund support from Ministry of Higher
Education
2014 TO PRESENT Co-founder of Embedded System Lab (ESL)
Student lab with full fund support from Ministry of Higher
Education
2014-2015 Participant in IEEE Digital Design Flow workshop
Understanding modern digital design flow and digital design
including both combinational and sequential designs using
Verilog.

2. 2
2012-2013 Member in k-vector foundation
Coordination committee: Events organization
2011-2012 Participant in STP
Marketing workshop: Know about marketing techniques
T E C H N I C AL S K I L L S
 RTL modeling using VHDL and Verilog
 MATLAB programming & Simulink
 Xilinx tools : ISE , PlanAhead , Xilinx platform studio(xps) and Xilinx software
development kit (xsdk)
 Implementation of partial dynamic configuration systems on Xilinx FPGAs
using ICAP IP
 Scripting languages (Shell, Perl and TCL)
 Using high frequency tools simulators (sonnet and Hyperlynx)
 Simulation Software (Multisim and Proteus)
 Cadence Virtuoso
 Good command of C++ with object oriented concepts(OOP) and data structure
 Design Patterns
 Microcontroller projects using AVR and arduino C
 Microprocessor design
 Mobile package diploma (2G-3G-4G)
P R O J E C T S
 Digital circuit design ,i.e. ALU (2012-2013)
 Minesweeper competition (2013-2014)
 32- bit,52-instructions general purpose processor based on harvard
architecture using VHDL (2013-2014)
 LC3 microprocessor using VHDL for mentor graphics competition (2013-2014)
 Temperature and motion monitoring system using AVR microcontrller,sensors
,lcd and keypad supported by a MATLAB GUI for continuously updating a PC
with the temperature and motion (2014-2015)
G R AD U A T I O N P R O J E C T
SDR Implementation using PDR
Supervision: Dr.Hassan Mostafa Hassan and Dr.Yassmen Aly Hassan Fahmy.
The target of the project is to implement the transmitter for the three standards (Wifi-
3G and LTE) and try to reconfigure the FPGA by the desired chain during the fly
without the need of resetting it. This technique depends on the new technology PDR
(Partial Dynamic Reconfiguration) which is expected to save area, power and cost of
communication devices and increase the speed of switching and reconfiguring the
FPGA. During the project, experience is gained in HDL & MATLAB modeling of the
transmitter and receiver blocks of the three standards, building a system on chip that
consists of: Microblaze processor IP, ICAP IP to enable partial configuration and
other peripherals to enable communication with PC for testing, testing the
reconfiguration on the entire chains then finally testing the reconfiguration on
separate blocks of the chain.
P E R S O N AL I N F O R M AT I O N
 Military Status: Exemption Date of Birth: December 1993