Vlsi best notes google docs
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This document provides resources for learning about the semiconductor industry, including conferences, papers, tutorials and courses. It aims to help readers achieve productivity, learn new things, share information, and gain concise knowledge. The resources cover topics like static and dynamic power analysis, memory macros, verification, low power design, and more. The document is intended to be updated weekly with additional learning materials.
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Vlsi best notes google docs
- 1. I am preparing this document to help others in the semiconductor industry to achieve: 1. productivity 2. learn new things 3. share information 4. remove noise and share the most important, relevant and concise information If you have any questions feel free to reach me @ mvrajesh1@gmail.com I plan to update this document every week and share it with the world This document is a working document, what I learned every day, I made a summary of those in here. Last updated: March 17, 2019 https://www.edn.com/electronicsblogs/edapowerup/4430406/RailanalysisforSoCASICs Static and Dynamic IR analysis on SoCs This early analysis is important, because placement and routing engines consider the routing resources that are left over after PG routing to be available for signal routing. So, late changes to PG routing can have a domino effect on the signal routing, and also on placement, as PG routing can effectively “block” legal placement locations, due to pin accessibility issues. In addition, the multipatterning routing that is required at 20nm and below further complicates late changes to PG routing, as the available legal routing outcomes are more constrained and computationally much more intensive to achieve. static rail analysis is driven by power consumption for the average situation, based on a switching probability for each instance in the design. This approach allows for the computation of IR drops and current densities to determine if the PG routing has a low enough resistance to deliver the required current for proper chip operation, and sufficient widths and via instantiations to carry the current without electromigration failure. Dynamic analysis outputs voltage waveforms that enable measurement of the transient droops or spikes at points of interest in the PG networks. This approach enables us to determine whether or not the decoupling capacitance between the power and ground networks is sufficient to keep these deviations to an acceptable level. Handling Memories and Other Macros As in the static case, a similar extension is needed. Current waveforms must be characterized at different physical points in the power pin geometries to account for local differences in current consumption due to spatial differences in circuit behavior. For example, in the case of an SRAM, the current signatures over the bit cells will be different from those over column drivers or row decoders. Thus, each macro will be represented by multiple current source waveforms for the dynamic rail analysis circuit formulation. SNUG conference every year: https://www.synopsys.com/community/snug.html Attend to socialize and meet other leaders from semiconductor industry Interesting practical ideas in the presentations while implementing complex SoCs Different tracks for verification, IP, PD etc. TSMC Technology Symposium https://www.tsmc.com/english/event/symp2019/index.html Get to know the latest of what Fab is offering Meet and socialize with other Semiconductor leaders ISPD conference happens every year: http://www.ispd.cc/?page=archives Rich set of slides archived relevant to PD Many of the advanced concepts are presented by University professors in a well defined manner Front end RTL Design, verification, CDC trainings: http://www.sunburstdesign.com/papers/ Take these trainings for a detailed and comprehensive knowledge on the topics of interest UVM, System Verilog, CDC, Verification techniques
- 2. https://www.ucscextension.edu/certificateprogram/technology/vlsiengineering I personally took a lot of classes in UCSC extension to broaden my areas of expertise I took DFT, Systemverilog, STA, PD, Perl, Python, Machine Learning courses here, the classes are after hours or on weekends and many professionals attend these courses You can take one course per quarter The location is very convenient to working professionals in bay area https://scpd.stanford.edu/public/category/courseCategoryCertificateProfile.do?method=load&certificateId=1222198 there are courses which Stanford offers for working professionals These require more time commitment To study about chip variation (OCV), I took a lot of time to prepare these slides, you can read up on these slides: https://www.slideshare.net/venkatamekala1/studyofinterandintrachipvariations https://www.hotchips.org/archives/2010s/hc29/ These are some awesome technical presentations on various Chips designed from several industry leaders I highly recommend watching these presentations If possible attend Hot Chips conference some time to get a feel of it and also meet the best people in the industry http://www.hotchips.org/ https://www.youtube.com/channel/UCjtg76lhmVr0K86zMxbFGw subscribe to hotchipvideos to listen to them in free time on youtube Learn TCL https://www.tcl.tk/ https://www.tcl.tk/man/tcl8.5/tutorial/tcltutorial.html Nice tutorial for TCL programming http://www.beedub.com/book/tkbook.pdf Practical programming in TCL/TK https://solvnet.synopsys.com/ enroll in solvnet (Synopsys) There are many good articles and comprehensive documentation on all Synopsys tools I highly recommend to read Design manuals, user guides of tools of your interest https://www.synopsys.com/support/training.html Attend these trainings on synopsys tools http://users.ece.utexas.edu/~mcdermot/vlsi2/Lecture_8.pdf Clock skew and jitter paper good read http://koreatest.or.kr/sub02/2014data/3.pdf Best paper on the timing margins Read it thoroughly few times http://sliponline.org/SLIP06/Presentations/2_1_lou.pdf Download and read about interconnect on chip variation Learn Linux commands especially sed, awk: https://catonmat.net/archive There are lot of online resources and it is not a one day sprint, keep learning daily as much as possible
- 3. So much detailed and indepth presentation of FinFet technology: https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSITshortcourse Another super article on timing margins, OCV: http://www.tauworkshop.com/2014/Slides/hill_tau_2014_shared.pdf There are some VLSI videos taught by this professor, they are quite basic and fundamental but are taught very well, watch these videos: https://www.youtube.com/playlist?list=PLFhizsGPFKt8gzbYlKMDCgBKwxMc33H2 Xilinx timing closure user guide: http://wwwwjp.cs.unisaarland.de/lehre/hadeprak/block_ss15/Upload/ug612.pdf Excellent thesis on clock tree design: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS200898.pdf I often find reading M.S. or PhD thesis papers are very refreshing, detailed and gives you a perspective on a particular topic at a whole new level Keep reading PhD/Master’s thesis presentations when you have free time Some of the SNUG user presentations are here: https://www.synopsys.com/community/snug/snugaustin/locationproceedings2015.html 2015 SNUG presentations These are very helpful to know uptodate of semiconductor industry happenings UPF standards document: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.133.6194&rep=rep1&type=pdf Design Verification Conference: https://dvcon.org/ What is dark silicon? https://en.wikipedia.org/wiki/Dark_silicon GCA (Galaxy Constraint Analyzer) https://www.synopsys.com/news/pubs/snug/sanjose11/tc3_tutorial_GCA_FINAL.pdf Global Routing and Detailed Routing (Few slides focused on this topic) http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/EDA_routing.pdf Low Power Design Techniques (Good Slides): http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf
- 4. SystemVerilog for Design (Textbook download): http://read.pudn.com/downloads166/sourcecode/math/758655/Springer%20%20SystemVerilog%20for%20Design,%2 02nd%20Edition.pdf HDL methods for low power design: https://www.designreuse.com/articles/20775/hdldesignlowpower.html Principles of verifiable RTL design: https://pdfs.semanticscholar.org/11d0/1cbdd90177c882bfa029879c48d0cbd3a4a9.pdf Serdes PAM4 presentation: https://www.xilinx.com/publications/events/designcon/2016/slidespam4signalingfor56gserialzhangdesigncon.pdf Thesis presentations from UC Berkeley: https://www2.eecs.berkeley.edu/Pubs/TechRpts/ https://vlsicad.ucsd.edu/Presentations/talk/EDPS2015_Kahngdistributed.pdf A Roadmap for LowPower Design: Trends, Technology, Tools http://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/Older/lect_09_power_delivery_1up.pdf Lecture from a course in Stanford university on power delivery on Chip Write constraints for synthesis tutorial: ***** http://www.ee.bgu.ac.il/~digivlsi/slides/synopsys_class_2_5_1.pdf Memory Errors in Modern Systems The Good, The Bad, and The Ugly https://www.cs.virginia.edu/~gurumurthi/papers/asplos15.pdf VLSI interview questions: https://cdcnitw.files.wordpress.com/2013/04/vlsi_questions.pdf https://www.edn.com/design/testandmeasurement/4388547/SOCDFTverificationwithstaticanalysisandformalm ethods SOC DFT verification with formal methods Understanding the I2C bus protocol: http://www.ti.com/lit/an/slva704/slva704.pdf Undestanding LVS (Layout versus Schematic): https://www.edn.com/design/integratedcircuitdesign/4418390/Aninsightintolayoutversusschematic https://en.wikipedia.org/wiki/Layout_Versus_Schematic
- 7. TCL commands index: https://www.tcl.tk/man/tcl8.6/TclCmd/contents.htm http://csg.csail.mit.edu/6.823/lecnotes.html MIT comp arch slides http://csg.csail.mit.edu/pubs/courses.html nice MIT courses clock dividebyn algorithm: https://www.slideshare.net/DeepakFloria/dividebynclock https://www.youtube.com/watch?v=J8jJrNxthKA timing exceptions tutorial xilinx, excellent These are a series of videos, watch them for sure ! Textbook purely focused on congestion: https://pure.tue.nl/ws/files/3334308/200911890.pdf http://courses.ece.ubc.ca/579/WireShieldingSpacing.pdf very good paper on crosstalk ICC2 PG planning slides: https://solvnet.synopsys.com/retrieve/customer/application_notes/attached_files/2559014/PG_Optimization_With_Co mposite_Patterns_v2.pdf Dynamic Voltage (IR) Drop Analysis and Design Closure: https://www.apacheda.com/system/files/Dynamic_Voltage_drop.pdf Question: What is the impact of metal fill on signal integrity analysis? Answer: There are two types of metal fill, floating fill and grounded fill. Both types of metal fill are considered during signal integrity analysis. ● Floating fill does not completely shield the aggressor nets, so signal integrity effects are seen from its neighbors. ● Grounded fill completely shields the aggressor nets, so it has less impact on signal integrity than floating fill. However, grounded fill increases the coupling capacitance and therefore increases the total capacitance more than floating fill. Most foundries recommend floating fill earlier in the design flow because it is more difficult to ground the fill, which requires tracking and connecting to the PG nets of the fill. You should get a recommendation from your foundry on which type of fill to use because it depends on the process and the cost.
- 9. set_output_delay min For more clarification Read this The data setup time is the time the data inputs must be valid before the clock/strobe signal occurs. The hold time is the time the data must remain valid after the clock/strobe. Both can be zero or negative. An example is that t_SHDI the data hold time after DS* is high is 0. A zero setup time means that the time for the data to propagate within the component and load into the latch is less than the time for the clock to propagate and trigger the latch. A zero hold time means either that the moment the clock is asserted, the latch no longer looks at its inputs, or else that the clock path delay is shorter than the data path delay. A negative setup or hold time means that there is an even larger difference in path delays, so that even if the data is sent later than the clock (for setup time), it still arrives at the latch first. Typically manufacturers avoid specifying negative values since this restricts later design and manufacturing decisions, but they often specify zero values since this simplifies usage in a system. https://www.intel.com/content/dam/alterawww/global/en_US/pdfs/literature/an/an433.pdf source synchronous constraints constraining data skew check in the .lib http://tech.tdzire.com/howtoconstrainthedataskewcheckinthelib/ DDR timing in primetime http://www.zimmerdesignservices.com/mydownloads/snug02_ddr_final032406.pdf http://www.zimmerdesignservices.com/publications/ low power design techniques dynamic power reduce toggle count RTL clock gating and ICGs reduce voltage structural placement reduce cell drive strengths VT sweep to achieve best subset of cells for timing closure and lower power reduce glitches reduce total net length multiple modes (different vdd, different frequency) split rails (VDD_mem, VDD_logic) relax max_trans constraint disable high drive strength cells meeting timing disable complex cells retiming? technology node selection voltage islands low power designware components clock tree quality (latency, skew)
- 10. accurate timing constraints better PLL for jitter margins multibit flipflop to reduce clock power custom/structural placement SAIF based placement, Low Power Placement flow memory placement, floorplanning affects placement, total net length software scheduling (not virus) SRAM selection sweep to change floorplan and reduce overall net length leakage power multi VT, multi drive strengths leakage, area recovery power gating (header/footer) body bias control LVT usage in PD (allow only % of LVT cells) 3sigma versus 2sigma corners, reduces yield but better leakage characterized library at power corner (Scaling values are pessimistic) https://m.eet.com/media/1121857/chapter2_clocks_resets03.pdf synchronous, asynchronous reset good document Perl Interview Questions: https://www.tutorialspoint.com/perl/perl_interview_questions.htm Difference between contact and via: Contact is connection to source, drain or poly. While vias is used to make connection between two metal layers. Both vias and contact are formed using metals. Vias are generally made of tungsten while contact is made using aluminum. Difference between via array and stacked via: http://www.vlsiexpert.com/2017/12/vias.html ISPD via pillar advantages presentation: http://www.ispd.cc/slides/2017/k3.pdf ITRS workshop slides: https://www.dropbox.com/sh/vasm431o2okvs16/AACXQvDNQ5hgzT8Bt4C6xT22a?dl=0 https://www.synopsys.com/news/pubs/snug/2018/europe/ta01sharmacrimminspresuser.pdf Design closure of a VPU MOM vs MIM capacitor explanation: https://www.quora.com/WhatisthestructureofaMIMcapacitor http://www.ispd.cc/contests/19/lefdefref.pdf LEF, DEF language reference document