ASIC Design Fundamentals

1. Current Challenges in Physical
Design
Presented by: PD Lead

2. Agenda - Current Challenges in ASIC
Physical Design
• Roots of challenges
• Delays - the main challenge
– Wire load models
• Generic PD flow
• Challenges in PD flow at different steps
• SI Challenge - Noise & Crosstalk, IR Drop
• Process effects
– Process Antenna Effect
– Electromigration
• Moving Forward

3. Root of challenges
• The main motivation behind ASIC Design is to develop chips
that:
– Work faster
– Are reliable
– Highly integrated
• Speed of a circuit is directly governed by delays involved in
the overall design – these are well-understood today
• Reliability is dependent on physical effects that can
manifest in some form or the other in a chip
– Can be controlled only by continuously evolving the fabrication
methodology
– A lot of effects are still a subject of active research
• Integration is being facilitated by scaling – very aggressive

4. Speed Requirement
P6
Pentium ® proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Frequency
(Mhz)
Doubles every
2 years

5. No. of Transistors - following Moore’s
law so far
Courtesy:Paper by Greg Watson of University of Delaware: “Moore’s Law: Is it rolling over?”

6. Root…
• While reliability and integration are foundry/ technology issues,
speed falls in ASIC design domain
• To achieve higher speeds, a lot of methodologies are being evolved
– Plain synthesis – not efficient for DSM (Deep Sub-Micron) technologies
– Physical Synthesis – closed the gap that was present in Plain Synthesis
flow
– Virtual Prototyping – closes the gap further – but yet not complete
– Interconnect-centric flow – likely to close the gap further – still being
studied
• Some device level effects have been modeled mathematically and
have been brought into EDA tool domain
• A lot of these are still at a very basic level – subject of active
research

7. Challenges
• Physical Design Engineer has to contend with real, physical effects
• Physical Design is an exercise of mapping a design from logical
domain to physical domain
• Entire process is dependant upon
– Libraries - where the physical effects are mathematically modeled
– Tools - have the necessary corrections/ remedies to the physical
effects
• As of now, not all the physical effects have been modeled - hence
there is a huge overhead on the Physical Design Flow to take care of
the adverse effects
• Delay is the only effect that has been modeled with a good accuracy
- flow based on handling delay has been used for long - known devil

8. Challenges
• Other challenges in Physical Design are:
– Flow Based:
• Partitioning - the most challenging aspect of this is getting a rectilinear
physical partition, optimal partition that meets timing, power etc.
• Floor planning - with IPs and memories flooding the designs, floor
planning is becoming the key to a successful design closure
• Placement - placer has to take care of a lot of issues like meeting
timing, congestion, design considerations like scan, boundary scan etc.
• Clock Tree Synthesis - the most challenging aspect of this is meeting
skew AND transition time AND insertion delay constraints
• Routing - router has to take care of design requirements like meeting
timing, incremental routing, routing on specific layers etc.
• Extraction - 3D and accurate extraction, extracting in standard format,
limited file size

9. Challenges
– Device related:
• Antenna effect - device scaling has made the transistor gate more
vulnerable to this effect - short term reliability issue
– Ref: https://en.wikipedia.org/wiki/Antenna_effect
• Noise - device scaling has also reduced the threshold of the
devices thereby increasing noise vulnerability
• Crosstalk - Due to increase in the vertical profile of nets, coupling
capacitance component has increased, causing increased crosstalk
• IR Drop - device scaling is also bringing down the value of
allowable IR drop
– Ref: http://www.vlsitechnology.org/html/irdrop_1.html
• Electromigration - Increased integration means increased power
dissipation - root for electromigration
– https://en.wikipedia.org/wiki/Electromigration
• Hot Electron effect - long term reliability issue
– https://en.wikipedia.org/wiki/Hot-carrier_injection
• Leakage current - IDDQ
• Sub-threshold effects due to reducing channel length

10. Delay
• Delay is the difference in “required time” and “arrival time”
– in synthesis terminology
• What can cause delay in a design?
– Device
– Interconnects
• Pre-DSM designs:
– Device delays were predominant
• DSM – UDSM designs:
– Device delays have been scaled down, but interconnect delays
have shot up
• ASIC design flow remained largely unchanged even if the
technology improved from 0.5 microns to 0.13 microns in
just 3 years

11. Gate delay vs Interconnect delay
0
5
10
15
20
25
30
35
40
0.65 0.5 0.35 0.25 0.18 0.13 0.1
Delay
(ps)
Interconnect Delay
Gate Delay

12. Gate Delay Modeling
• Cell Delay consists of two components:
– Intrinsic component
• Intrinsic delay - DI
– Extrinsic component
• Slope delay – DS – caused due to input transition - transition due
to previous stage
• Transition delay – DT – caused due to output pin loading and its
driving capability
• Interconnect delay – DC – caused due to the wire connecting the
output of one stage to the input of the next stage
DI
DS
DT
DC

13. Gate Delay…
• DI  Is the intrinsic delay of the cell without any load
connected to it
• DC  Is the delay due to the wire connecting one
stage to another – this is not known until the routing stage
• DT  Is the delay due to the output load – more
popularly known as fanout
• DS  Is the delay due to the transition delay of the previous
stage
• Cell delay are modeled in library in the form of 2-
dimensional tables
– Delay is a function of input transition and output load
– Too difficult to make it a function of DC since immense
possibilities of net topologies
Differentiate better between input delay and output delay

14. Interconnect Modeling - Wire Load
Models
• As DC is not available at the time of Synthesis,
some estimate is taken for calculation - this is
called Wire Load Model
• Equations for different delay components are
as follows:
DS = Ss x DT(previous stage)
DT = Rdriver(Cwire + Cpins)
DC = Rwire(Cwire + Cpins)

15. Wire Load Models
• Rwire
– determined from wire load model
• Length of net
– computed from the global estimation function which is
based on the number of fanouts for that net
• Cwire
– determined from the function that relates wire length with
the capacitance
• This forms the basis of Wire Load Models
• WLMs are estimations which relate the above three
parameters
• Examples:

16. WLM - Examples
• In the examples shown below
– Resistance - typical resistance of the nets per length
– Capacitance - typical capacitance of the nets per length
– Area - area of the net
– Slope - multiplication factor for wire lengths > 1 in the fanout_length construct
wire_load("tsmc13_wl10") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 66.667;
fanout_length (1,66.667);
}
wire_load("tsmc13_wl20") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 133.334;
fanout_length (1,133.334);
}
Example - 1 Example - 2

17. Gate Intrinsic Delay
• The basic building block of today’s cell-based designs is
a CMOS inverter
• CMOS Parasitics
– Resistance
• Source - Drain channel resistance
• Well tap resistance
• Substrate tap resistance
– Capacitance
• Source - Drain capacitance
• Gate - Channel capacitance
• Gate - Source overlap capacitance
• Gate - Drain overlap capacitance etc.
– SCR - causes latch up (Similar to Thyristor latchup)

18. MOS - parasitic capacitors

19. CMOS:Typical Structure - up to Metal2
n - well
p+ p+
n+
n+
p substrate
p epitaxial layer

20. Moving to Flow

21. Physical Design Flow Basics
• Physical Design Flow methodology can be classified as
follows:
– Flat
• Entire design is read into the PD tool and then P&R carried out
• Does not mean that the netlist is flat - netlist CAN have logical
hierarchy - it is flattened once it is read into PD tool
– Hierarchical
• Entire design is read into the PD tool, partitioned and then P&R
carried out on each partition as well as top-level
• Netlist MUST have logical hierarchy
• It can be further classified into:
– Timing Driven - based on timing constraints
– Non-timing Driven - does not depend upon the timing
constraints

22. Existing ASIC Design Flow:
Floorplan
TPNA
S, P&R
Physical
Verification
TPNA
TPNA
Block
Charact.
Top level FLP
P&R
Physical
Verification
TPNA
TPNA
TPNA
Block Level Implementation
Top Level Integration
TPNA
T - Timing
P - Power
N - Noise

23. Basic ASIC Design Flow
Chip Specification
RTL
Partition into Blocks
Floorplan
Select circuit fam. & topology
Draw schematics
Functional Verification
Timing Verification
Fast enough?
Synthesize
Timing Verification
Fast enough?
Layout & Tapeout
Resize
or
change
topology
Add/
modify
constraints
No No
Custom Circuit
Flow
Automatic Circuit
Flow

24. Partitioning
• The process of decomposition of a larger system is
done such that:
– the original functionality of the design is not lost
– the interface interconnections between the blocks is kept
to minimum
– the resulting block sizes are manageable from the tool
point of view (memory/ processor time/ manpower etc.)
– the process of decomposition should be just a fraction of
the total design time (this is from the tool algorithm point
of view)
– the resulting block could be reusable in different designs
• Both SOCE and MAGMA can handle designs with
around 5 million gate count in “flat” fashion

25. Partitioning
• For all the existing tools, physical partitioning is possible only if the
design has logical hierarchy - limitation
• Partitioning exercise is actually a grouping exercise where one
groups the modules together based on certain design criteria
– functionality
– proximity
– least number of interconnection between physical partitions
• It has been difficult to obtain partitions that are rectilinear in shape
- SOCE is capable of generating rectilinear soft blocks, MAGMA is
not
• Each tool generates a different type of soft block abstract
– LEF in Cadence flow
– Glass Box in MAGMA flow
• Top level interconnect lengths are long - challenge

26. Partitioning: Example - Pentium
Source: Intel

27. Floor Planning
• The floorplanning problem is to plan the positions and
shapes of the modules at the beginning of the design
cycle to optimize the circuit performance:
– Chip Area
• Should be minimized keeping the Aspect Ratio in mind
– Total Wirelength
• Cannot be estimated at such an earlier stage - a major challenge
– Delay of critical path
• Plan the block placement and module placement in a way that
minimizes this delay
– Routability
• Floor planning should be carried out keeping in mind the
routability of the design

28. Floor Planning - some factors for
consideration
• Factors to be considered during floorplanning are:
– Shape of the block
• Modules should be shaped such that they form a perfect fit
– Routing considerations
• Follows from the routability concern from the previous slide
– Floorplanning and placement for high-performance circuits
• Certain techniques like blockaging etc. to be used to effectively
plan the area available for placement
– Packaging considerations
• While placing IOs one has to follow the packaging rules - IO
spacing rules
– Pre-placed blocks
• pre-placed blocks should not be moved

29. Floor Planning...
• One of the major challenges during the floor planning steps is to
ensure that timings are met
– how can one ensure timing closure when the interconnects are not in
place?
– Virtual Prototyping is the answer to this - tool must support that
• a step where a quick P&R is done to get an idea about the over all timing
profile of the design
• There is no tool which automatically generates a few floor plans
and gives out the timing and design statistics for each floor plan
– this will allow the designer to choose from the possible floor plans
• There is not tool which writes out parasitics file at this stage of the
flow
– If it does, the designer can carry out STA and find out the timing
statistics for a given floor plan

30. Floor Planning
• Hard IPs
– Advantage is that these are reusable as they are
– Problem is that these have fixed size
• Cannot resize during floor plan
• Causes problems for timing closure at the chip level (top
level)
– Can be solved by obtaining Soft IPs
• Can be resized and timing optimized from global perspective
• Another major challenge is packaging:
– Wire bond packaging - to follow packaging rules to
plan IOs
– Flip Chip methodology

31. Placement
• Placement strategies are built around the basic classification of
whether it is done timing driven or non-timing driven
• These strategies are:
– Scan based - whether scan is present or not
– Spare Cells based - whether spare cells are present in the design or
not
– Timing optimization requirement - whether timing optimization is
required or not and modes of optimization required
– Optimization Cells requirements - to use or not to use certain cells for
optimization
– Pre-wire keepout requirements - whether placement should be
allowed under the power stripes or not
– Region based placement - whether some cells are to be placed close
to IOs or in some region

32. Placement
• Challenges:
– Handling Multi-VT cells
• one would be required to create a different area for placing
these components since their physical features are different
• Most of the library vendors have started supporting this type
of cells as they are used for Low Power applications
– Ref: http://asic-soc.blogspot.in/2008/04/multi-threshold-mvt-
technique.html
– Handling Double-height cells
• one would be required to create a different area for placing
these components since their physical features are different

33. TERMINOLOGY
• Insertion delay - is a measure of time it takes the clock to
propagate from the root of the tree to the leaf cells
– Caused due to insertion of buffers along the clock path
– Two types - Minimum insertion delay and Maximum insertion
delay
• Skew - Spatial variation in arrival time of clock transition
• Jitter - Temporal variation of clock period at a given point
on a chip
• Transition time - slew rate of the clock
• Clock Tree Problem statement - balance the arrival time of
clock edge at the leaf pins with minimum skew making use
of the insertion delays while not compromising on the clock
transition time

34. TERMINOLOGY
• Skew - Spatial variation in arrival time of clock transition
– is the measure of the difference of delay between the minimum
and maximum time it takes the clock to reach the leaf cells
– A pair of registers are sequentially adjacent if only combinatorial
logic (no sequential elements) exist between the two cells.
– Effective skew - is the measure of the difference of delay between
the minimum and maximum time it takes the clock to reach the
leaf cells which are sequentially adjacent
– Does not change from cycle to cycle
Ri Rj
Combinational Logic
Tcomb
d q d q
clk
din dout
Ref for what is a leaf cell and other terms in the hierarchy:
http://www.rulabinsky.com/cavd/text/chap01-2.html

35. Terminology
• Jitter - temporal variation of clock period at a
given point on the chip
– Clock period changes from cycle to cycle
– Often specified at a given point
– Becoming a concern as clock frequencies are rising
– Cannot prevent it - PLL issue

36. Terminology
clk
clk with skew
clk with jitter
T
tjitter
launch edge capture edge
tskew
tsetup
thold
clk with skew & jitter
tskew
tjitter

37. Clock Equations
• Without skew and jitter
T > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold
• With Skew
T + tskew > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold + tskew
• With Jitter (worst case)
T - 2tjitter > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold + 2tjitter
• Combined skew and jitter effects (worst case)
T + tskew - 2tjitter > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold + 2tjitter + tskew

38. Causes of skew & jitter
• Clock Generation - Jitter
• Manufacturing Device Variations - Skew
• Interconnect variations: Skew
• Environmental variations: Skew and Jitter
• Capacitive coupling: Jitter

39. Routing
• Design Requirement
– Timing Driven Routing
– Non Timing Driven Routing
– Routing in a particular order
• Example: Clock Nets, Critical Nets etc.
– Routing the nets on a particular layer
– Routing with Process Antenna Effect corrections
– Routing only on the grid or allow off grid routing
– Post Route optimization
– Shielded Routing
– ECO routing
– Route only specific area

40. Extraction
• The Standard Parasitic File (SPF) lists extracted electrical
data for a design created by Place and Route tools such as
Silicon Ensemble
– This extracted data consists of placed and interconnected cell
instances
• The SPF file can have one of two formats
– Detailed SPF (DSPF) format or
– Reduced SPF (RSPF) format
• Embedded in each format are two circuit level models,
each with different degrees of complexity and accuracy,
that represent the physical design
• SPEF - Standard Parasitics Extraction Format - IEEE 1481
standard

41. Capacitance - overall view
Source: Cadence - HyperExtract User's Manual
C a= Area capacitance
from the target wire
to the bottom plate
C f = Fringe (or sidewall-
to-plate) capacitance
from the target wire to
the bottom plate
C c= Sidewall coupling
(or sidewall-to-sidewall)
capacitance from the
target wire to an
adjacent parallel wire
C v= Vertical coupling (or
vertical-wall-to-vertical-
wall) capacitance from
the target wire to a wire
that aligns exactly on at
least one side on an
adjacent layer

42. Interconnect Modeling
• Prevailing models are based only on Resistance and Capacitance
• Classification
– Lumped model
• The RCs are modeled as “near cap”, “far cap” and total resistance - pi model
• Less accurate
• File handling is easier and faster since less information
– Distributed model
• PI RC network for sections of net - number of section can be controlled
• More accurate
• File handling is slower
– Extraction tools use Model Order Reduction to reduce information
without compromising on accuracy
• Elmore algorithm
• Arnoldi algorithm

43. Extraction Challenges
• Modeling inductance
– depends upon a current loop
– difficult to model only from the layout since current return
paths need not necessarily be through substrate
• Modeling process effects
– Dishing effects due to CMP (chemical mechanical polishing)
process on metals
– Trapezoidal net profiles
– ILD (inter-level dielectric) thickness variation due to CMP
process
– Interconnect profile change caused due to Optical Proximity
Correction applied during mask preparation step
– Contacts and vias have started contributing to the RC effects -
this was ignored in earlier technologies

44. Extraction - Process effects
Post-CMP ILD thickness
Features
Dummy features
Post-CMP ILD thickness
Copper Dishing Effect
Optical Proximity Correction

45. Interconnect Capacitance Components
Cpp

Cfringe t
W

46. Noise and Crosstalk
• Noise and Crosstalk effects have increased due to the above net
profiles
– Together, the noise and crosstalk effects are called “SI” effects
• Capacitance components
– Parallel Plate - between the net and substrate
– Coupling - between the side-walls of the nets
CC
CC
CPP CPP CPP CPP
0.25 microns
0.13 microns

47. SI Effects
• SI effect revolves around two types of nets
– Aggressor net - the source net from where the transitions get coupled
– Victim net - the destination net which gets affected by the coupled
transition
• Crosstalk is the effects where the transition on one net (aggressor)
gets induced on to another net (victim)
• Causes two types of effects:
– Static - where victim net is quiet and only the aggressor net is
switching
• Not a concern if the induced glitch is at the input of a Flop
• Definitely a concern if the induced glitch is at the input of a combinational
logic
– Dynamic - where both, the victim and the aggressor are swicthing
• Causes timing violations

48. Static SI Effects
• Victim net is static
• If the glitch remains at the time when clock arrives, it would be
passed on to the next stage and would be a failure
• If the glitch vanishes before the clock arrives, it is not a concern

49. Dynamic SI Effects - Timing Violations
• Both, the victim net and the aggressor net are switching
• Here, the timing window is important
– If the nets are switching in the same timing window, it is a
matter of concern
– If the nets are not switching in the same window - case reduces
to static effects
• Switching within the same timing window
– If the aggressor and the victim are switching in the same
direction, it results into speeding up the signal on the victim net
- hold issue
– If the aggressor and the victim are switching in the opposite
direction, it results into slowing down of the signal on the victim
net - setup issue

50. SI Effects
Setup issue Hold issue

51. Corrections
• The corrections can be planned upfront during
functional simulation and can be applied during
routing
• Corrections include:
– Wire Spacing
– Net Ordering and Wire Topology Control
– Layer selection to reduce coupling
– Layer selection to reduce resistance
– Minimizing parallel long wires
– Shielding
– Buffer insertion on victim

52. Corrections
Reduced coupling due to
Wider spacing
Reduced coupling due to
layer selection
Net order/ topology control Avoiding long parallel nets

53. Corrections

54. IR Drop
• One of the most basic causes of failure in nanometer
designs is failure due to Ohm’s Law - IR Drop
• As voltage is scaling, IR drop is becoming a challenge
• Has a direct bearing on Power Distribution arrangement
• Maximum allowable IR drop is a technology measure -
around 2-3% of VDD
• Can cause IR drop induced delays
• An IR drop of 100mV caused an increase in path delays by:
– 15% in 0.25 micron technologies - VDD = 3.3V
– 55% in 0.13 micron technologies - VDD = 1V
• Correction measure is to carry out a Power aware physical
design

55. Process Antenna Effect
• This is a process effect - caused at the time of fabrication
• It is an “immediate” reliability issue
• Causes dielectric breakdown of the gate of a transistor
thereby destroying it - corresponding gate will be shorted
to channel
• Caused by accumulation of charge on an interconnect at
the time of fabrication
• This charge is generated during the processes like Ion
Etching or Chemical Mechanical Polishing etc.
• If the amount of charge collected on a net exceeds the gate
capability the gate oxide breaks down leading to short
circuit between gate and the channel

56. Process Antenna Effect
• Has been successfully modeled in library as well as
tools
• Library
– has parameters like:
• Antenna Gate Area Ratio: which is the ratio of Gate area to area of
the Net connected to the gate
• Antenna Diffusion Area Ratio: which is the ratio of Diffusion area
to area of the Net connected to the gate
• and so on
• Tool - routers
– Routers are built with PAE correction mechanism
• through Diode insertion
• Through layer hopping - re-ordering of metal layers of a net

57. Electromigration
• Electromigration is a long term reliability issue
• This is the effect where the wire heats up and breaks (fuses)
• Can cause voids (open circuit) at one end and hillocks (shorts) at the
other end

58. Electromigration
• Current flow in a normal housing wire is limited to 104 A/cm2 as it is
limited due to Joule heating effect
• In a semiconductor this limit is 1010 A/cm2 - due to good heat-
sinking
• If the current exceeds the above limit, the wire heats up and fuses
• This is the effect of electromigration
• Electromigration is caused by transport of diffusion atoms by flow
of current in a wire
• Definition: (Arzt and Nix, 1991)
– Electromigration is considered to be the result of momentum transfer
from the electrons, which move in the applied electric field, to the
ions which make up the lattice of the interconnect material

59. Electromigration
• Cause:
– Ions make up a crystal lattice which in turn make up a metal
– These ions vibrate due to several reasons - thermal energy is one of
the reasons
– Some ions can shift from their positions in the lattice - due to internal
vibration of the ions
– If the shift coincides with the flow of electrons these ions are carried
away - resulting into mass transfer
• Electromigration causes voids at the source point and hillocks at the
destination point of the current flow
• The electromigration effect is accelerated due to imperfection in
the interconnect microstructure - that is the reason Cu is preferred
over Al as an interconnect nowadays

60. Electromigration
• It is a regenerative effect as seen from the
figure
Growth of voids
Increase of local
current density
Increase of
heating
Increase of
temperature

61. Project Execution
•Design:
•Micro-architecture definition
•RTL coding in verilog
•Integration
•Verification
•Test environment design and coding
•System test plan generation & verification
•Synthesis and STA
•Synthesis (RC)
•Formal verification (Conformal), STA (ETS)
•PD
•Cadence flow for Digital and Analog physical design
•FE, QRC, VSPE, ETS and Virtuoso XL
•DFT – Encounter Test
•Scan, ATPG for the digital block
•Test IO pins for testing system
•Methodology – hierarchical
Chip Features
•Target Technology :90nm - Fujitsu
•Die Size : 2.5mm X 2.5mm
•Gate Count : 250K (no embedded memories)
•Frequency : 2 domains 696MHz, 232MHz
(Sigma Delta: 1.6GHz)
•Team size : 2 verification, 1 Physical Design and
1 DFT engineers, 4 Analog design
engineers, 4 analog layout engineers
•Project Duration : 6 months
DigitalCore DigitalTop
Case Study – 90nm TV Tuner

62. Case Study – 28nm Networking Chip
• Design Parameters
– 28nm TSMC HPM
– 1Ghz Core Clock
– 800 MHz Serdes Logic Clock
– 25G Hz Serdes Internal Freq
– 25mm x 25mm Die Size
– Flip Chip
– 180 SERDES Instances
– 50 unique Blocks
– 140W - Die Power
• Program Size
– PnR : 25 Engineers ( Including Leads )
– 9 Months Execution ( 2 Phases )
– Final Netlist Phase : 2.5 months ( 1.5 months
Blocks, 1 Month Top )
• Methodology
– Full Hierarchical implementation
– Mesh Clock Implementation
– All Feedthrough paths are implements are
repeater islands to isolate the Top & Block
Level dependencies
– Max block Size 3M instance count
– Max IO block size : 1.2M instance count
– Synthesis - DC Topo/DC-SPG
– PnR Implementation – ICC ( IO Blocks ),
Talus (Core Blocks)
– Formal Verification Sign-off : LEC
– Timing / Noise Sign-off : PTSI
– Power Analysis Sign-off : Redhawk
– Physical verification Signoff : calibre
– Vt based Timing / Power recovery
• Sign-off Parameters
– Modes : Core Block : 2 Modes, IO Blocks – 12
Modes
– Timing Corners : 3 – Process, 2 –Temp, 4 –
voltage, 4 – RC, 2- RC Temp
– Setup Fix scenario : 8
– Hold Fix scenario : 9
– Nosie : ff, rcbest, 125C
– OCV : Setup – 10% capture Clock Cells. 10%
capture Clock Nets
• Hold : 15% Launch Clock Cells , 15% Capture Clock
Cells , 20% Launch Clock Nets , 20% capture Clock Netss
– Sign-off Margin : 40ps Hold , 160ps setup
– IR Drop : 60mV ( Dynamic Vector-less worst
case Activity Based Analysis )
– 5% LVT Count

63. Case Study – 16nm FINFET SoC T/C

64. Moving Forward
• Steps being studied and undertaken
– Unified Data Model between the tool vendors - remote chances!!
• Difficult since the algorithms used in the tools are different and cannot be
merged
– Common libraries between the tools
• This step has matured over the last few years and today we have to deal with
LEF and LIB format only
• However, these formats are tool vendor specific - LEF: Cadence and LIB:
Synopsys and are not standards
– Subject to unilateral modifications
• Industry working towards ALF (Advanced Library Format) which is an IEEE
standard - IEEE1603 - 2003
– Models timing, power, SI, synthesis and physical library views
– Manufacturing aware Physical Design
• Design For Manufacturing is the new Mantra!!