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# ATPG Methods and Algorithms

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### ATPG Methods and Algorithms

1. 1. Seminar ATPG Methods and Algorithms Shankardas Deepti Bharat CGB0911002 VSD530 M. Sc. [Engg.] in VLSI System DesignModule Title: Reliable Power Aware ASICs Module Leader: Mr. Padmanaban K . M. S. Ramaiah School of Advanced Studies 1
2. 2. Outline• Introduction• ATPG• Classification• ATPG Methods• ATPG Algorithms• Summary• References M. S. Ramaiah School of Advanced Studies 2
3. 3. ATPG• ATPG enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior based on inputs patters• The generated patterns are used to test semiconductor devices for defects after manufacturing• A defect is an error introduced into a device during the manufacturing process• The effectiveness of ATPG is measured by the amount of modeled defects, or fault models, that are detected and the number of generated patterns.• The effectiveness of ATGP gives an estimate of test quality• A fault model is a mathematical description of how a defect alters design behavior• A fault is said to be detected by a test pattern if, the faulty circuit output differs from the original circuit output M. S. Ramaiah School of Advanced Studies 3
4. 4. ATPGThere are two steps that ATPG should take to detect fault.Fault activation: Establishes a signal value at the fault model site that is opposite ofthe value produced by the fault modelFault propagation: Moves the resulting signal value, or fault effect, forward bysensitizing a path from the fault site to a primary output.Sequential ATPGSearches for a sequence of vectors to detect a particular fault through the space of allpossible vector sequences• Vector Sequence: A sequence of values for circuit input• In Sequential Circuits due to the presence of memory elements, the controllability and observability of the internal signals (in general)are much more difficult than those in a combinational circuit• Complexity of sequential ATPG much higher than that of combinational ATPG M. S. Ramaiah School of Advanced Studies 4
5. 5. Major classificationMajor classifications of methods• Pseudorandom• Ad-Hoc• Algorithmic• Pseudorandom Figure 1. Fault coverage vs. test vectors Generates an input vector using a pseudorandom number generator and perform fault simulation to determine if it detects the target fault.• Ad-Hoc Re-fault simulation and repeating until desired fault coverage is achieved, determining the locations of undetected faults. No special test generation system is required, only fault simulator Both have a disadvantage that it consumes more time for synthesized designs M. S. Ramaiah School of Advanced Studies 5
6. 6. Algorithmic Methods• Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity• Many different ATPG methods have been developed to address combinatorial and sequential circuitsSome examples: • Pseudorandom test generation is the simplest method of creating tests. It uses a pseudorandom number generator to generate test vectors • The D Algorithm was the first practical test generation algorithm in terms of memory requirements. The D Algorithm introduced D Notation which continues to be used in most ATPG algorithms. • Fan-Out Oriented Algorithm: It limits the ATPG search space to reduce computation time and accelerates backtracing M. S. Ramaiah School of Advanced Studies 6
7. 7. Algorithms of ATPG• Path Sensitization• Boolean Difference methods• D-Algorithm Combinational Circuits• PODEM• Fan• Tupert-Shofer• State Table verification approach Sequential Circuits M. S. Ramaiah School of Advanced Studies 7
8. 8. D - Algorithm Two Approaches Algebraic Structural approaches approachesD notationD=“1” normal & “0” faultD = “0” presence of fault & “1” normalD Algorithm1. Excitation2. D-drive3. Justification4. Back track whenever required M. S. Ramaiah School of Advanced Studies 8
9. 9. D – Algorithm1 4 72 Propagations paths for test error 5 9 •5 8 9 8 •5 7 9 3 6 Test for struck at fault=1 Table 1. D-Algorithm illustration Step 1 2 3 4 5 6 7 8 9 NodesInitial 1 0 D5 8 1 0 D 0 D D-drive8 9 1 0 D 0 1 D DJustification Due to inconsistency on the nodes 1 &4 7 1 0 0 D 0 1 D D 2, backtracking is necessary. Now,3 6 1 0 1 0 D 0 1 D D instead of propagating the error through 5,8,9 ;choose a different path1,2 4 0 0 1 0 D 0 1 D D i.e. 5,7,9. M. S. Ramaiah School of Advanced Studies 9
10. 10. Back track & Retry Table 2. Backtracking Step 1 2 3 4 5 6 7 8 9 1Initial 1 0 D 4 7 25 7 1 0 1 D D 9 57 9 1 0 1 D D 1 D 8Justification6 8 1 0 1 D 1 D 1 D 3 63 6 1 0 0 1 D 1 D 1 D Test for struck at1,2 4 1 0 0 1 D 1 D 1 D fault=1 • NO inconsistency, as value on nodes 1 & 2 match initial values set on the nodes. Hence, we have a test value of 1,0,0 D- Algorithm acts like search algorithm until it finds a test pattern, thus an iterative process M. S. Ramaiah School of Advanced Studies 10
11. 11. PODEMDeveloped in 1981 by geol to address the problem of D-algorithm had with XOR/XNOR gates• D-algorithm is exponentially complex to the number of internal circuits nodes- XOR gates makes complexity of the D-algorithm approach this limitation• PODEM express the search space in terms of assignments to the primary inputs only• It is also a branch- and - bound algorithm which is exponentially complex to the number for circuit inputs- usually a much smaller number than circuit nodes• Repetitive process-branching• If inconsistency found –bounding M. S. Ramaiah School of Advanced Studies 11
12. 12. Initial: Stuck-at-1 fault at 5Backward tracing and X1=0 Table 3. PODEM illustration 1 2 3 4 5 6 7 8 9 10 11 12 0 X X X X X X X X X X X X1X2X3X4=0XXX not a test set Assign X2=0 1 2 3 4 5 6 7 8 9 10 11 12 0 0 X X D X X X X X X X M. S. Ramaiah School of Advanced Studies 12
13. 13. FAN• FAN algorithm is an improvised version of PODEM designed to utilize circuits topology information to increase search efficiency• D-algorithm and PODEM gives problem with area of re-convergent fan out• Re-convergent fan out can cause complex interactions between internal circuits nodes Figure 2. FAN illustration The requirement for M<=1 to Propagate the D value through the AND gate cause R to be set to 1 which terminates the propagation path M. S. Ramaiah School of Advanced Studies 13
14. 14. How Patterns are generated? M. S. Ramaiah School of Advanced Studies 14
15. 15. Table 4. Types of algorithms Algorithm Estimated speedup over D-algorithm Year D-ALG 1 1966 PODEM 7 1981 FAN 23 1983 TOPS 292 1987 SOCRATES 1574(ATPG system) 1988Waicukauski et,al. 2189(ATPG system) 1990 EST 8765(ATPG system) 1991 TRAN 3005(ATPG system) 1993Recursive learning 485 1995Tafer-shofer et.al 25057 1997 M. S. Ramaiah School of Advanced Studies 15
16. 16. Sequential Circuits Test Generation Primary . . Combinational . . . Primary . . . inputs Logic outputs Present Next state State F/F Figure 3. Sequential test generation• Combinational logic testing• Abstract behaviour of the machine in terms of its state transition graph(STG)is also used• Problem occurs when the test vector depends on present state lines or the fault effect is propagated to the next state lines M. S. Ramaiah School of Advanced Studies 16
17. 17. Sequential AlgorithmsConcurrent Test (CONTEST) algorithmTest generation process can be subdivided into three phases:Phase 1• Initialization vectors are generated• Here, the cost is defined as the number of flip flops that are in the unknown state• To start the process, any trial vector (a randomly generated or user-supplied vector) can be used• After simulation of a trial vector, the “trial cost” is computed as the number of flip-flops that are in the unknown state• If trail cost < current cost, then vector is saved else a new trail vector is usedPhase 2: Application of test vectors supplied by the designer or generated in Phase 1Phase 3: This phase is initiated only if Phase 2 doesn‟t meet required fault coverage. Here, test vectors are generated for single faults targeted one at a time M. S. Ramaiah School of Advanced Studies 17
18. 18. Genetic algorithm• Improved results are possible if trial vectors are generated by some “learning” process• The cost function is replaced by a fitness function in genetic algorithm which makes the generation of trail vectors more efficient• The procedure works with a set of vector sequences, called the population, which is improved iteratively resulting in a new generation for each iteration• Vectors of a generation are produced from those of the previous generation, using operations known as crossover, mutation, and selection• The fitness of the new generation is evaluated by simulation of the required characteristics such as initialization or fault detection M. S. Ramaiah School of Advanced Studies 18
19. 19. Summary• Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity• Many different ATPG methods have been developed to address combinatorial and sequential circuits ATPG can fail to find a test for a particular fault in at least two cases:  The fault may be undetectable  It is possible that a pattern(s) exist, but the algorithm cannot find it M. S. Ramaiah School of Advanced Studies 19
20. 20. References[1] Wang, Wu and Wen (2006) VLSI Test Principles and Architectures: Design for Testability. San Francisco: Morgan Kaufmann Publishers[2] Bushnell and Agrawal (2002) Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. New York: Kluwer Academic Publishers[3] Kwang-Ting Cheng, „Gate-Level Test Generation for Sequential Circuits‟, ACM Transactions on Design Automation of Electronic Systems, 4(1), Oct 1996 M. S. Ramaiah School of Advanced Studies 20
21. 21. Thank YouM. S. Ramaiah School of Advanced Studies 21