The document summarizes the architecture and components of the 8085 microprocessor. It discusses the central processing unit (CPU) which contains the arithmetic logic unit (ALU) for arithmetic and logical operations, and register unit for temporarily storing data. The register unit contains general purpose registers and special purpose registers like the program counter, stack pointer, and flag registers. It also describes the address bus, data bus, and control bus. The document outlines the different types of interrupts in the 8085 like software interrupts, trap, and hardware interrupts like RST 7.5, RST 6.5, RST 5.5 and their priorities.

1. PRINCIPLES OF 8085
MICROPROCESSOR
Dr.S.Barani
School of Electrical and Electronics Engineering
Sathyabama Institute of Science and Technology
Week 1 – Introduction to Microprocessor

2. ARCHITECTURE OF A MICROPROCESSOR

3. CENTRAL PROCESSING UNIT CPU
ALU (Arithmetic and Logic Unit)
•Performs Arithmetic and Logical operations
REGISTER UNIT
•Registers are used primarily to store data temporarily during the
execution of a program.
•Few registers are accessible to the uses through instructions
•General Purpose Registers - B, C, D, E, H & L (8 bit registers)
•er)
3

4. •Can be used singly or can be used as 16 bit register pairs BC, DE,
HL
•H & L can be used as a data pointer (holds memory address)
•Special Purpose Registers Accumulator (8 bit regist
CONTROL UNIT
•Provides necessary timing & control signals necessary to all the
operations
•Controls the flow of data
CENTRAL PROCESSING UNIT CPU Contd...
4

5. ADDRESS BUS
• It is a group of wires or lines that are used to transfer the
addresses of Memory or I/O devices. It is unidirectional.
• 16 bits.
• Multiplexed with 8 bit data bus.
• Most significant bits (MSB) of address goes through Address bus
(A7-A0)
• LSB goes through multiplexed data bus (AD0-AD7).
ADDRESS BUS
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6. Data Bus
• Transfer data within
Microprocessor and
Memory/Input or Output
devices.
• Bidirectional
• 8 Bits long
Control Bus
• Control signals are Read,
Write and Opcode fetch etc.
• Dedicated bus, because all
timing signals are generated
according to control signal.
DATA AND CONTROL BUS
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7. REGISTERS
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8. 8 bit register
shows the status of the
microprocessor
before/after an operation
❑ S (sign flag)
❑ Z (zero flag)
❑ AC (auxillary carry flag)
❑ P (parity flag)
❑ CY (carry flag) D7
FLAG REGISTERS
8

9. The program counter PC
❑ This is a register that is
used to control the
sequencing of the
execution of instructions.
❑ This register always holds
the address of the next
instruction.
❑ Since it holds an address,
it must be 16 bits wide.
The Stack pointer
The stack pointer is also a 16-
bit register that is used to point
into memory.
Points to is a special area
called the stack.
The stack is an area of
memory used to hold data that
will be retreived soon.
The stack is usually accessed
in a Last In First Out (LIFO)9

10. INTERRUPTS
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11. CLASSIFICATION OF INTERRUPTS
An interrupt is a signal
initiated by an external
device to the
microprocessor. Once this
signal is received, the
microprocessor completes
the execution of the current
instruction and responds to
the interrupt
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12. The software interrupts are
program instructions. When the
instruction is executed, the
processor executes an interrupt
service routine stored in the
vector address of the software
interrupt instruction.
The software interrupts are RST 0,
RST 1, RST 2, RST 3, RST 4, RST 5,
RST 6 and RST 7.
SOFTWARE INTERRUPTS OF 8085
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13. TRAP
❑ This interrupt is a Non-Maskable interrupt (NMI). It is unaffected
by any mask or interrupt enable.
❑ TRAP is the highest priority and vectored interrupt(as vector
address is fixed i.e. memory location where to transfer control).
❑ TRAP interrupt is edge and level triggered. This means hat the
TRAP must go high and remain high until it is acknowledged.
❑ In sudden power failure, it executes a ISR and send the data
from main memory to backup memory.
HARDWARE INTERRUPTS OF 8085
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14. HARDWARE INTERRUPTS OF 8085
RST 7.5
•The RST 7.5 interrupt is a Maskable interrupt.
• It has the second highest priority.
•It is edge sensitive. i.e. Input goes to high and no need to maintain high state
until it recognized.
RST 6.5 & RST 5.5
•The RST 6.5 and RST 5.5 both are level triggered (i.e.) Input goes to high and stay
high until it recognized.
•Maskable interrupt.
•The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR 14

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