It contains file for Cad of Electronics lab. it have 5 practicals written with its vhdl code and test bench

1. INDEX
S.NO. DESCRIPTION PAGE NO. SIGNATURE
1 Design, simulation and analysis of
two input NAND and NOR gate.
2
2 Design, simulation and analysis of
Full Adder circuit.
8
3 Design, simulation and analysis of
4:1 multiplexer.
13
4 Design, simulation and analysis of
1-bit comparator.
22
5 Design, simulation and analysis of
up-down counter.
29

2. Program 1
Aim: Design, simulation and analysis of two input NAND and NOR gate.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 3GB RAM,300 GB hard disk
Theory:
NAND gate: This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.
The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents inversion.
NOR gate: This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a
small circle on the output. The small circle represents inversion.
VHDL code for implementing logic gates using data flow modeling:
Nand gate-
--author @rajeev_kumar
--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
--ENTITY DECLARATION: name, inputs, outputs
entity nandGate is
port( A, B : in std_logic;
F : out std_logic);
end nandGate;
--FUNCTIONAL DESCRIPTION: how the NAND Gate works
architecture func of nandGate is
begin
F <= A nand B;
end func;
Nor gate-
--author @rajeev_kumar
--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
--ENTITY DECLARATION: name, inputs, outputs
entity norGate is
port( A, B : in std_logic;
2

3. F : out std_logic);
end norGate;
--FUNCTIONAL DESCRIPTION: how the NOR Gate works
architecture func of norGate is
begin
F <= A nor B;
end func;
RTL schematic diagram :
NAND gate:
Truth Table:
3

4. NOR gate:
Truth Table:
Test Bench: A testbench is a program that defines a set of input signals to verity the
operation of a circuit.
1) The testbench takes no inputs and returns no outputs. As such the ENTITY
declaration is empty.
2) The circuit under verification, is imported into the testbench ARCHITECTURE as a
component.
4

5. Nand gate
--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
--ENTITY DECLARATION: no inputs, no outputs
entity nandGate_tb is
end nandGate_tb;
-- Describe how to test the NAND Gate
architecture tb of nandGate_tb is
--pass nandGate entity to the testbench as component
component nandGate is
port( A, B : in std_logic;
F : out std_logic);
end component;
signal inA, inB, outF : std_logic;
begin
--map the testbench signals to the ports of the nandGate
mapping: nandGate port map(inA, inB, outF);
process
--variable to track errors
variable errCnt : integer := 0;
begin
--TEST 1
inA <= '0';
inB <= '0';
wait for 15 ns;
assert(outF = '1') report "Error 1" severity error;
if(outF /= '1') then
errCnt := errCnt + 1;
end if;
--TEST 2
inA <= '0';
inB <= '1';
wait for 15 ns;
assert(outF = '1') report "Error 2" severity error;
if(outF /= '1') then
errCnt := errCnt + 1;
end if;
--TEST 3
inA <= '1';
inB <= '1';
wait for 15 ns;
assert(outF = '0') report "Error 3" severity error;
if(outF /= '0') then
errCnt := errCnt + 1;
end if;
-------------- SUMMARY -------------
if(errCnt = 0) then
assert false report "Good!" severity note;
5

6. else
assert true report "Error!" severity error;
end if;
end process;
end tb;
--------------------------------------------
configuration cfg_tb of nandGate_tb is
for tb
end for;
end cfg_tb;
Nor gate
--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
--ENTITY DECLARATION: no inputs, no outputs
entity norGate_tb is
end norGate_tb;
-- Describe how to test the NOR Gate
architecture tb of norGate_tb is
--pass norGate entity to the testbench as component
component norGate is
port( A, B : in std_logic;
F : out std_logic);
end component;
signal inA, inB, outF : std_logic;
begin
--map the testbench signals to the ports of the norGate
mapping: norGate port map(inA, inB, outF);
process
--variable to track errors
variable errCnt : integer := 0;
begin
--TEST 1
inA <= '0';
inB <= '0';
wait for 15 ns;
assert(outF = '1') report "Error 1" severity error;
if(outF /= '1') then
errCnt := errCnt + 1;
end if;
--TEST 2
inA <= '0';
inB <= '1';
wait for 15 ns;
assert(outF = '0') report "Error 2" severity error;
if(outF /= '0') then
6

7. errCnt := errCnt + 1;
end if;
--TEST 3
inA <= '1';
inB <= '1';
wait for 15 ns;
assert(outF = '0') report "Error 3" severity error;
if(outF /= '0') then
errCnt := errCnt + 1;
end if;
-------------- SUMMARY -------------
if(errCnt = 0) then
assert false report "Good!" severity note;
else
assert true report "Error!" severity error;
end if;
end process;
end tb;
--------------------------------------------
configuration cfg_tb of norGate_tb is
for tb
end for;
end cfg_tb;
Simulation waveform:
7

8. Program 2
Aim: Design, simulation and analysis of Full Adder circuit.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 3GB RAM,300 GB hard disk
Theory:
A full adder adds binary numbers and accounts for values carried
in as well as out. A one-bit full adder adds three one-bit
numbers, often written as A, B, and Cin; A and B are the operands,
and Cin is a bit carried in from the next less significant stage.
The full-adder is usually a component in a cascade of adders,
which add 8, 16, 32, etc. binary numbers. The circuit produces a
two-bit output, output carry and sum typically represented by the
signals C out and S,where
SUM = 2*Cout + S
VHDL code for implementing full adder:
--author @rajeev_kumar
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
8

9. sum : out STD_LOGIC;
carry : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
begin
sum<=a xor b xor cin;
carry<=(a and b)or(a and cin)or(b and cin);
end Behavioral;
RTL Schematic Diagram for implementing full adder:
9

10. Technology Schematic Diagram for implementing full adder:
For Sum:
10

11. Truth Table:
For Carry:
11

12. Truth Table:
Test Bench for implementing full adder:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY full_adder_tb_vhd IS
END full_adder_tb_vhd;
ARCHITECTURE behavior OF full_adder_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT full_adder
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
12

13. carry : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL cin : std_logic := '0';
--Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: full_adder PORT MAP(
a => a,
b => b,
cin => cin,
sum => sum,
carry => carry);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
-- Place stimulus here
a<='0','1' after 100ns,'0' after 200ns;
b<='0','1' after 50ns,'0' after 100ns,'1' after 150ns;
cin<='0','1' after 50ns,'0' after 150ns,'1' after 200ns;
wait; -- will wait forever
END PROCESS;
END;
13

14. Simulation Waveform for Full Adder:
14

15. Program 3
Aim: Design, simulation and analysis of 4:1 multiplexer.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 3GB RAM, 300GB hard disk
Theory:
In electronics, a multiplexer ( or mux ) is a device that selects
one of several analog or digital input signals and forwards the
selected input into a single line. A multiplexer of 2 n inputs has
n select lines, which are used to select which input line to send
to the output. Multiplexers are mainly used to increase the amount
of data that can be sent over the network within a certain amount
of time and bandwidth. A multiplexer is also called a data
selector. An electronic multiplexer makes it possible for several
signals to share one device or resource, for example one A/D
converter or one communication line, instead of having one device
per input signal.
4:1 Multiplexer
15

16. VHDL code for implementing 4:1 multiplexer
--author @rajeev_kumar
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux4to1 is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end mux4to1;
architecture Behavioral of mux4to1 is
begin
process(i0,i1,i2,i3,s0,s1)
begin
if(s1='0' and s0='0') then
y<=i0;
elsif(s1='0' and s0='1') then
y<=i1;
16

17. elsif(s1='1' and s0='0') then
y<=i2;
else
y<=i3;
end if;
end process;
end Behavioral;
RTL Schematic Diagram for implementing 4:1 multiplexer:
17

18. Technology Schematic Diagram for implementing 4:1
multiplexer:
18

19. Test bench for 4:1 multiplexer:
HDL Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
19

20. USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY pgm3_tb_vhd IS
END pgm3_tb_vhd;
ARCHITECTURE behavior OF pgm3_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pgm3
PORT(
i0 : IN std_logic;
i1 : IN std_logic;
i2 : IN std_logic;
i3 : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL i0 : std_logic := '0';
SIGNAL i1 : std_logic := '0';
SIGNAL i2 : std_logic := '0';
SIGNAL i3 : std_logic := '0';
SIGNAL S0 : std_logic := '0';
SIGNAL S1 : std_logic := '0';
--Outputs
SIGNAL Y : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
20

21. uut: pgm3 PORT MAP(
i0 => i0,
i1 => i1,
i2 => i2,
i3 => i3,
S0 => S0,
S1 => S1,
Y => Y
);
tb : PROCESS
BEGIN
-- Place stimulus here
i0<='0','1' after 50ns, '0' after 100ns;
i1<='0','1' after 100ns, '0' after 150ns, '1' after 200ns;
i2<='0','1' after 50ns, '0' after 100ns;
i3<='0','1' after 50ns, '0' after 100ns, '1' after 200ns;
S0<='0','1' after 150ns, '0' after 200ns;
S1<='0','1' after 50ns, '0' after 100ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation waveform for 4:1 multiplexer:
21

22. Program 4
Aim: Design, simulation and analysis of 1-bit comparator.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 3GB RAM,300 GB hard disk
Theory:
A digital comparator or magnitude comparator is a hardware
electronic device that takes two numbers as input in binary form
and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central
processing units (CPUs) and microcontrollers (MCUs). The operation
of a single bit digital comparator can be expressed as a truth
table:
VHDL code for implementing 1-bit comparator
--author @rajeev_kumar
22

23. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity com is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
agb : out STD_LOGIC;
aeb : out STD_LOGIC;
alb : out STD_LOGIC);
end com;
architecture Behavioral of com is
begin
process(a,b)
begin
if(a>b)then
agb<='1';
aeb<='0';
alb<='0';
elsif(a=b) then
agb<='0';
aeb<='1';
alb<='0';
elsif(a<b) then
23

24. agb<='0';
aeb<='0';
alb<='1';
end if;
end process;
end Behavioral;
RTL schematic diagram for 1-bit comparator:
24

25. Technology schematic diagram for 1-bit comparator:
Truth Table:
25

26. 26

27. Test Bench for implementing 1-bit comparator:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY com_tb_vhd IS
END com_tb_vhd;
ARCHITECTURE behavior OF com_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT com
PORT(
a : IN std_logic;
b : IN std_logic;
agb : OUT std_logic;
aeb : OUT std_logic;
alb : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
--Outputs
SIGNAL agb : std_logic;
SIGNAL aeb : std_logic;
SIGNAL alb : std_logic;
BEGIN
27

28. -- Instantiate the Unit Under Test (UUT)
uut: com PORT MAP(
a => a,
b => b,
agb => agb,
aeb => aeb,
alb => alb
);
tb : PROCESS
BEGIN
-- Place stimulus here
a<='0','1' after 20ns,'0' after 100ns,'1' after 150ns;
b<='0','1' after 20ns,'0' after 80ns,'1' after 120ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation Waveform for 1-bit comparator :
28

29. Program 5
Aim: Design, simulation and analysis of up-down counter.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 3GB RAM,300 GB hard disk
Theory:
The similarities between the implementation of a binary up counter
and a binary down counter leads to the possibility of a binary
up/down counter, which is a binary up counter and a binary down
counter combined into one. Since the difference is only in which
output of the flip-flop to use, the normal output or the inverted
one, we use two AND gates for each flip-flop to "choose" which of
the output to use.
From the diagram, we can see that COUNT-UP and COUNT-DOWN are used
as control inputs to determine whether the normal flip-flop
outputs or the inverted ones are fed into the J-K inputs of the
following flip-flops. If neither is at logic level 1, the counter
doesn't count and if both are at logic level 1, all the bits of
the counter toggle at every clock pulse. The OR gate allows either
of the two outputs which have been enabled to be fed into the next
flip-flop. As with the binary up and binary down counter, the
speed up techniques apply.
3-Bit Synchronous Up-Down Counter
29

30. VHDL code for implementing up-down counter using
behavioral modeling:
--author @rajeev_kumar
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity up_dc is
Port ( pr : in STD_LOGIC;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
t : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (2 downto 0));
end up_dc;
architecture Behavioral of up_dc is
function "+"(a,b:bit_vector(0 to 2)) return bit_vector is
variable cout:bit;
variable cin: bit:='0';
variable sum: bit_vector(0 to 2):="000";
begin
for i in 0 to 2 loop
cout:=(a(i) and b(i)) or (b(i) and cin) or (a(i) and cin);
sum(i):=a(i) xor b(i) xor cin;
cin:= cout;
30

31. end loop;
return sum;
end"+";
begin
process(clk,pr,clr)
begin
if(pr='0' and clr='1') then
q<="111";
elsif (pr='1' and clr='0') then
q<="000";
elsif(pr='1' and clr='1' and clk='0' and clk' event) then
q<=q+ "100";
end if;
end process;
end Behavioral;
RTL schematic diagram for up-down counter:
31

32. 32

33. Technology schematic diagram for up-down counter:
33

34. Test Bench for implementing up-down counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY up_dc_tb_vhd IS
END up_dc_tb_vhd;
ARCHITECTURE behavior OF up_dc_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT up_dc
PORT(
pr : IN std_logic;
clr : IN std_logic;
clk : IN std_logic;
t : IN std_logic;
q : INOUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL pr : std_logic := '0';
SIGNAL clr : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL t : std_logic := '0';
--BiDirs
SIGNAL q : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
34

35. uut: up_dc PORT MAP(
pr => pr,
clr => clr,
clk => clk,
t => t,
q => q
);
tb : PROCESS
BEGIN
-- Place stimulus here
clk<='1', '1' after 100ns,'0' after 150ns;
pr<='0', '1' after 200ns, '0' after 250ns;
clr<='0' ,'1' after 80ns, '0' after 100ns;
t<='0', '1' after 100ns,'0' after 200ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation waveform for up-down counter :
35

36. 36