1. Enumerated Types
The first style is used most often to define cases or states
for a state machine
type CAR_STATE is (back, stop, slow, medium, fast);
VHDL also allows users to create subtypes of a type
The values in the subtype must be a contiguous range of values
of the base type from start to end
Subtype GO_KART is CAR_STATE range stop to medium;
VHDL has two predefined integer subtypes
Subtype natural is integer range 0 to highest integer;
Subtype positive is integer range 1 to highest integer;
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2. Enumerated Types
BIT – can be ‘0’ or ‘1’ (note single quotes)
STD_LOGIC IEEE std_logic_1164 package
Has NINE legal values:
‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’
Example Subtype Declarations
Subtype twoval_logic is std_logic range ‘0’ to ‘1’;
Subtype fourval_logic is std_logic range ‘X’ to ‘Z’;
Subtype negint is integer range -2147483647 to -1;
Subtype bitnum is integer range 31 downto 0;
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3. Constants
They contribute to readability, maintainability and
portability of programs in any language
The syntax is as shown
constant BUS_SIZE: integer := 32; --
width of component
constant MSB: integer := BUS_SIZE - 1; --
bit number of MSB
constant Z: character := ‘Z’; -- synonym
for Hi-Z value
The value of a constant can be a simple expression
Constants can be used anywhere the corresponding value
can be used and they can be put to good use in type
definitions
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4. Arrays
Another very important category of user-defined types
Ordered set of elements of the same type, where each element is
selected by an array index
Syntax for VHDL array definitions
type type-name is array (start to end) of element-type;
type type-name is array (start downto end) of element-
type;
type type-name is array (range-type) of element-type;
type type-name is array (range-type range start to end)
of element-type;
type type-name is array (range-type range start downto
end) of element-type;
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5. Array declarations
type monthly_count is array (1 to 12) of integer;
type byte is array (7 downto 0) of STD_LOGIC;
constant WORD_LEN: integer := 32;
type word is array (WORD_LEN - 1 downto 0) of STD_LOGIC;
constant NUM_REGS: integer := 8;
type reg_file is array ( 1 to NUM_REGS ) of word;
type traffic_light_state is (reset, stop, wait, go);
type statecount is array (traffic_light_state) of integer;
Array elements are considered to be ordered from left to right in
the same direction as index range
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6. Array declarations
type monthly_count is array (1 to 12) of integer; 1
type byte is array (7 downto 0) of STD_LOGIC; 7
Constant WORD_LEN: integer := 32;
type word is array (WORD_LEN - 1 downto 0) of STD_LOGIC; 31
Constant NUM_REGS: integer := 8;
type reg_file is array ( 1 to NUM_REGS ) of word; 1
Type traffic_light_state is (reset, stop, wait, go);
type statecount is array (traffic_light_state) of integer;
reset
Left most elements of arrays are shown in blue
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7. Array elements and literals
Within VHDL program statements, individual array elements
are accessed using the array name and the element’s index in
parentheses.
If M, B, W, R, and S are signals of variables of the five array
types defined in the previous slides then M(11), B(5),
W(WORD_LEN – 5), R(0,0), R(0) and S(reset) are all valid
elements.
Array literals can be specified by listing the element values in
parentheses. The byte variable B could be set to all ones by the
statement
B := (‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’);
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8. Array elements and literals
VHDL also has a shorthand notation that allows you to specify
values by index.
To set word variable W to all ones except for zeroes in the LSB
of each byte
W := (0 => ‘0’, 8 => ‘0’, 16 => ‘0’, 24 => ‘0’, others => 1);
The methods work for arrays with any element type, but the
easiest way to write a literal of type STD_LOGIC is to use a
“string”
VHDL string is an array of ISO characters enclosed in double
quotes such as “Hello”
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9. String
A string is just an array of characters.
A STD_LOGIC array of a given length can be
assigned the value of a string of the same length, as
long as the characters in the string are taken from the
set of nine characters defined as the possible values of
the STD_LOGIC elements like ‘0’, ‘1’, ‘U’
The two previous examples can be rewritten as
B := “11111111”;
W := “11111110111111101111111011111110”;
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11. Entity Declaration for LogicFcn
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is
port (
A
A: in std_logic; B Y
B: in std_logic; C
C: in std_logic;
Y: out std_logic
);
end entity LogicFcn;
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12. Parts of Architecture Body
architecture ARCH_NAME of ENTITY_NAME is
<declarative section : list internal signals, variables,
and components here. For each component used
show the port map, (unless port map defined is in a
“package”) >
begin
<statement section : all concurrent statements and
components and processes in this section execute at
the same time, NOT sequentially>
end ARCH_NAME;
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13. Architecture Body
Specifies the internal circuit of an entity, using any
one of the following modeling styles:
1. As a set of interconnected components, as wired
(called structural modeling)
2. As a set of concurrent signal assignment
statements (called dataflow modeling)
3. As a set of sequential assignment statements,
i.e., a “process” (called behavioral modeling)
4. As any combination of the above (called mixed
modeling)
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14. Architecture Body (Dataflow)
With a signal assignment statement:
architecture dataflow of LogicFcn is
begin
Y <= (not A and not B) or C;
end dataflow;
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15. Architecture Body (Dataflow)
With a conditional signal assignment statement:
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
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16. Architecture Body (Behavioral)
architecture behavioral of LogicFcn is
“Label:”
begin Sensitivity List - The Process will
be executed anytime there is an
Name of fcn: process (A,B,C) EVENT (change of state) on one of
process these signals.
begin
wait on A,B,C; WAIT ON statement - has same
effect as sensitivity list.
if (A = '0' and B = '0') then CANNOT USE BOTH.
Processes with WAIT statements
Y <= '1'; cannot have sensitivity lists !!
process elsif C = '1' then
Y <= '1'; Statements within Processes are
executed sequentially. (This is a
else single IF statement)
The process, however, executes
Y <= '0'; concurrently with other processes
and concurrent statements in the
end if; architecture.
end process;
end behavioral;
Values are assigned to signals when process suspends
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17. Architecture Body (Structural)
Internal signals are LOCAL to the Architecture, and cannot
be seen outside it !
signals
notA
A andSignal
B notB
C Y
entity architecture
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18. Architecture Body (Structural)
architecture structural of LogicFcn is LOCAL SIGNALS are
COMPONENT signal notA, notB, andSignal: std_logic; declared within the
declarations begin architecture and they
may go here i1: inverter port map (i => A,
have no MODE (IN,
OUT, etc.)
o => notA);
i2: inverter port map (i => B,
o => notB); These are
a1: and2 port map (i1 => notA, COMPONENT
i2 => notB, INSTANTIATIONS
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
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19. Components for Structural Model
library IEEE; component OR2 port (
use IEEE.std_logic_1164.all; i1: in std_logic;
package primitive is i2: in std_logic;
component AND2 port ( y: out std_logic
i1: in std_logic; );
i2: in std_logic; end component;
y: out std_logic component INVERTER port (
); i: in std_logic;
end component; o: out std_logic
);
end component;
end primitive;
these are component declarations
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