The document describes designing and simulating sequential circuits using Verilog HDL. It discusses creating a counter, PRBS generator, and accumulator. The procedure involves using Xilinx ISE software to write the Verilog code for each circuit and its test bench. The code is synthesized, simulated, and the waveforms are observed to verify the circuit behavior.

1. Ex. No: 2 DESIGN AND SIMULATION OF SEQUENTIAL CIRCUITS
USING VERILOG HDL
AIM:
To design the following sequential circuits and simulate them by creating the test benches
•Counter
•PRBS Generator
•Accumulator
SOFTWARE REQUIRED:
•Xilinx 13.4 ISE– A project navigator software tool
PROCEDURE:
•Double click Xilinx ISE Design Suite 13.4 on the desktop or Go to Start–> All programs
–>Xilinx ISE Design Suite 13.4->ISE Design tools.
•Click on File –> New project. A new project wizard will open. Type the name of the project
and select the location. The top-level source type should be selected as HDL. Click next.
•A new project wizard opens.
Product category :All
Family :Spartan 6
Device :XC6SLX45
Package :CSG324
Speed :-2
Top-level source type :HDL
Synthesis tool :XST(VHDL/Verilog)
Simulator :Isim(VHDL/Verilog)
Preferred language :Verilog
•Click next–>finish–>Right click on the project name shown in hierarchy and select new
source.
•New source wizard open. Select Verilog module and give program name as the file name
and click next and finish.
•Write the program and save it.
•In the process tab click on ‘+’ sign of synthesis and double click on check syntax.
•In the hierarchy tab right click on the program and select new source.
•In the opened new source wizard select Verilog test fixture and then give file name and click
next and select the associate source and click next and then finish.
•Write the test bench code save it and select the simulation in design tab.
•Select the test bench file in hierarchy tab and in process tab click on ‘+’ sign of Isim
simulator and double click on simulate behavioral model .The waveform displays.
•Save the waveform.
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

2. CODING:
Date: a) COUNTER
Verilog Code:
module counter(clk,reset,count);
input clk,reset;
output [3:0] count;
wire clk,reset;
reg [3:0] count;
always @ (posedge clk)
begin
if(!reset)
count=4'b0000;
else
count=count+4'b1;
end
endmodule
Testbench:
module countertb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] count;
// Instantiate the Unit Under Test (UUT)
counter uut (
.clk(clk),
.reset(reset),
.count(count)
);
initial begin
$display("timet clk reset count");
$display("%gt %b %b %b %b",$time,clk,reset,count);
// Initialize Inputs
clk=1;
#50 reset=1;
#70 reset=0;
#50 reset=1;
#50 $finish;
end
always
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

3. begin
#10 clk=~clk;
end
endmodule
Waveform:
Date: b) PRBS GENERATOR
Verilog Code:
module prbs(rand,clk,reset);
input clk,reset;
output rand;
reg [3:0] temp;
always @ (posedge reset)
begin
temp=4'hF;
end
always @(posedge clk)
begin
if(~reset)
begin
temp<={temp[0]^temp[1],temp[2],temp[3]};
end
end
assign rand=temp[0];
endmodule
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

4. Testbench:
module prbstb;
// Inputs
reg clk;
reg reset;
// Outputs
wire rand;
// Instantiate the Unit Under Test (UUT)
prbs uut (
.rand(rand),
.clk(clk),
.reset(reset)
);
initial
forever
begin
// Initialize Inputs
clk = 0;
#20 clk=1;
#20 clk=0;
end
initial
forever
begin
// Initialize Inputs
reset = 0;
#80 reset=1;
#50 reset=0;
end
endmodule
Waveform:
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

5. Date: c) ACCUMULATOR
Verilog Code:
module accu (in, acc, clk, reset);
input [7:0] in;
input clk, reset;
output [7:0] acc;
reg [7:0] acc;
always@(posedge clk)
begin
if(reset) acc<= 0;
else acc<=acc+in;
end
endmodule
Testbench:
module accu_tb;
reg clk, reset;
reg [7:0] in;
wire [7:0] out;
accu accu1(in, out, clk, reset);
initial
begin
clk =1'b0;
forever
begin
#5 clk = ~clk;
end
end
initial
begin
#50 $finish;
end
initial
begin
#10 reset<=1;
in<=1;
#10 reset<=0;
#10 reset<=1;
in<=4;
#10 reset<=1;
in<=3;
#10 reset<=0;
#10 reset<=1;
end
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

6. endmodule
Waveform:
RESULT:
The Verilog code for sequential circuits were designed, simulated and waveforms were
generated using test bench.
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE