EELE 5331 Digital ASIC DesignLab ManualDr. Yushi Zhou.docx
Lab 4 final report
1. Laboratory #4:
The Simple Processor
Kyle Villano, Tim Kindervatter and Ian Patel
ELC 363-02
Dr. Jesson
The College of New Jersey
November 12th, 2014
2. Table of Contents
Introduction..................................................................................................................................... 3
Problem Description ....................................................................................................................... 3
Materials and Procedure.................................................................................................................. 4
Results............................................................................................................................................. 4
Discussion....................................................................................................................................... 6
Conclusion ...................................................................................................................................... 7
Appendix......................................................................................................................................... 9
Introduction
3. In this lab we used Xilinx ISE to create a simple processor. This processor needed to
perform a variety of different functions, including not, add, jump, load accumulator and store and
clear accumulator processes, among others. We also needed to split up our code into four distinct
sections that dealt with the datapath, ALU, controller, and the actual processor module itself. In
order to do this, we wrote code in Verilog that would be able to define and implement these
various processes. Once the code was written, we used built-in features of ISE to simulate the
output of the processor and confirm that it indeed functioned in the desired manner. After
completing the design of the modules related to our simple processor, we concluded our work by
instantiating a test bench and using it to run a simulation that showed the actual outputs of the
code, which verified that we had indeed satisfied the original tasks of the lab.
Problem Description
The primary task of this lab experiment was to create a simple processor through the
implementation and simulation of Verilog code. In order to accomplish this task, we needed to
focus our work in four distinct sections: the datapath, the ALU, the control values, and the actual
processor module itself. Tables of information regarding control values and function definitions,
along with an overall data path diagram were given in order to aid us in this task. After writing
our code that accurately represented and defined these modules, we needed to verify our results
through the simulation and analysis of the overall ModelSim waveform. In essence, our task
could only be solved by creating, simulating, verifying, and analyzing Verilog code that acted as
a simple processor.
Materials and Procedure
4. Materials Used:
o XILINX ISE 14.2
Procedure:
1. Study the supplied architecture that uses a minimum CPI Von Newman approach.
2. Study the supplied controller flow diagram.
3. Design and code necessary modules.
4. Perform ModelSim simulation of simple processor code to verify project accuracy.
Results
Once we had all of our code working correctly, we used the ModelSim capabilities of
Xilinx to simulate the simple processor. The waveform of this simulation is shown below in
Figures 1 through 3. The processor started operation at time 100ns and ended at 171ns.
Figure 1: Simulation Waveform
5. Figure 2: Simulation Waveform
Figure 3: Simulation Waveform
Looking at the PresentState variable, we could see how the processor would move through the
various states to perform the necessary operations. The state of the accumulator (y variable)
could also be observed to see how each instruction would change the result. For instance, at time
105ns the NOT instruction is processed and the contents of the accumulator changes from all
zeros to all ones.
6. Discussion
In this lab, we were tasked with building a simple processor. This processor required us
to define the behavior of 4 specific components: Datapath, Control, ALU, and Processor.
The datapath is used to define how the processor handles different instructions. Every
instruction set architecture has a certain format to its instructions that is represented as a binary
string. The datapath must be able to recognize these binary strings and send them to different
portions of the hardware so that they can perform different operations. Some of these
destinations include the processor’s registers, the ALU, and memory, among others.
The control portion is used to set various control values that will be used by the datapath.
By reading the initial instruction, the control module sets all the necessary control bits, so that
the other modules can react accordingly to incoming instructions.
The ALU, which stands for Arithmetic Logic Unit, is used to perform arithmetic
operations, such as addition and subtraction, on incoming values. It can be used to perform
operations such as “add,” which simply adds the values contained in two registers and puts it in a
third register. It can also be used to perform operations such as load word, which adds an
immediate value to the value of a register in order to locate a different register, and then load the
value contained in that register. Many other operations require the use of arithmetic operations as
well, which makes the ALU an integral component of the processor.
The processor module was simply a portion of code that tied all of the other components
together and made sure they functioned properly. With each portion working in tandem, we were
able to input a few select instructions and have to processor implement them accordingly.
The main difficulty with this lab was actually get started and figuring out how all the
modules would work together. We were able to design the ALU module fairly easily, but it took
7. some time before we understood how the datapath and control modules would fit together. Once
we had that understanding though, we realized how the control module would set all the control
values and that the datapath would use these control values to actually perform most of the
desired operations.
Conclusion
In this lab, we learned how to design very complex Verilog code, and how one can
simulate and verify these results in the Xilinx software. We also learned how to design a simple
processor, and how to effectively code and implement such a program in computer architecture
projects. We also were able to ascertain information regarding various errors that could occur
during the coding process, and how to identify and correct them with the software and various
debugging methods.
Using this newly gained knowledge, we were able to successfully design, code, and
analyze the various modules that we needed to successfully implement a simple processor. We
were also able to run one overarching ModelSim waveform generation that allowed us to see the
entire performance and accuracy of our program. We were also able to understand the function
of the many functions and variables utilized in our modules, but more importantly, we were able
to identify the ways in which we needed to alter these components to fit the necessary tasks for
our overall project.
Overall, the simple processor is an important program to be able to understand and create
in Xilinx. Although considered one of the most difficult tasks we will be assigned as
undergraduates, the knowledge and experiences gained from successfully completing such a task
will prove to be invaluable. This lab is also important in that it helps us understand the higher-
8. level functions of our complex code as well as the various applications that may be able to utilize
it in order to further our knowledge in this field and help us solve future electrical and computer
engineering projects.
Appendix: Code
ALU Module:
`timescale 1ns / 1ps
module alu(y, MD, ALUc, z, c, c);
input [15:0] y; //input 1
input [15:0] MD; //input 2
input [2:0] ALUc; //opcode for ALU
9. output [15:0] z; //output
output c; //carry in/out
reg [15:0] z;
reg c;
always @ (y or MD or ALUc) begin
case (ALUc)
0: //NOT
z = ~y;
1: //ADC
{c, z} = y + MD;
//JPA doesn't use ALU
3: //INCA
z = y + 1;
4: //STA
z = 0'b000;
5: //LDA
z = MD[15:0];
endcase
end
endmodule
10. Datapath Module:
`timescale 1ns / 1ps
module Datapath(RD, clk, rstn, enableMD, enableAC, enablePC, enableIR, enableMA,
selectmuxMA, selectmuxPC, selectmuxA, ALUc, WD, A, RWn, PC, MA, y, IR, MD, c);
input clk, rstn;
input [15:0] RD;
input enableAC, enableIR, enableMA, enableMD, enablePC, selectmuxA, selectmuxMA;
input [2:0] ALUc;
input [1:0] selectmuxPC;
input RWn;
output [11:0] A;
output [15:0] y;
output [15:0] IR;
output [11:0] MA;
output [15:0] MD;
output [11:0] PC;
output [15:0] WD;
output c;
reg [11:0] A;
reg [15:0] IR;
reg [11:0] PC;
reg [15:0] y; //Accumulator
reg [11:0] MA;
reg [15:0] MD;
reg [15:0] WD;
reg c; //Corresponding to carry in state 15
wire enableAC, enableIR, enableMA, enableMD, enablePC, selectmuxA, selectmuxMA;
wire [1:0] selectmuxPC;
wire [2:0] ALUc;
wire [15:0] z; //ALU store output
initial begin
A = 0;
y = 0;
c = 0;
PC = 0;
end
alu ALU(y, MD, ALUc, z, c, c);
always @ (posedge clk or MD or ALUc) begin
11. if (enableAC == 1)
y = z; //Load y with ALU store output
end
always @ (posedge clk or negedge rstn) begin
case (RWn)
0 : begin
if (enableAC == 1)
WD = y;
end
1 : begin
if (enableMD == 1)
MD = RD;
else if (enableIR == 1)
IR = RD;
end
endcase
case (selectmuxMA)
0 : begin
if (enableMA == 1 && enableIR == 1)
MA <= IR[11:0];
end
1 : begin
if (enableMA == 1 && enableMD == 1)
MA <= MD[11:0];
end
endcase
case (selectmuxPC)
0 : begin
if (enablePC == 1)
PC <= PC + 1;
end
1 : begin
if (enablePC == 1)
PC <= IR[11:0];
end
2 : begin
if (enablePC == 1)
PC <= MD[11:0];
end
endcase
end
always @ (posedge clk or MA or MD or PC) begin
12. case (selectmuxA)
0 : begin
if (enablePC == 1)
A = PC;
end
1 : begin
if (enableMA == 1)
A = MA;
end
endcase
end
endmodule
