This document provides lecture notes on MOS design equations and parameters. It includes: - MOS transistor symbol definitions and varieties - Support equations for threshold voltage, subthreshold slope, gate overdrive voltage, velocity saturation, drain current factor, channel length modulation, and thermal voltage - Current equations for strong, weak, and moderate inversion regions - Sample MOSFET parameters for 0.35μm and 0.18μm processes - Problems involving calculating small signal parameters, voltage gain, and transistor sizing for different circuits like common source amplifiers, NAND gates, and current mirrors.

1. Lecture Notes in Microelectronics
Torsten Lehmann
October 14, 2008
1 MOS design equations
S
B
D
G
−
+
D
B
S
G +
vGS
−
+
−
vBS
vDS
+
−
+
−
vGS
iDS
vDS
+
iDS
−
vBS
(B)(A)
Figure 1: MOS transistor symbol, voltage and current definitions; (A) NMOS transistor
(B) PMOS transistor.
NMOS PMOS
full symbol
bulk implicit
switch
depletion
high-voltage
Figure 2: MOS transistor varieties.
1

2. 1.1 Support equations
threshold voltage Vth = Vth0 + γ |2φF − vBS| − |2φF| (1)
n/p sign function |x|p ≡
x for n-channel
−x for p-channel
; |x|p =
γ
|γ|
x (2)
sub-threshold slope n =
γ
2 |2φF − vBS|
+ |1|p (3)
gate-overdrive voltage vEff = vGS − Vth (4)
velocity saturation µ =
µ0
1 + vDS/(ECritL)
(5)
drain saturation voltage vDSsat = LECrit 1 + 2vEff/(LECrit) − 1 (6)
≃ vEff, |2vEff|p ≪ |LECrit|p (7)
drain current factor β =
W
L
K′
=
W
L
µCox; K′
= µCox (8)
channel-length modulation α = 1 + λvDS = 1 +
kλvDS
L
; λ =
kλ
L
(9)
thermal voltage VT = kT/q (10)
sub-threshold scale current I0 = 1
2
µCox(2nVT )2
(11)
weak-strong transition IWST = I0 ln2
(2)
W
L
(12)
1.2 Current equations
Strong inversion (|vEff|p >∼ |2nVT ln(10)|p, or |IDS,sat|p ≫ |IWST|p):
iDS = µCox
W
L
vEffvDS − 1
2
v2
DS α, |vDSsat|p > |vDS|p (triode) (13)
iDS = IDS,sat = µCox
W
L
vEffvDSsat − 1
2
v2
DSsat α, |vDSsat|p ≤ |vDS|p (saturation)(14)
≃ 1
2
µCox
W
L
v2
Effα, |2vEff|p ≪ |LECrit|p (not velocity saturated) (15)
≃ µ0CoxECritW vEff − 1
2
vDSsat α, |2vEff|p ≫ |LECrit|p (deep velocity sat.) (16)
Weak inversion (|vEff|p <∼ −|2nVT ln(10)|p, or |IDS,sat|p ≪ |IWST|p):
iDS = I0
W
L
evEff /(nVT )
1 − e−|vDS|p/VT
α (17)
iDS = IDS,sat = I0
W
L
evEff /(nVT )
α, |nVT |p ≪ |vDS|p (saturation) (18)
Moderate inversion saturation (|vDS|p ≫ |nVT |p, and |vDS|p > |vEff|p):
iDS = IDS,sat = 1
2
µCox
W
L
(2nVT )2
ln2
1 + evEff /(2nVT )
α (19)
2

3. 0.001
0.01
0.1
1
10
100
1000
-4 -2 0 2 4
iDS/Iwst
veff/nVT
current expression
(log(1+exp(x/2))/log(2))**2
x**2/(log(2)*2)**2
exp(x)/log(2)**2
Figure 3: Normalised saturation current
1.3 Sample MOST parameters
Typical parameters for some CMOS processes (preliminary):
Process 0.35 µm 0.18 µm
Parameter n-channel p-channel n-channel p-channel
VDD,max 2.5 V 2.5 V 1.8 V 1.8 V
Vth0 0.6 V −0.6 V 0.5 V −0.5 V
γ 0.5
√
V −0.5
√
V 0.6
√
V −0.4
√
V
2φF 0.7 V −0.7 V 0.8 V −0.8 V
n (zero bias) 1.3 −1.3 1.4 −1.3
Lmin 0.35 µm 0.35 µm 0.18 µm 0.18 µm
kλ 0.1 µm/V −0.1 µm/V 0.12 µm/V −0.08 µm/V
µ0Cox 120 µA/V2
−40 µA/V2
260 µA/V2
−65 µA/V2
Cox 4 fF/µm2
4 fF/µm2
8 fF/µm2
8 fF/µm2
Cj0 0.8 fF/µm2
1.2 fF/µm2
2 fF/µm2
2 fF/µm2
Cj0sw 0.3 fF/µm 0.4 fF/µm 0.6 fF/µm 0.6 fF/µm
Cov 0.2 fF/µm 0.2 fF/µm 0.1 fF/µm 0.1 fF/µm
xj 0.1 µm 0.1 µm 0.05 µm 0.05 µm
ℓsd 1 µm 1 µm 0.5 µm 0.5 µm
λ (DRC) 0.2 µm 0.2 µm 0.1 µm 0.1 µm
ECrit ∞ −∞ 2.2 V/µm −5 V/µm
3

4. 2 Noise
Calculating total input referred noise is often impossible, as the integral typically diverges
for both high frequencies (white noise) and low frequencies (1/f noise). The total output
referred noise is easier, as any circuit has an upper band-width — typically, this doesn’t
solve the 1/f divergence problem, however. My suggestion is to equate the lower frequency
bound to 1/Tobs, where Tobs is the observation time of the system (e.g., the time it is turned
on — say a day or so):
V 2
no,tot =
∞
1/Tobs i
V 2
ni(f)|Hi(f)|2
df
3 Matching
To a first order approximation, the relative variance of drain current in MOS transistor
biased in strong inversion saturation can be expressed as:
σ2
D
I2
D
=
BW
LW2
+
BL
WL2
+
BK
WL(µCox)2
+ 4
BV
WL(VGS − Vth)2
(20)
where ID is the average (nominal) drain current, and the Bs are constants. For relatively
large transistors and a given gate bias voltage, this simplifies to:
σ2
D
I2
D
≃
BI
WL
(21)
4

5. 4 Problems
4.1 Problem 1
vOUT
vIN
IB
VDD
VSS
Figure 4: Common source amplifier
The common source amplifier in figure 4 is biased with a DC drain current of IB = 1 µA.
It is to be implemented in the 0.35 µm process, where the smallest transistor dimensions
allowed (for this amplifier) is 0.7 µm.
• Find W and L such that the transistor is biased in weak inversion. Find for this
transistor all the small-signal parameters (gm, rds, Cgs, Cgd, Csb, and Cdb) and the
low-frequency voltage gain, Av. Find also fT for the transistor.
• Now find W and L such that the transistor is biased in strong inversion, and again
find gm, rds, Av and fT. For this amplifier, what must the DC bias value, VIN, of in
the input voltage be? What must VIN be if the source voltage is 1 V rather than 0 V
as on the figure?
• Finally, find W and L such that the transistor is biased in strong inversion, but has
the same gate area as the weak-inversion amplifier, and find gm, rds, Av and fT.
4.2 Problem 2
For the circuit in figure 5, prove that
i1 − i2 = µCox
W
L
v1v2 ,
when all transistors are identical and operate in the triode region (the bulk affect can be
ignored).
4.3 Problem 3
For the CMOS nand-gate in figure 6, find all transistors widths, W and lengths, L such
that the gate can drive a load capacitance of CL = 1 pF in less than 5 ns.
5

6. 0V by feedbackv2
v1
i1
i2
Figure 5: Cross-coupled transistor pairs
z
a
b
CL
N
N
PP
DDV
(a)
param N P unit
µCox 92 −30 µA/V2
Vth 0.8 −0.9 V
Lmin 0.8 µm
VDD 2 V
(b)
Figure 6: Static CMOS nand-gate (a) and circuit and transistor parameters (b)
4.4 Problem 4
a
b
z
CL
VB
SN
SN
N
P
DDV
Figure 7: CSL nand-gate
For the Current Steering Logic (CSL) nand-gate in figure 7, find all transistors widths,
W and lengths, L, and the bias voltage, VB such that the gate can drive a load capacitance
of CL = 1 pF in less than 5 ns; use the same circuit and transistor parameters as in problem
3.
6

7. 4.5 Problem 5
word line
bit line
MS
MC
VB
(a)
param val unit
Cox 5 fF/µm2
Lmin 0.35 µm
Cj(sb, sd) 1.5 fF · W
VDD 3 V
(b)
Figure 8: DRAM cell (a) and transistor parameters
The dynamic RAM cell in figure 8 is arranged in a square, 1 cm2
matrix. Estimate the
largest number of bits in the matrix when the sense amplifier can detect a 50 mV voltage
difference and relevant transistor parameters are given in the figure. Transistor ms is a
switch transistor while transistor MC act as a storage capacitor. The bias voltage, VB is
chosen > VDD + Vth, and the word-line is like-wise clock-boosted to a voltage > VDD + Vth
when high. Find also the widths, W and lengths, L for the transistors.
4.6 Problem 6
iin iout
Figure 9: Current mirror
For a given vGS, the relative drain current variation (in saturation) is given by
σ2
I2
D
=
BI
WL
, BI = 5 · 10−4
µm2
,
where ID is the average drain current and σ2
is the variance of the drain current. The
drain current is assumed to be normally distributed. For the current mirror in figure 9
with W/L = 5µm/2µm for both transistors, what is the probability that |iout − iin| < 1 %?
4.7 Problem 7
A wafer has a defect density of D = 0.01 cm−2
. Chips on the wafer are 2 cm2
in size,
each having 1000 sub-components that perform outside specifications with a probability of
0.002 % each. Find the fraction of chips which function within specifications after manu-
facturing.
7