The document discusses field effect transistors (FETs), specifically metal-oxide-semiconductor FETs (MOSFETs). It describes the basic structure and operation of n-channel and p-channel enhancement-mode MOSFETs. The key characteristics of MOSFETs include: they have three terminals - gate, source, and drain; the channel current flowing from source to drain is controlled by the electric field generated by the gate; and their input impedance is extremely high. The document provides equations to describe the linear and saturation regions of the drain current-drain voltage characteristics of n-channel and p-channel MOSFETs. It also discusses concepts such as channel length modulation and output resistance.

1. FIELD EFFECT TRANSISTORS
(FET)
Celso José Faria de Araújo, Dr.

2. 1
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Gate
Drain
Source
Base
Collector
Emitter
FET
 3 terminal device
 Channel e- current
from source to drain
controlled by the
electric field
generated by the gate
 Extremely high input
impedance for base
BJT
 3 terminal device emitter
to collector e- current
controlled by the current
injected into the base
FET X BJT (NPN)

3. 2
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
• In addition to carrier type (N or P channel), there are differences in
how the control element is constructed (Junction x Insulated) and
those devices must be used differently
Depletion mode junction FETs (JFET)
npn
pnp
npn
pnp
Metal oxide semi-conductor FET (MOSFET)
– depletion/enhancement mode
– enhancement mode
(insulated gate FETs, IGFETs, are the same as MOSFETs)
Types of FETs

4. 3
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W = 2
to 500 m, and the thickness of the oxide layer is in the range of 0.02 to 0.1 m.

5. 4
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
n
+
v Small
DS
D
n
+
S
B
v > V
GS TN
G
Depletion
Region
p
n
+
D
n
+
S v = v - V
DS GS TN
v > V
GS TN
G
B
Depletion
Region
p
n
+
D
n
+
S v > v - V
DS GS TN
v > V
GS TN
G
B
Depletion
Region Pinch-off Point
p Acceptor Ion
( a ) MOSFET in the linear region
( b ) MOSFET with channel just pinched
off at the drain.
( c ) Channel pinch off for vDS > vGS - VTN
Water
Waterfalls analogy

6. 5
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate
beneath the gate.

7. 6
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is determined by vGS.
Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the depletion
region is not shown (for simplicity).

8. 7
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
0.8
0.6
0.4
0.2
0.0
0.00e+0
2.00e-4
4.00e-4
6.00e-4
8.00e-4
Drain-Source Voltage (V)
Drain-Source
Current
(A)
V = 2 V
V = 3 V
V = 4 V
V = 5 V
GS
GS
GS
GS
NMOS i-v characteristics in the linear region (VSB = 0)
  








2
2
DS
DS
tn
GS
OX
n
D
v
v
V
v
L
W
C
μ
i vGS  Vtn
0  vDS  vDSSAT
= vGS-Vtn
Linear Region (small vDS)
 
 
tn
GS
n
DS
D
DS
tn
GS
n
D
DS
V
v
L
W
k
dv
di
v
V
v
L
W
k
i
v
small




'
'
VTN =1V
OX
n
n C
μ
k 
'

9. 8
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape and its resistance
increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

10. 9
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

11. 10
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Output characteristics
for an NMOS transistor with
Vtn = 1 V and k’n (W/L)= 25 x 10-6 A/V2
12
10
8
6
4
2
0
0.00e+0
2.00e-5
4.00e-5
6.00e-5
8.00e-5
1.00e-4
1.20e-4
1.40e-4
1.60e-4
1.80e-4
2.00e-4
2.20e-4
Drain-Source Voltage (V)
Drain-Source
Current
(A)
V = 2 V
V = 3 V
V = 4 V
V = 5 V
Pinchoff Locus
V Š 1 V
Saturation Region
Linear
Region
GS
GS
GS
GS
GS
 
















tn
GS
DS
DS
tn
GS
DS
DS
tn
GS
n
D
V
v
v
v
V
v
for
v
v
V
v
L
W
k
i
SAT
2
2
'
ID
G
D
S  B
vD  vS
tn
GS
D V
v
for
i 
 0
 









tn
GS
DS
DS
tn
GS
tn
GS
n
D
V
v
v
v
V
v
for
V
v
L
W
k
i
SAT
2
'
2

12. 11
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Derivation of the iD - vDS characteristic of the NMOS transistor.

13. 12
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
p+
L
Source
Gate
Drain
Channel Region
Body
N-Type Substrate
v > 0
B
i
B
iS
v
S
v < 0
G
i
G
v < 0
D
iD
p+
Cross section of an enhancement-mode PMOS transistor
ID
G
D
S
ID
G
D
S
B
The PMOS Transistor

14. 13
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Output characteristics for a
PMOS transistor with
Vtp = -1V and k’P (W/L)= 25 x 10-6 A/V2
12
10
8
6
4
2
0
-2
-5.00e-5
0.00e+0
5.00e-5
1.00e-4
1.50e-4
2.00e-4
2.50e-4
Source-Drain Voltage (V)
Source-Drain
Current
(A)
V Š 1 V (V •
-1 V)
SG GS
V = 3 V (V = -3 V)
SG GS
V = 2 V (V = -2 V)
SG GS
V = 4 V (V = -4 V)
SG GS
V = 5 V (V = -5 V)
SG GS
ID
G
D
S  B
tp
GS
D V
v
for
i 
 0
 
















tp
GS
DS
DS
tp
GS
DS
DS
tp
GS
p
D
V
v
v
v
V
v
for
v
v
V
v
L
W
k
i
SAT
2
2
'
 









tp
GS
DS
DS
tp
GS
tp
GS
p
D
V
v
v
v
V
v
for
V
v
L
W
k
i
SAT
2
'
2
vS  vD

15. 14
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well.
Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.

16. 15
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated.
(b)The iD - vDS characteristics for a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2 (d) The iD - vGS characteristic for an enhancement-
type NMOS transistor in saturation.
(d)

17. 16
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Channel Length Modulation
 





 










M
D
M
D
D
M
D
t
GS
ox
D
L
L
I
L
L
I
i
L
L
I
V
v
L
W
C
i
SAT
SAT
SAT
1
1
2
2

LM
   
DS
t
GS
ox
D
A
DS
M
v
V
v
L
W
C
i
L
V
v
L
L












1
2
1
2
Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective
channel length (by L).

18. 17
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Effect of vDS on iD in the saturation region. The MOSFET parameter VA is typically in the range of 30 to 200 V.
    Saturation
1
2
2



 DS
t
GS
ox
D v
V
v
L
W
C
i 

D
DS
-
v
DS
D
o
I
v
v
i
r
GS

1
1
constant














  A
DS
D
A
D
o V
V
I
V
I
r 



1

Output Resistance:
VA is directly proportional to L; thus two devices with the same process, and having channel lengths L1 e L2,
will have Early voltage VA1 and VA2,.
2
1
2
1
L
L
V
V
A
A


19. 18
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output
resistance models the linear dependence of iD on vDS and is given by ro  VA/ID.

20. 19
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
ID
G
D
S
ID
G
D
S
G
D
S
B G
D
S
B
P-channel
N-channel
Vtn > 0
vDS  0
Vtp < 0
vDS  0
or or
ox
p
p C
μ
k 
'
Summary of equations for the enhancement-mode MOSFET
   
    























































A
SD
tp
SG
p
D
tp
SG
SD
tp
SG
A
DS
tn
GS
n
D
tn
GS
DS
tn
GS
SD
SD
tp
SG
p
D
tp
SG
SD
tp
SG
DS
DS
tn
GS
n
D
tn
GS
DS
tn
GS
D
tp
SG
D
tn
GS
V
V
V
v
L
W
k
i
V
v
v
and
V
v
V
V
V
v
L
W
k
i
V
v
v
and
V
v
v
v
V
v
L
W
k
i
V
v
v
and
V
v
v
v
V
v
L
W
k
i
V
v
v
and
V
v
i
V
v
i
V
v
1
2
1
2
Saturation
2
2
(Linear)
Triodo
0
0
Cutoff
Type
-
P
Type
-
N
Region
2
'
2
'
2
'
2
'
ox
n
n C
μ
k 
'

21. 20
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2 mA/V2:
(a) transistor with current and voltage polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic in saturation.

22. 21
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
-  usually neglected ( 1/  =VA)
- Q-point most often located in saturation for analog circuits
DD
G V
R
R
R
V
2
1
2


D
S
S I
R
V 
  D
S
D
DD
DS I
R
R
V
V 


 2
'
2
t
GS
n
D V
V
L
W
k
I 

2
2
1
2
'
2









 D
S
t
DD
n
D I
R
V
V
R
R
R
L
W
k
I
D
S
DD
GS I
R
V
R
R
R
V 


2
1
2
VDD
VG
RD
RS
RG
R1
R2
ID
( assuming the MOSFET to be
in the saturation region )
( two solutions  only one
is possible )
Ex: VDD = 10 V R1 = 150 k R2 = 100 k RS = 10 k
RD = 50 k k’n(W/L) = 50 A/V2 Vt = 1 V
Solution: ID = 100 A VDS = 4 V
Bias Circuits 1

23. 22
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
VDD
-VSS
RD
RS
RG
VDD
-VSS
RD
I
RG
Two power supplies are
available
A simple circuit utilizing
a current source
Bias Circuits 2
VDD
VDS = VGS2
load line
curve VDS = VGS
VGS1
VGS2
VGS3
Q
VDD/ RD
VDD
RD
RG
ID
 2
'
2
t
GS
n
D V
V
L
W
k
I 

 2
'
2
D
D
t
DD
n
D I
R
V
V
k
I 


 
0


 G
DS
GS I
V
V
Analysis
D
D
DD
GS I
R
V
V 


24. 23
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Basic MOSFET current mirror.
Q1: I  V converter
Q2: V  I converter
If Q2 in saturation
then
 
 1
2
L
W
L
W
I
I
REF
o 
 
t
GS
o V
V
v 

min
Example: VDD = 5V ;IREF=10A; Q1 and Q2 are
matched ; L=10 m and W=100 m; Vt = 1V ;
k’
n=20  A/V2 VA = 10L; Vo=+3V
 
3%
μA
3
M
1
V
3
M
1
100
V
100
V
100
10
x
10
1V
1
2
30
100
2
5
2V
1
10
100
20
2
1
100
min
2
1



























o
o
o
o
A
o
GS
GS
REF
D
r
V
I
μA
r
V
v
K
R
V
V
I
I


25. 24
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
 
 
   
 
 
 
D
m
gs
d
v
gs
D
m
D
d
d
d
D
D
d
D
D
DD
D
D
DD
D
D
n
t
GS
n
gs
d
V
v
GS
D
m
gs
t
GS
n
d
d
D
D
t
GS
gs
gs
t
GS
n
gs
n
gs
n
gs
t
GS
n
t
GS
n
D
t
gs
GS
n
D
gs
GS
GS
t
GS
D
D
D
DD
D
t
GS
n
D
R
g
v
v
A
v
R
g
R
i
v
i
R
V
i
I
R
V
i
R
V
v
I
L
W
k
V
V
L
W
k
v
i
v
i
g
v
V
V
L
W
k
i
i
I
i
V
V
v
v
V
V
L
W
k
v
L
W
k
v
L
W
k
v
V
V
L
W
k
V
V
L
W
k
i
V
v
V
L
W
k
i
v
V
v
V
V
V
I
R
V
V
V
V
L
W
k
I
GS
GS





















































)
(
Gain
Voltage
2
)
(
2
2
1
2
1
2
1
2
1
Terminal
Drain
in the
Current
signal
The
0
2
1
Point
Bias
DC
ctance
transcondu
'
'
'
signal
small
'
2
'
2
'
'
2
'
2
'
2
'










 










 










 









 


The operation of the MOSFET as an amplifier.

26. 25
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation effect); and
(b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
(a.1) -Model
(a.2) T-Model
(b.1) -Model
(b.2) T-Model

27. 26
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
 
 
 
2.33MΩ
3
.
4
3
.
4
1
Resistance
Input
V
V
37
.
3
//
//
//
1
Gain
Voltage
0
//
//
Analysis
AC
47KΩ
1.06m
50
mA/V
725
.
0
)
5
.
1
4
.
4
(
25
.
0
Meaningful
Physically
4.4V
and
1.06mA
K
10
15
15
5
.
1
25
.
0
2
1
Analysis
DC
2























 























G
i
i
in
G
i
i
o
G
i
G
o
i
i
G
L
D
o
G
m
i
o
v
G
i
o
i
m
L
D
o
o
o
m
D
D
D
D
D
D
D
D
D
GS
R
i
v
R
R
v
v
v
R
v
R
v
v
i
R
R
R
r
R
g
v
v
A
R
v
v
v
g
R
R
r
v
r
m
g
V
I
I
I
R
V
V
m
I
V
V
Example: Vt = 1.5V ; k’
n(W/L)=0.25 mA/V2 VA = 50V

28. 27
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Small-signal equivalent-circuit model of a MOSFET in which the body is not connected to the source.
0.3
χ
0.1
g
v
i
g m
v
v
BS
D
mb
DS
GS









constante
constante
ctance
Transcondu
Body

29. 28
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
VDD
I
vo
-VSS
vI
VDD
I
vo
vI
VDD
I
vI
vo
Source follower
or common-drain
amplifier
Common-source
amplifier
Common-gate
amplifier
Basic amplifier configurations with current sources

30. 29
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
 
2
1
1
2
1
//
//
o
o
m
v
o
o
o
i
r
r
g
A
r
r
R
R





ID2
ID2
The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to determine
the transfer characteristic; and transfer characteristic.

31. 30
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Example: VDD=10V;Vtn = | Vtp| = 1V ; k’
n= 2 k’
p= 20 A/V2
(W=100 m; L =10 m |VA|= 100V for both the n and p device)
IREF=100 A.
 
 
 
 
  MΩ
5
.
0
//
V
V
100
//
1MΩ
V
A
2
.
0
2
2V
2
1
μA
100
V
795
.
4
V
1
8.59V
)
(
10
2.41V
2
1
μA
100
μA
100
2
1
2
1
1
2
1
1
'
1
2
1
'
1
2
1
1
2
3
'
3
1
2
min
min
max
min
max




























































o
o
o
in
o
o
m
i
o
v
REF
A
o
o
REF
n
m
I
tn
I
n
REF
D
O
o
o
o
O
O
O
tn
I
O
tp
SG
O
SG
tp
SG
p
REF
D
D
D
REF
r
r
R
R
r
r
g
v
v
A
I
V
r
r
m
I
L
W
k
g
V
V
V
L
W
k
I
I
v
r
r
r
v
v
V
V
V
v
V
V
v
V
V
V
L
W
k
I
I
I
I
I
vO
vI
2 2.04
1.96
8.59
10
4.795
1
Bias Point
Slope = -100V/V
p
^
p
^
mV
40
V
795
.
3 



 i
o v
v

32. 31
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).
 
  






































1
2
1
1
1
2
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
//
//
1
o
o
mb
m
i
o
o
o
mb
m
i
i
i
o
o
mb
m
v
o
o
o
mb
m
i
o
v
r
r
g
g
R
r
r
r
g
g
i
v
R
r
r
g
g
A
r
r
r
g
g
v
v
A

33. 32
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.
 
χ
g
g
g
R
r
r
g
g
R
χ
g
g
g
A
r
r
g
g
g
R
g
R
g
v
v
A
m
mb
m
o
o
o
mb
m
o
mb
m
m
v
o
o
mb
m
m
S
m
S
m
i
o
v







































1
1
1
//
1
//
//
1
//
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
2
1
1
1
1
1
1

34. 33
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
(a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer characteristic.
 
 
 
 
 
 
 
 2
1
2
2
1
2
1
2
1
1
1
L
W
L
W
L
W
L
W
A
v
L
W
L
W
V
L
W
L
W
V
V
v
v
I
t
t
DD
O



















35. 34
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and
(c) transfer characteristic.
 
  χ
L
W
L
W
g
g
A
r
r
g
g
v
v
A
mb
m
v
o
o
mb
m
i
o
v
1
//
//
1
2
1
2
1
2
1
1
1





















36. 35
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
 













tn
DD
n
n
DSN
V
V
L
W
k
r
'
1

37. 36
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
 
















tp
DD
p
p
DSP
V
V
L
W
k
r
'
1

38. 37
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
 
 
t
DD
IL
t
DD
IH
V
V
V
V
V
V
2
3
8
1
2
5
8
1




The voltage transfer characteristic of the CMOS inverter.
 
 
t
DD
L
t
DD
H
V
V
NM
V
V
NM
2
3
8
1
2
3
8
1
Margins
Noise





39. 38
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating
point as the input goes high and C discharges through the QN; (d) equivalent circuit during the capacitor discharge.

40. 39
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
(a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected to the
substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).
  D
m I
L
W
k
g 2

D
DS
A
o
I
V
V
r


Strong inversion and saturation:
VGS – Vt > 200 mV
W L
C
C ox
gs
3
2


41. 40
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Determining the short-circuit current gain Io/Ii.
 
gd
gs
m
i
o
C
C
s
g
I
I


For physical frequencies s = j, it cam be seen that the magnitude of the current gain
becomes unity at the frequency:
 
gd
gs
m
T
C
C
g
f


π
2

42. 41
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The Junction Field-Effect Transistor
p
p
Depletion
region
Depletion
region
G
S D
G
n
p
p
v = 0
GS
W
p
p
Depletion
region
Depletion
region
G
S D
G
n
p
p
+ -
V < v < 0
GS
P
W'
i
G
p
p
Depletion
region
Depletion
region
G
S D
G
n
p
p
+ -
v = V
GS P
Pinched-Off Channel
< 0
( a ) JFET with zero gate-source bias
( b ) JFET with negative gate-source voltage
that is less negative than the pinch-off
voltage VP. Note W’ < W
( c ) JFET at pinch-off with VGS = VP

43. 42
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
The Junction Field-Effect Transistor ( a ) JFET with small drain-source ( b ) JFET with channel just at
pinch-off with vDS = vDSP
D
S
G
G
+ -
vGS
Depletion
region
Depletion
region
v
DS
p
p
p
n iDS
< 0
D
S
G
G
+ -
vGS
Depletion
region
Depletion
region
p
p
p
n iDS
v = v
DS DSP
( a ) JFET with small drain-source
( b ) JFET with channel just at
pinch-off with vDS = vDSP

44. 43
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
iD
G
D
S
G
D
S
iD
P-channel
N-channel
Summary of equations for the JFET


















































































































A
DS
P
GS
DSS
D
P
GS
DS
P
GS
A
DS
P
GS
DSS
D
P
GS
DS
GS
P
P
DS
P
DS
P
GS
DSS
D
P
GS
DS
P
GS
P
DS
P
DS
P
GS
DSS
D
P
GS
DS
GS
P
D
P
GS
D
P
GS
V
V
V
v
I
i
V
v
v
and
V
v
V
V
V
v
I
i
V
v
v
and
v
V
V
v
V
v
V
v
I
i
V
v
v
and
V
v
V
v
V
v
V
v
I
i
V
v
v
and
v
V
i
V
v
i
V
v
1
1
0
1
1
0
Saturation
1
2
0
1
2
0
(Linear)
Triodo
0
0
Cutoff
Type
-
P
Type
-
N
Region
2
2
2
2
0
0
max


GS
P
v
V
0
0
min


GS
P
v
V
D
A
o
DSS
D
P
DSS
P
GS
P
DSS
m
I
V
r
I
I
V
I
V
V
V
I
g 




























2
1
2

45. 44
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Output characteristics for a JFET with IDSS = 200 A and VP = -4V
12
10
8
6
4
2
0
0.00e+0
2.00e-5
4.00e-5
6.00e-5
8.00e-5
1.00e-4
1.20e-4
1.40e-4
1.60e-4
1.80e-4
2.00e-4
2.20e-4
Drain-Source Voltage (V)
Drain-Source
Current
(A)
V = -3 V
V = -2 V
V = -1 V
V = 0 V
Pinch-off Locus
V Š V
Pinch-off Region
(Saturation)
Linear
Region I
GS
P
DSS
GS
GS
GS
GS
D
S
G
iDS
vGS
v
DS
D
S
G
iSD
vSG
v
SD
n-channel JFET p-channel JFET
+
-
+
-
+
-
+
-

46. 45
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Transfer characteristic for a saturated JFET with IDSS = 1 mA and VP = -3.5V
3
2
1
0
-1
-2
-3
-4
-5
-6
-5.00e-4
0.00e+0
5.00e-4
1.00e-3
1.50e-3
Gate-Source Voltage (V)
Drain-Source
Current
(A) I DSS
V
P

47. 46
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
When to use JFETs
 JFET have much higher input impedances
and much lower input currents than BJTs.
 BJTs are more linear than JFETs.
 The gain of a BJT is much higher than that
of a JFET.

48. 47
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
JFET (Example)
The JFET in the circuit below has VP=-3V, IDSS=9mA,
and =0. Find the values of all resistors so that VG=5V,
ID=4mA, and VD=11V. Design for 0.05mA in the
voltage divider.
1KΩ
4m
11
15
R
100KΩ
R
200KΩ
R
0.05m
R
R
15
15
R
R
R
5
D
G2
G1
G1
G2
G1
G2
G2









1.5KΩ
R
10V
V
6V
V
3
V
5
1
9m
4m
S
'
'
S
Ok
'
S
2
S





















 


 

Saturation
For the JFET circuit designed in the former exercise,
let an input signal vi be capacitively coupled to the
gate, a large bypass capacitor be connected between
the source and ground, and the output signal vo be
taken from the drain through a large coupling
capacitor. The resulting common-source amplifier is
shown below. Calculate gm and ro (assuming
VA=100V). Also find Ri and Ro.
25KΩ
4m
100
V
A
4m
9m
4m
3
9m
2x













 o
m r
g
  V
V
3.85
R
// D 



 o
m
i
o
v r
g
v
v
A
66.7KΩ
//R
R
962
R
// G2
G1
D 




 i
o
o R
r
R

49. 48
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
 SEDRA. Adel S. e SMITH, Kenneth C. Microelectronic
Circuits. Oxford University Press.
 BOYLESTAD, Robert e NASHELSKY, Louis.
Dispositivos Eletrônicos e Teoria de Circuitos. Prentice
Hall do Brasil.
 SZE, S. M. Physics of Semiconductor Devices. John Wiley
& Sons.
 SCHILLING, Donald L. e BELOVE, Charles. Circuitos
Eletrônicos Discretos e Integrados. Guanabara Dois.
 COMER, David J. Introduction to Semiconductor
Circuits Design. Addison Wesley Publishing Company.
 MALVINO, Albert P. Eletrônica. Volume I. McGraw-Hill.
References