This document provides information on a digital audio MOSFET in a TO-220 Full-Pak 5 pin package designed for class D audio amplifier applications. The MOSFET integrates two power switches in a half-bridge configuration to reduce part count. Key parameters like low RDS(on), Qg, Qsw, and Qrr are optimized to improve efficiency, THD, and reduce EMI. Figures and tables of electrical characteristics like breakdown voltage, on-resistance, gate charge, and switching performance are provided. The document also includes test circuits and considerations for evaluating the MOSFET.

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8/22/06
IRFI4019H-117P
Notes  through † are on page 2
DIGITAL AUDIO MOSFET
TO-220 Full-Pak 5 PIN
Features
Ÿ Integrated Half-Bridge Package
Ÿ Reduces the Part Count by Half
Ÿ Facilitates Better PCB Layout
Ÿ Key Parameters Optimized for Class-D
Audio Amplifier Applications
Ÿ Low RDS(ON) for Improved Efficiency
Ÿ Low Qg and Qsw for Better THD and
Improved Efficiency
Ÿ Low Qrr for Better THD and Lower EMI
Ÿ Can Delivery up to 200W per Channel into
8Ω Load in Half-Bridge Configuration
Amplifier
Ÿ Lead-Free Package
Description
This Digital Audio MosFET Half-Bridge is specifically designed for Class D audio amplifier applications. It
consists of two power MosFET switches connected in half-bridge configuration. The latest process is used
toachievelowon-resistancepersiliconarea.Furthermore,Gatecharge,body-diodereverserecovery,and
internal Gate resistance are optimized to improve key Class D audio amplifier performance factors such
as efficiency, THD and EMI. These combine to make this Half-Bridge a highly efficient, robust and reliable
device for Class D audio amplifier applications.
G1, G2 D1, D2 S1, S2
Gate Drain Source
Absolute Maximum Ratings h
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM Pulsed Drain Current c
EAS Single Pulse Avalanche Energyd mJ
PD @TC = 25°C Power Dissipation f W
PD @TC = 100°C Power Dissipation f
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Thermal Resistance h
Parameter Typ. Max. Units
RθJC
Junction-to-Case f ––– 6.9
RθJA
Junction-to-Ambient f ––– 65
77
18
7.2
0.15
10lbxin (1.1Nxm)
-55 to + 150
300
Max.
6.2
34
±20
150
8.7
S2
G2
S1/D2
G1
D1
VDS 150 V
RDS(ON) typ. @ 10V 80 m:
Qg typ. 13 nC
Qsw typ. 4.1 nC
RG(int) typ. 2.5 Ω
TJ max 150 °C
Key Parameters h
PD - 97074A

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S
D
G
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Starting TJ = 25°C, L = 5.8mH, RG = 25Ω, IAS = 5.2A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Notes: „ Rθ is measured at TJ of approximately 90°C.
… Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
avalanche information
† Specifications refer to single MosFET.
Electrical Characteristics @ TJ = 25°C (unless otherwise specified) h
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 150 ––– ––– V
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.19 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 80 95 mΩ
VGS(th) Gate Threshold Voltage 3.0 ––– 4.9 V
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -11 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 11 ––– ––– S
Qg Total Gate Charge ––– 13 20
Qgs1 Pre-Vth Gate-to-Source Charge ––– 3.3 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.8 ––– nC
Qgd Gate-to-Drain Charge ––– 3.9 –––
Qgodr Gate Charge Overdrive ––– 5.0 ––– See Fig. 6 and 19
Qsw Switch Charge (Qgs2 + Qgd) ––– 4.1 –––
RG(int) Internal Gate Resistance ––– 2.5 ––– Ω
td(on) Turn-On Delay Time ––– 7.0 –––
tr Rise Time ––– 6.6 –––
td(off) Turn-Off Delay Time ––– 13 ––– ns
tf Fall Time ––– 3.1 –––
Ciss Input Capacitance ––– 810 –––
Coss Output Capacitance ––– 100 ––– pF
Crss Reverse Transfer Capacitance ––– 15 –––
Coss Effective Output Capacitance ––– 97 –––
LD Internal Drain Inductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package
Diode Characteristics h
Parameter Min. Typ. Max. Units
IS @ TC = 25°C Continuous Source Current ––– ––– 8.7
(Body Diode) A
ISM Pulsed Source Current ––– ––– 34
(Body Diode) c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 57 86 ns
Qrr Reverse Recovery Charge ––– 140 210 nC
ID = 5.2A
ƒ = 1.0MHz, See Fig.5
TJ = 25°C, IF = 5.2A
di/dt = 100A/µs e
TJ = 25°C, IS = 5.2A, VGS = 0V e
showing the
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 5.2A e
VDS = VGS, ID = 50µA
VDS = 150V, VGS = 0V
VGS = 0V, VDS = 0V to 120V
VDS = 150V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VGS = 10V
ID = 5.2A
VGS = 0V
MOSFET symbol
RG = 2.4Ω
VDS = 50V, ID = 5.2A
Conditions
and center of die contact
VDD = 75V, VGS = 10V e
VDS = 75V
VDS = 25V

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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 6. Typical Gate Charge vs.Gate-to-Source VoltageFig 5. Typical Capacitance vs.Drain-to-Source Voltage
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
ID,Drain-to-SourceCurrent(A)
≤ 60µs PULSE WIDTH
Tj = 25°C
5.5V
VGS
TOP 15V
12V
10V
9.0V
8.0V
7.0V
6.0V
BOTTOM 5.5V
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
100000
C,Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 5 10 15 20
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS,Gate-to-SourceVoltage(V)
VDS= 120V
VDS= 75V
VDS= 30V
ID= 5.2A
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
ID,Drain-to-SourceCurrent(A)
≤ 60µs PULSE WIDTH
Tj = 150°C
5.5V
VGS
TOP 15V
12V
10V
9.0V
8.0V
7.0V
6.0V
BOTTOM 5.5V
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
0.0
0.5
1.0
1.5
2.0
2.5
RDS(on),Drain-to-SourceOnResistance
(Normalized)
ID = 5.2A
VGS = 10V
4 5 6 7 8
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
ID,Drain-to-SourceCurrent(Α)
VDS = 50V
≤ 60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C

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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area
Fig 10. Threshold Voltage vs. Temperature
25 50 75 100 125 150
TJ , Junction Temperature (°C)
0
2
4
6
8
10
ID,DrainCurrent(A)
0.0 0.5 1.0 1.5
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
ISD,ReverseDrainCurrent(A)
TJ = 25°C
TJ = 150°C
VGS = 0V
-75 -50 -25 0 25 50 75 100 125 150
TJ , Temperature ( °C )
2.0
3.0
4.0
5.0
VGS(th)GatethresholdVoltage(V) ID = 50µA
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
ThermalResponse(ZthJC)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τι (sec)
1.508254 0.000814
2.154008 0.111589
3.237738 2.2891
τJ
τJ
τ1
τ1
τ2
τ2
τ3
τ3
R1
R1
R2
R2
R3
R3
τ
τC
Ci= τi/Ri
Ci= τi/Ri
1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
ID,Drain-to-SourceCurrent(A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC

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Fig 13. Maximum Avalanche Energy Vs. Drain CurrentFig 12. On-Resistance Vs. Gate Voltage
4 5 6 7 8 9 10
VGS, Gate-to-Source Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
RDS(on),Drain-to-SourceOnResistance(Ω)
TJ = 25°C
TJ = 125°C
ID = 5.2A
25 50 75 100 125 150
Starting TJ, Junction Temperature (°C)
0
50
100
150
200
250
300
350
EAS,SinglePulseAvalancheEnergy(mJ)
I D
TOP 0.91A
1.1A
BOTTOM 5.2A
Fig 14. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D =
P.W.
Period
*** VGS = 5V for Logic Level Devices
***
+
-
+
+
+-
-
-
ƒ
„
‚
RG
VDD• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T

**
*
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel

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Fig 16a. Switching Time Test Circuit Fig 16b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)tr tf
Fig 15b. Unclamped Inductive WaveformsFig 15a. Unclamped Inductive Test Circuit
tp
V(BR)DSS
IAS
RG
IAS
0.01Ωtp
D.U.T
LVDS
+
-
VDD
DRIVER
A
15V
20VVGS
Fig 17a. Gate Charge Test Circuit Fig 17b Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
1K
VCC
DUT
0
L
S
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-VDD
20K

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Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/06
TO-220 Full-Pak 5-Pin Part Marking Information
TO-220AB Full-Pak 5-Pin package is not recommended for Surface Mount Application.
TO-220 Full-Pak 5-Pin Package Outline, Lead-Form Option 117
(Dimensions are shown in millimeters (inches))
ÃPS

8. Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/