This document discusses synchronous and asynchronous data transmission methods. Synchronous transmission uses timing signals to ensure the receiver and transmitter stay synchronized during continuous data transfer, allowing for high throughput but requiring more complex hardware. Asynchronous transmission encodes each character with start and stop bits, making it slower but cheaper to implement without a shared clock. Both methods are compared in terms of speed, overhead, complexity and cost.

1. Computer
Peripherals &
Interfacing
Topic: Synchronous & Asynchronous data transmission

2. This is a data transmission method, in which a continuous
stream of data signals is accompanied by timing signals to
ensure that the receiver and transmitter in a step with one
another. This used to describe continuous data transfer.
So this transfers large amount of data one location to
another.
Synchronous
Syn Syn data data data data data
Data flow
This id lower overhead thus, great throughput. But it is
slightly more complex and this hardware is much expensive.

3. Simplified synchronous block data format
syn syn syn
FinishStart
8bit to each character
Data

4. Synchronous serial interface
Transmit
data buffer
register
Receive
data buffer
register
Status
register
Control
register
Control
logic
To data bus
Chip enable
- - - - - - - - - - - -
--------
- - - - - -
- - - - - - - - - - - - - - - -
- - - - - - - -
Clock
Clock
Shift register Shift register
Syn generator Syn recognition
Transmitted serial data Register serial data

5. This is used to describe the process where the
transmitted data encoded with start and stop beat,
specifying the beginning and the ending of each
character.
Asynchronous
It is cheaper than synchronous but this process is slow.
0 0 1 1 1 0 0 1 0 1
Start bit Stop bit

6. Asynchronous character format
Idle State
of line
0
1
Start
bit
5 to 8 data bits
Odd or even
parity or unused
1 to 2 bit times
Stop
elements
Remain idle
or next start bit
P
bit

7. Asynchronous serial interface
Transmit
data buffer
register
Divide by
sixteen
Receive
data buffer
register
Divide by
sixteen
Status
register
Control
register
Control
logic
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Shift register Shift register
Start bit Start bit
Parity &
stop bit
Parity &
stop bit
To data bus External transmit clock External receive clock clock chip enable
Transmitted serial data Register serial data
Serial
out
Serial
bus

8. Sends blocks or frames of data
Fast transmission
Needs a common clock signal, or some
way to sharing it
May have to wait briefly until data can
be send
Synchronous Asynchronous
Sends one byte or character
Slower transmission due to extra
bits and gaps
Cheap and easy to implement, no clock
shearing
Can transmit when ready

9. Prepared by:
Ankon Gopal Banik
Front End Developer | WWF (Web With Friends)
m: +8801771981989
p: 027730402
e: agbanik2081@outlook.com
75-B, Kyetpara, Dhamrai, Dhaka, Bangladesh
www.wwfriends.org

10. Thank you