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F e a tur e s 
• The Intel 8251 is an universal synchronous and 
asynchronous communication controller. 
• It supports standard asynchronous protocol with: 
5 to 8 bit character format 
Odd, even or no parity generation and detection 
Baud rate of 19.2 KBaud 
False start bit detection 
Automatically break detect and handling 
Break character generator
• It has built in baud rate generator. 
• It supports standard synchronous 
protocol with: 
5 to 8 bit character format 
Internal and external character 
synchronization 
Automatic sync insertion 
Baud rate of 64 KBaud
• It allows full duplex transmission and 
reception. 
• It provider error detection logic, which 
detects parity, overrun and framing errors. 
• It has Modem Control Logic, which supports 
basic data set control signals. 
• It is compatible with an extended range of 
Intel microprocessors.
• It provides separate clock inputs for 
receiver and transmitter sections, thus 
providing an option of fixing different 
baud rates for the transmitter and 
receiver section. 
• It is 28 pin IC package.
PIN di a g r am
pin de s c r ipt ion 
• D0 to D7 (I/O Terminal): This is 
bidirectional data bus which 
receive control words, transmits 
data from the CPU, sends status 
words and received data to CPU.
• RESET (Input Terminal): A “High” on 
this input forces the 8251 into “reset 
status.” The device waits for the 
writing of “mode instruction” 
• CLK (Input Terminal): CLK signal is 
used to generate internal device timing. 
CLK signal is independent of RXC or 
TXC.
• WR (Input Terminal): This is the "active low" 
input terminal which receives a signal for 
writing transmit data and control words from 
the CPU into the 8251. 
• RD (Input Terminal): This is the "active low" 
input terminal which receives a signal for 
reading receive data and status words from 
the 8251.
• C/D (Input Terminal): This is an input terminal 
which receives a signal for selecting data or 
command words and status words when the 8251 is 
accessed by the CPU. If C/D = low, data will be 
accessed. If C/D = high, command word or status 
word will be accessed. 
• CS (Input Terminal): This is the "active low" input 
terminal which selects the 8251 at low level when 
the CPU accesses.
• TXD (Output Terminal): This is an 
output terminal for transmitting data 
from which serial-converted data is 
sent out. 
• TXRDY (Output Terminal): This is an 
output terminal which indicates that 
the 8251 is ready to accept a 
transmitted data character.
• TXEMPTY (Output Terminal): This is an 
output terminal which indicates that the 8251 
has transmitted all the characters and had no 
data character. 
• TXC (Input Terminal): This is a clock input 
signal which determines the transfer speed of 
transmitted data. In "synchronous mode," the 
baud rate will be the same as the frequency 
of TXC.
• RXD (Input Terminal): This is a terminal 
which receives serial data. 
• RXRDY (Output Terminal): This is a 
terminal which indicates that the 8251 
contains a character that is ready to READ. 
• RXC (Input Terminal): This is a clock input 
signal which determines the transfer speed of 
received data. In "synchronous mode," the 
baud rate is the same as the frequency of 
RXC.
• SYNDET (Sync Detect)/BRKDET (Break 
Detect) (Input or Output Terminal): This 
pin is used in synchronous mode for 
detection of synchronous characters. 
In asynchronous mode this pin goes high 
to indicate a break in the data stream.
• DSR (Data Set Ready) (Input Terminal): 
This is an input port for MODEM 
interface. The input status of the terminal 
can be recognized by the CPU reading 
status words. 
• DTR (Data Terminal Ready) (Output 
Terminal): This is an output port for 
MODEM interface. It is possible to set 
the status of DTR by a command.
• CTS (Clear To Send) (Input Terminal): 
This is an input terminal for MODEM 
interface which is used for controlling a 
transmit circuit. 
• RTS (Request To Send) (Output 
Terminal): This is an output port for 
MODEM interface. It is possible to set 
the status RTS by a command.
Bloc k di a g r am 
It includes:- 
Data bus buffer 
Read/Write control 
logic 
Modem Control 
Transmit Buffer 
Transmit Control 
Receiver Buffer 
Receiver Control
Prog r amming 
Mode Register:- 
7 6 5 4 3 2 1 0 Mode register 
Number of 
Stop bits 
00: invalid 
01: 1 bit 
10: 1.5 bits 
11: 2 bits 
Parity enable 
0: disable 
1: enable 
Parity 
0: odd 
1: even 
Character length 
00: 5 bits 
01: 6 bits 
10: 7 bits 
11: 8 bits 
Baud Rate 
00: Syn. Mode 
01: x1 clock 
10: x16 clock 
11: x64 clock
Command Register:- 
TxE: transmit enable 
DTR: data terminal ready, DTR pin will be low 
RxE: receiver enable 
SBPRK: send break character 
ER: error reset 
RTS: request to send 
IR: internal reset 
EH: enter hunt mode
Status Register:- 
DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY 
TxRDY: transmit ready 
RxRDY: receiver ready 
TxEMPTY: transmitter empty 
PE: parity error 
OE: overrun error 
FE: framing error 
SYNDET: sync. character detected 
DSR: data set ready

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Pci

  • 1.
  • 2. F e a tur e s • The Intel 8251 is an universal synchronous and asynchronous communication controller. • It supports standard asynchronous protocol with: 5 to 8 bit character format Odd, even or no parity generation and detection Baud rate of 19.2 KBaud False start bit detection Automatically break detect and handling Break character generator
  • 3. • It has built in baud rate generator. • It supports standard synchronous protocol with: 5 to 8 bit character format Internal and external character synchronization Automatic sync insertion Baud rate of 64 KBaud
  • 4. • It allows full duplex transmission and reception. • It provider error detection logic, which detects parity, overrun and framing errors. • It has Modem Control Logic, which supports basic data set control signals. • It is compatible with an extended range of Intel microprocessors.
  • 5. • It provides separate clock inputs for receiver and transmitter sections, thus providing an option of fixing different baud rates for the transmitter and receiver section. • It is 28 pin IC package.
  • 6. PIN di a g r am
  • 7. pin de s c r ipt ion • D0 to D7 (I/O Terminal): This is bidirectional data bus which receive control words, transmits data from the CPU, sends status words and received data to CPU.
  • 8. • RESET (Input Terminal): A “High” on this input forces the 8251 into “reset status.” The device waits for the writing of “mode instruction” • CLK (Input Terminal): CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC.
  • 9. • WR (Input Terminal): This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251. • RD (Input Terminal): This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.
  • 10. • C/D (Input Terminal): This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed. • CS (Input Terminal): This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses.
  • 11. • TXD (Output Terminal): This is an output terminal for transmitting data from which serial-converted data is sent out. • TXRDY (Output Terminal): This is an output terminal which indicates that the 8251 is ready to accept a transmitted data character.
  • 12. • TXEMPTY (Output Terminal): This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data character. • TXC (Input Terminal): This is a clock input signal which determines the transfer speed of transmitted data. In "synchronous mode," the baud rate will be the same as the frequency of TXC.
  • 13. • RXD (Input Terminal): This is a terminal which receives serial data. • RXRDY (Output Terminal): This is a terminal which indicates that the 8251 contains a character that is ready to READ. • RXC (Input Terminal): This is a clock input signal which determines the transfer speed of received data. In "synchronous mode," the baud rate is the same as the frequency of RXC.
  • 14. • SYNDET (Sync Detect)/BRKDET (Break Detect) (Input or Output Terminal): This pin is used in synchronous mode for detection of synchronous characters. In asynchronous mode this pin goes high to indicate a break in the data stream.
  • 15. • DSR (Data Set Ready) (Input Terminal): This is an input port for MODEM interface. The input status of the terminal can be recognized by the CPU reading status words. • DTR (Data Terminal Ready) (Output Terminal): This is an output port for MODEM interface. It is possible to set the status of DTR by a command.
  • 16. • CTS (Clear To Send) (Input Terminal): This is an input terminal for MODEM interface which is used for controlling a transmit circuit. • RTS (Request To Send) (Output Terminal): This is an output port for MODEM interface. It is possible to set the status RTS by a command.
  • 17. Bloc k di a g r am It includes:- Data bus buffer Read/Write control logic Modem Control Transmit Buffer Transmit Control Receiver Buffer Receiver Control
  • 18. Prog r amming Mode Register:- 7 6 5 4 3 2 1 0 Mode register Number of Stop bits 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits Parity enable 0: disable 1: enable Parity 0: odd 1: even Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits Baud Rate 00: Syn. Mode 01: x1 clock 10: x16 clock 11: x64 clock
  • 19. Command Register:- TxE: transmit enable DTR: data terminal ready, DTR pin will be low RxE: receiver enable SBPRK: send break character ER: error reset RTS: request to send IR: internal reset EH: enter hunt mode
  • 20. Status Register:- DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY TxRDY: transmit ready RxRDY: receiver ready TxEMPTY: transmitter empty PE: parity error OE: overrun error FE: framing error SYNDET: sync. character detected DSR: data set ready