Before 2000 area, delay and performance were the most important parameters, if anyone design circuit the main focus was on how much less area is occupied by the circuit on the chip and what the speed is. Now situation is changed, the performance and speed is a secondary concern. In all nanometer (deep sub-micron) technology power becomes the most important parameter in the design. Almost all portable devices run on battery power. Power consumption is a very big challenge in modern-day VLSI design as technology is going to shrinks Because of Increasing transistors count on small chip Higher speed of operations Greater device leakage currents

1. Intro Issues Checks
PowerPlanning
How to Plan your own chip
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, February 2022
Ahmed Abdelazeem ASIC Physical Design

2. Intro Issues Checks
Table of Contents
1 Introduction
2 Power Planning Issues
3 Power Plan Checks
Ahmed Abdelazeem ASIC Physical Design

3. Intro Issues Checks Design Objective Power
Table of Contents
1 Introduction
2 Power Planning Issues
3 Power Plan Checks
Ahmed Abdelazeem ASIC Physical Design

4. Intro Issues Checks Design Objective Power
PowerPlanning
Ahmed Abdelazeem ASIC Physical Design

5. Intro Issues Checks Design Objective Power
Objective of PowerPlanning
To distribute the power from power pads to all elements in
the chip.
Unified supply of power with less voltage drop
A proper Power design should aim at using as less routing
recourse as possible.
Power Analysis (EMIR) check should be done after power
planning is completed
Ahmed Abdelazeem ASIC Physical Design

6. Intro Issues Checks Design Objective Power
PowerPlanning
Creation of the power network within a design
Power planning is integrated with the overall design flow and
must be taken into account early in the design process
because:
# of pads may determine physical size (pad limited).
The power structures within the core area consume physical
area.
The power grid topology effects top level routability, and also
placement and routing within the child blocks.
The power structure effects functionality and reliability.
Ahmed Abdelazeem ASIC Physical Design

7. Intro Issues Checks Design Objective Power
Simplified Power Distribution Architecture
Ahmed Abdelazeem ASIC Physical Design

8. Intro Issues Checks Design Objective Power
Power Network Elements
Power Pad
Trunks
Connects Ring to Power Pad
Power Rings
Form complete rings around the periphery of the die, around
individual hard macros, or inside of hierarchical blocks
higher-level Metal layers Power
Power Stripes
Carries VDD and VSS from Rings across the chip
Horizontal and vertical metal wires placed in an array across
the entire or section die
higher level routing layers
typically uniformly distributed across the die.
Power Rails
Is used to connect the standard cell power rails together, and
or power straps.
Low level, typically metal 1.
Ahmed Abdelazeem ASIC Physical Design

9. Intro Issues Checks Design Objective Power
Power Estimations
Power Estimation is based on total power consumed by the chip:
IO Power
Core Power (Std. Cells +Macros)
Ahmed Abdelazeem ASIC Physical Design

10. Intro Issues Checks Design Objective Power
Power Planning
Power Planning includes:
proper Estimation of power of chip
power routing the design based on the estimation.
We create a mesh kind of structure, so that instance(s) can
take direct supply from the nearest point
We create multiple VDD and VSS lines(for each power
domain)
Hierarchical Mesh from upper metal layers to lowest(Ml or M2
layers for standard cells). Connection from higher to adjacent
lower metal layer is through VIAs
Ahmed Abdelazeem ASIC Physical Design

11. Intro Issues Checks Design Objective Power
Power Mesh
Power/Ground mesh will allow multiple paths from P/G
sources to destinations
Hierarchical power and ground meshes from upper metal layers
to lower metal layers
Multiple vias between layers
Ahmed Abdelazeem ASIC Physical Design

12. Intro Issues Checks Design Objective Power
Why create mesh kind of structure ?
To distribute the Power from power pads/pins to all elements
of the chip.
Provides multiple paths from PG sources to destinations (less
series resistance)
Uniformly distribute power with less voltage drop.
To meet IR/EM targets
For meeting timing requirements
Ahmed Abdelazeem ASIC Physical Design

13. Intro Issues Checks Design Objective Power
Power Planning vs. Power Routing
Ahmed Abdelazeem ASIC Physical Design

14. Intro Issues Checks IR Drop Ground Bounce EM
Table of Contents
1 Introduction
2 Power Planning Issues
3 Power Plan Checks
Ahmed Abdelazeem ASIC Physical Design

15. Intro Issues Checks IR Drop Ground Bounce EM
IR Drop
Reduction in voltage that occurs on power supply networks
IC design expects availability of ideal power supply
In reality, localized voltage drops within the power grid
Increasing current/area on die
Narrower metal line widths (increases power grid resistance)
Results in decreased power supply voltage at cells/transistors
Decreases the operating voltage of the chip, resulting in
timing and functional failures
Ahmed Abdelazeem ASIC Physical Design

16. Intro Issues Checks IR Drop Ground Bounce EM
Reasons of IR Drop Violations
Power structure is not proper.
Cell density is very high.
Instances are not get proper power because of no straps over
there
Mesh structure is proper but there is no via
Ahmed Abdelazeem ASIC Physical Design

17. Intro Issues Checks IR Drop Ground Bounce EM
How to reduce IR drop ?
Routing should be from Top Layer.
By adding some more Power Stripes.
By increasing the width of the metal.
By adding Decaps(DCAP cells).
By using some Low Power Techniques
Ahmed Abdelazeem ASIC Physical Design

18. Intro Issues Checks IR Drop Ground Bounce EM
Ground Bounce
Increase in voltage that occurs on ground networks (VSS or
GND) in integrated circuits
Increase in ground voltage decreases the operating voltage of
the chip, resulting in timing and functional problems
Ahmed Abdelazeem ASIC Physical Design

19. Intro Issues Checks IR Drop Ground Bounce EM
Electromigration
Electromigration is the movement of atoms based on the flow
of current through a material.
If the current density is high enough, the heat dissipated
within the material will repeatedly break atoms from the
structure and move them.
Results of EM in ICs: The VOIDs and HILLOCKS gets
created and potentially causing open and short circuits.
Ahmed Abdelazeem ASIC Physical Design

20. Intro Issues Checks IR Drop Ground Bounce EM
EM violations : Reasons of EM violation
High Fanout Net (multiple fanout cells switch simultaneously,
draws larger current from driver)
Higher Driver Strength Cells(delivers large current
unnecessarily, heating up the wire)
Higher frequency(quick transitions)
Narrow metal width
Metal slotting (resulting into narrower widths)
Long Nets (because of larger resistance, higher localized
temperature)
Ahmed Abdelazeem ASIC Physical Design

21. Intro Issues Checks IR Drop Ground Bounce EM
Solutions of EM violations
Decrease Driver’s drive Strength.
NonDefault (wider) rule based routing.
Insert buffer on long nets.
Route with higher metal layers(lessresistive, higher tolerance
(current carrying capabilities)
Use multi-Cut Via
Break the fanout (have lesser fanouts)
Use wider metals (more width)
Ahmed Abdelazeem ASIC Physical Design

22. Intro Issues Checks Checks
Table of Contents
1 Introduction
2 Power Planning Issues
3 Power Plan Checks
Ahmed Abdelazeem ASIC Physical Design

23. Intro Issues Checks Checks
Power Plan Checks
There should be no open connection
All the Macros should be hooked up with Power/Ground.
IR/EM target should be met.
Missing Vias should be taken care
There should be no Hot Spots (during IR-Drop Analysis)
Ahmed Abdelazeem ASIC Physical Design

24. Intro Issues Checks Checks
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Ahmed Abdelazeem ASIC Physical Design