1. The document describes how to write a finite state machine (FSM) in Verilog using a Moore machine approach. It provides a template for creating an FSM with a state encoding, current state register, state transition logic, and output logic.
2. The template uses parameters to define a state encoding, a register to store the current state, and always blocks with non-blocking assignments to describe the state transition logic and output logic based on the current state.
3. The approach is meant to avoid common Verilog issues while keeping the code concise and readable for describing FSM designs.
1.5 Legal Labels in Verilog areSystem Verilog extends it and al.pdfankit482504
1.
5 Legal Labels in Verilog are:
System Verilog extends it and allows one to add named blocks to reserve word end and join.
Also SystemVerilog allows to add the LABLE or NAMED BLOCK before begin, fork as below.
1.\"MY NAMED_ BLOCK\":Begin
2..\"MY NAMED_ BLOCK\":End
3..\"MY NAMED_ BLOCK\":Fork
4..\"MY NAMED_ BLOCK\":Join
5..\"MY NAMED_ BLOCK\":Initial Begin
It is illegal to have both a label before a begin or fork and a block name after the begin or fork. A
label cannot appear before the end, join, join_any or join_none, as these keywords do not form a
statement.
2.Verilog Provides in-built primitives for basic gate and switch level modeling. Any circuit can
be modeled by using continuous assignment of gate and switch level primitives.
and (strong1, weak0)#(1,2) gate1(out, in1, in2);
This is an and gate with output \'out\' and two inputs in1 and in2. Strong1 and weak0 are
optional driving strengths and gate1 is optional instance name that can be used while debugging.
First parameter in the bracket is output and you can have any number of inputs after that. This is
how you use a 3 input and gate without instance name, delay and driving strengths:
3.verilog has built in primitives like gates,transmission gates,and switches.if we need complex
primitives then verilog provides UDP or simply user defined primitives using UDP we can
model:
1.Combinational Logic
2.Sequential Logic
Verilog has 2 primitives
1.User Defined primitives
2.HDL gate primitive
4.
UDP definitions are independent of modules; they are at the same level as module definitions in
the syntax hierarchy. They can appear anywhere in the source text, either before or after they are
used inside a module. They may not appear between the keywords module and endmodule.
User-Defined Primitives(UDP) :
5. Yes it is True
One of the advanced concepts in verilog
non synthesizable
single output many iput
consume very less memory
I/Os must be scalar (i.e. bit)
1) UDPs can take only scalar input terminals (1 bit). Multiple input terminals are permitted.
2) UDPs can have only one scalar output terminal (1 bit). The output terminal must
always appear first in the terminal list. Multiple output terminals are not allowed.
3) In the declarations section, the output terminal is declared with the keyword output. Since
sequential UDPs store state, the output terminal must also be declared as a reg.
4) The inputs are declared with the keyword input.
5) The state in a sequential UDP can be initialized with an ‘initial’ statement. This statement is
optional. A 1-bit value is assigned to the output, which is declared as reg.
6) The state table entries can contain values 0,1,or x . UDPs do not handle z values. Z values
passed to a UDP are treated x values.
7)UDPs are defined at the same level as modules. UDPs can not be defined inside modules.
They can be instantiated only inside modules. UDPs are instantiated exactly like
gate primitives.
8)UDPs do not support inout ports.
6
The module is the basic unit of hier.
Design of Real - Time Operating System Using Keil µVision Ideiosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
1.5 Legal Labels in Verilog areSystem Verilog extends it and al.pdfankit482504
1.
5 Legal Labels in Verilog are:
System Verilog extends it and allows one to add named blocks to reserve word end and join.
Also SystemVerilog allows to add the LABLE or NAMED BLOCK before begin, fork as below.
1.\"MY NAMED_ BLOCK\":Begin
2..\"MY NAMED_ BLOCK\":End
3..\"MY NAMED_ BLOCK\":Fork
4..\"MY NAMED_ BLOCK\":Join
5..\"MY NAMED_ BLOCK\":Initial Begin
It is illegal to have both a label before a begin or fork and a block name after the begin or fork. A
label cannot appear before the end, join, join_any or join_none, as these keywords do not form a
statement.
2.Verilog Provides in-built primitives for basic gate and switch level modeling. Any circuit can
be modeled by using continuous assignment of gate and switch level primitives.
and (strong1, weak0)#(1,2) gate1(out, in1, in2);
This is an and gate with output \'out\' and two inputs in1 and in2. Strong1 and weak0 are
optional driving strengths and gate1 is optional instance name that can be used while debugging.
First parameter in the bracket is output and you can have any number of inputs after that. This is
how you use a 3 input and gate without instance name, delay and driving strengths:
3.verilog has built in primitives like gates,transmission gates,and switches.if we need complex
primitives then verilog provides UDP or simply user defined primitives using UDP we can
model:
1.Combinational Logic
2.Sequential Logic
Verilog has 2 primitives
1.User Defined primitives
2.HDL gate primitive
4.
UDP definitions are independent of modules; they are at the same level as module definitions in
the syntax hierarchy. They can appear anywhere in the source text, either before or after they are
used inside a module. They may not appear between the keywords module and endmodule.
User-Defined Primitives(UDP) :
5. Yes it is True
One of the advanced concepts in verilog
non synthesizable
single output many iput
consume very less memory
I/Os must be scalar (i.e. bit)
1) UDPs can take only scalar input terminals (1 bit). Multiple input terminals are permitted.
2) UDPs can have only one scalar output terminal (1 bit). The output terminal must
always appear first in the terminal list. Multiple output terminals are not allowed.
3) In the declarations section, the output terminal is declared with the keyword output. Since
sequential UDPs store state, the output terminal must also be declared as a reg.
4) The inputs are declared with the keyword input.
5) The state in a sequential UDP can be initialized with an ‘initial’ statement. This statement is
optional. A 1-bit value is assigned to the output, which is declared as reg.
6) The state table entries can contain values 0,1,or x . UDPs do not handle z values. Z values
passed to a UDP are treated x values.
7)UDPs are defined at the same level as modules. UDPs can not be defined inside modules.
They can be instantiated only inside modules. UDPs are instantiated exactly like
gate primitives.
8)UDPs do not support inout ports.
6
The module is the basic unit of hier.
Design of Real - Time Operating System Using Keil µVision Ideiosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
DOUBLE PRECISION FLOATING POINT CORE IN VERILOGIJCI JOURNAL
A floating-point unit (FPU) is a math coprocessor, a part of a computer system specially designed to carry
out operations on floating point numbers. The term floating point refers to the fact that the radix point can
"float"; that is, it can placed anywhere with respect to the significant digits of the number. Double
precision floating point, also known as double, is a commonly used format on PCs due to its wider range
over single precision in spite of its performance and bandwidth cost. This paper aims at developing the
verilog version of the double precision floating point core designed to meet the IEEE 754 standard .This
standard defines a double as sign bit, exponent and mantissa. The aim is to build an efficient FPU that
performs basic functions with reduced complexity of the logic used and also reduces the memory
requirement as far as possible.
This material is developed in such beautiful manner to the beginners of C language can understand it accurately.
Every concept In material is explained in well disciplined.
Even it will be helpful to the professors for presenting lecture in class room
Introduction to C Language - Version 1.0 by Mark John LadoMark John Lado, MIT
The C programming language is a general-purpose, high – level language (generally denoted as structured language). C programming language was at first developed by Dennis M. Ritchie at At&T Bell Labs.
C is one of the most commonly used programming languages. It is simple and efficient therefore it becomes best among all. It is used in all extents of application, mainly in the software development.
Many software's & applications as well as the compilers for the other programming languages are written in C also Operating Systems like Unix, DOS and windows are written in C.
C has many powers, it is simple, stretchy and portable, and it can control system hardware easily. It is also one of the few languages to have an international standard, ANSI C.
Customizable Microprocessor design on Nexys 3 Spartan FPGA BoardBharat Biyani
- Designed a 4 stage pipelined, 16-bit customizable microprocessor in VHDL which can execute instructions (direct & memory mapped addressing modes), handle interrupts (IVT based), communicate with IO devices including keyboard and VGA monitor and facilitates with a single port BLOCK RAM for Stack, Instruction , Data & IVT memory. Keyboard and VGA controller provides input-output interface gives user flexibility of keying in the instructions through Keyboard that is interfaced with Nexys 3 through USB 2.0; VGA interface to display the output. Keyboard and VGA controllers are also coded in VHDL.
- Implemented the VHDL code on Nexys 3 Spartan FPGA board which involved simulation, synthesis and bit file generation using Xilinx ISE,programming the FPGA with Digilent Adept.
- Employed the debug mode to make the design more user friendly
Implementation of FSM-MBIST and Design of Hybrid MBIST for Memory cluster in ...Editor IJCATR
In current scenario, power efficient MPSoC’s are of great demand. The power efficient asynchronous MPSoC’s with
multiple memories are thought-off to replace clocked synchronous SoC, in which clock consumes more than 40% of the total power. It
is right time to develop the test compliant asynchronous MpSoC. In this paper, Traditional MBIST and FSM based MBIST schemes
are designed and applied to single port RAM. The results are discussed based on the synthesis reports obtained from RTL Complier
from Cadence. FSM based MBIST is power and area efficient method for single memory testing. It consumes 40% less power when
compared with traditional MBIST. But, in case of multiple memory scenarios, separate MBIST controllers are required to test each
individual memories. Thus this scheme consumes huge area and becomes inefficient. A novel technique for testing different memories
which are working at different frequencies is in need. Therefore, an area efficient Hybrid MBIST is proposed with single MBIST
controller to test multiple memories in an Asynchronous SoC. It also includes multiple test algorithms to detect various faults. An
Asynchronous SoC with DWT processor and multiple memories is discussed in this paper, which will used as Design under Test
[DUT] and Hybrid MBIST is built around it to test the heterogeneous memories. The design is coded in Verilog and Validated in
Spartan-3e FPGA kit.
CSCI 2121- Computer Organization and Assembly Language Labor.docxannettsparrow
CSCI 2121- Computer Organization and Assembly Language
Laboratory No. 5
Week of March 12th, 2018
Submission Instructions:
1. Save the files as shift.sv and vending.sv
2. Put all files into one folder.
3. Compress the folder into a .zip file.
4. Submit the zip file on Brightspace.
5. Submission Deadline: Sunday, April 15th, 2018, 11.55PM
SRC CHIP PROJECT
In order to proceed on the project for this course, there are several key Verilog concepts which are
necessary in the implementation of this code.
Part 0: More Verilog concepts.
Shared busses and tri-state buffers
Before we begin implementing the CPU, let's go over a few concepts which will be needed for the lab
assignment. The first is the concept of a shared bus. We've already seen busses in Verilog in terms of an
array of wires or registers, however in the context of our CPU, the word "bus" has another meaning. Our
CPU uses a shared "bus" which is a wire connected between the inputs and outputs of many different
registers, in order to share data:
This can be easily modelled in Verilog, using the inout keyword for a module. This defines a wire which
can act as both an input and an output to our module. However, there is one critically important design
concept which goes along with the usage of shared busses:
Only one signal can be written to a shared bus at any given time.
If two signals are written to the bus, the result is a bus collision, and the value is undefined. In the
simulation, this is represented as "X", but in real life this would cause garbage data to exist on the bus,
potentially corrupting any process which is running on the CPU. As Verilog programmers, it's our job to
ensure that a bus collision never happens. To facilitate this, we'll use a digital logic component called a
tri-state buffer:
The purpose of a tri-state buffer is to act as a switch. If B is 1, then the data can pass through the buffer,
but if not, it simply disconnects the wire, outputting a high-impedance state (in Verilog, denoted by Z).
hz943141
A B C
0 0 Z
0 1 0
1 0 Z
1 1 1
In Verilog, we can't directly write a tri-state buffer, but it can be easily synthesized using a ternary
operator as shown on line 11:
Line 11 shows the construction of a ternary operator to use as a tri-state buffer. If the input called
activate_out is set to 1, then the tri-state buffer is activated, and the circuit will put my_result on the
bus. Otherwise, it puts the value 32'bz on the bus, which will disconnect my_result from the bus, and
allow another circuit to write to the bus.
Note: It is important that during your lab assignment, any circuits which write to the bus have a tri-
state buffer implemented to prevent bus collisions.
Verilog Tasks:
Verilog tasks are like object functions in Java. Read more about them here. You may find that they are
useful in separating the code for instructions within a module, particularly for th.
Android Application Development - Level 3Isham Rashik
Final level of the Android Application Development series. With this tutorial documentation, this will enable mobile developers to gain complete basic knowledge of Android Development. After completing all 3 of the levels, the developers can proceed with intermediary and advanced concepts.
Recipes 9 of Data Warehouse and Business Intelligence - Techniques to control...Massimo Cenci
In the loading of a Data Warehouse is important to have full control of the processing units that compose it.
Each processing unit must be carefully monitored both in the detection of errors that may occur,
both in the analysis of the execution times
This chapter contains information for memory compilers available in STDL80 cell library. These are
complete compilers that consist of various generators to satisfy the requirements of the circuit at hand. Each
of the final building block, the physical layout, will be implemented as a stand-alone, densely packed,
pitch-matched array. Using this complex layout generator and adopting state-of-the-art logic and circuit
design technique, these memory cells can realize extreme density and performance. In each layout
generator, we added an option which makes the aspect ratio of the physical layout selectable so that the
ASIC designers can choose the aspect ratio according to the convenience of the chip level layout.
Sign off in VLSI is used to represent the completion of the design process. It is the final stage of the design cycle, in which all aspects of the chip are verified to make sure it meets the desired specifications. Sign off includes the physical verification of the design, the timing verification of the design, the power verification of the design, and the electrical verification of the design. Once all these verifications are completed and the chip is deemed to be functioning as expected, the design can be signed off
DOUBLE PRECISION FLOATING POINT CORE IN VERILOGIJCI JOURNAL
A floating-point unit (FPU) is a math coprocessor, a part of a computer system specially designed to carry
out operations on floating point numbers. The term floating point refers to the fact that the radix point can
"float"; that is, it can placed anywhere with respect to the significant digits of the number. Double
precision floating point, also known as double, is a commonly used format on PCs due to its wider range
over single precision in spite of its performance and bandwidth cost. This paper aims at developing the
verilog version of the double precision floating point core designed to meet the IEEE 754 standard .This
standard defines a double as sign bit, exponent and mantissa. The aim is to build an efficient FPU that
performs basic functions with reduced complexity of the logic used and also reduces the memory
requirement as far as possible.
This material is developed in such beautiful manner to the beginners of C language can understand it accurately.
Every concept In material is explained in well disciplined.
Even it will be helpful to the professors for presenting lecture in class room
Introduction to C Language - Version 1.0 by Mark John LadoMark John Lado, MIT
The C programming language is a general-purpose, high – level language (generally denoted as structured language). C programming language was at first developed by Dennis M. Ritchie at At&T Bell Labs.
C is one of the most commonly used programming languages. It is simple and efficient therefore it becomes best among all. It is used in all extents of application, mainly in the software development.
Many software's & applications as well as the compilers for the other programming languages are written in C also Operating Systems like Unix, DOS and windows are written in C.
C has many powers, it is simple, stretchy and portable, and it can control system hardware easily. It is also one of the few languages to have an international standard, ANSI C.
Customizable Microprocessor design on Nexys 3 Spartan FPGA BoardBharat Biyani
- Designed a 4 stage pipelined, 16-bit customizable microprocessor in VHDL which can execute instructions (direct & memory mapped addressing modes), handle interrupts (IVT based), communicate with IO devices including keyboard and VGA monitor and facilitates with a single port BLOCK RAM for Stack, Instruction , Data & IVT memory. Keyboard and VGA controller provides input-output interface gives user flexibility of keying in the instructions through Keyboard that is interfaced with Nexys 3 through USB 2.0; VGA interface to display the output. Keyboard and VGA controllers are also coded in VHDL.
- Implemented the VHDL code on Nexys 3 Spartan FPGA board which involved simulation, synthesis and bit file generation using Xilinx ISE,programming the FPGA with Digilent Adept.
- Employed the debug mode to make the design more user friendly
Implementation of FSM-MBIST and Design of Hybrid MBIST for Memory cluster in ...Editor IJCATR
In current scenario, power efficient MPSoC’s are of great demand. The power efficient asynchronous MPSoC’s with
multiple memories are thought-off to replace clocked synchronous SoC, in which clock consumes more than 40% of the total power. It
is right time to develop the test compliant asynchronous MpSoC. In this paper, Traditional MBIST and FSM based MBIST schemes
are designed and applied to single port RAM. The results are discussed based on the synthesis reports obtained from RTL Complier
from Cadence. FSM based MBIST is power and area efficient method for single memory testing. It consumes 40% less power when
compared with traditional MBIST. But, in case of multiple memory scenarios, separate MBIST controllers are required to test each
individual memories. Thus this scheme consumes huge area and becomes inefficient. A novel technique for testing different memories
which are working at different frequencies is in need. Therefore, an area efficient Hybrid MBIST is proposed with single MBIST
controller to test multiple memories in an Asynchronous SoC. It also includes multiple test algorithms to detect various faults. An
Asynchronous SoC with DWT processor and multiple memories is discussed in this paper, which will used as Design under Test
[DUT] and Hybrid MBIST is built around it to test the heterogeneous memories. The design is coded in Verilog and Validated in
Spartan-3e FPGA kit.
CSCI 2121- Computer Organization and Assembly Language Labor.docxannettsparrow
CSCI 2121- Computer Organization and Assembly Language
Laboratory No. 5
Week of March 12th, 2018
Submission Instructions:
1. Save the files as shift.sv and vending.sv
2. Put all files into one folder.
3. Compress the folder into a .zip file.
4. Submit the zip file on Brightspace.
5. Submission Deadline: Sunday, April 15th, 2018, 11.55PM
SRC CHIP PROJECT
In order to proceed on the project for this course, there are several key Verilog concepts which are
necessary in the implementation of this code.
Part 0: More Verilog concepts.
Shared busses and tri-state buffers
Before we begin implementing the CPU, let's go over a few concepts which will be needed for the lab
assignment. The first is the concept of a shared bus. We've already seen busses in Verilog in terms of an
array of wires or registers, however in the context of our CPU, the word "bus" has another meaning. Our
CPU uses a shared "bus" which is a wire connected between the inputs and outputs of many different
registers, in order to share data:
This can be easily modelled in Verilog, using the inout keyword for a module. This defines a wire which
can act as both an input and an output to our module. However, there is one critically important design
concept which goes along with the usage of shared busses:
Only one signal can be written to a shared bus at any given time.
If two signals are written to the bus, the result is a bus collision, and the value is undefined. In the
simulation, this is represented as "X", but in real life this would cause garbage data to exist on the bus,
potentially corrupting any process which is running on the CPU. As Verilog programmers, it's our job to
ensure that a bus collision never happens. To facilitate this, we'll use a digital logic component called a
tri-state buffer:
The purpose of a tri-state buffer is to act as a switch. If B is 1, then the data can pass through the buffer,
but if not, it simply disconnects the wire, outputting a high-impedance state (in Verilog, denoted by Z).
hz943141
A B C
0 0 Z
0 1 0
1 0 Z
1 1 1
In Verilog, we can't directly write a tri-state buffer, but it can be easily synthesized using a ternary
operator as shown on line 11:
Line 11 shows the construction of a ternary operator to use as a tri-state buffer. If the input called
activate_out is set to 1, then the tri-state buffer is activated, and the circuit will put my_result on the
bus. Otherwise, it puts the value 32'bz on the bus, which will disconnect my_result from the bus, and
allow another circuit to write to the bus.
Note: It is important that during your lab assignment, any circuits which write to the bus have a tri-
state buffer implemented to prevent bus collisions.
Verilog Tasks:
Verilog tasks are like object functions in Java. Read more about them here. You may find that they are
useful in separating the code for instructions within a module, particularly for th.
Android Application Development - Level 3Isham Rashik
Final level of the Android Application Development series. With this tutorial documentation, this will enable mobile developers to gain complete basic knowledge of Android Development. After completing all 3 of the levels, the developers can proceed with intermediary and advanced concepts.
Recipes 9 of Data Warehouse and Business Intelligence - Techniques to control...Massimo Cenci
In the loading of a Data Warehouse is important to have full control of the processing units that compose it.
Each processing unit must be carefully monitored both in the detection of errors that may occur,
both in the analysis of the execution times
This chapter contains information for memory compilers available in STDL80 cell library. These are
complete compilers that consist of various generators to satisfy the requirements of the circuit at hand. Each
of the final building block, the physical layout, will be implemented as a stand-alone, densely packed,
pitch-matched array. Using this complex layout generator and adopting state-of-the-art logic and circuit
design technique, these memory cells can realize extreme density and performance. In each layout
generator, we added an option which makes the aspect ratio of the physical layout selectable so that the
ASIC designers can choose the aspect ratio according to the convenience of the chip level layout.
Sign off in VLSI is used to represent the completion of the design process. It is the final stage of the design cycle, in which all aspects of the chip are verified to make sure it meets the desired specifications. Sign off includes the physical verification of the design, the timing verification of the design, the power verification of the design, and the electrical verification of the design. Once all these verifications are completed and the chip is deemed to be functioning as expected, the design can be signed off
Routing in VLSI is making physical connections between signal pins using metal layers. Following Clock Tree Synthesis (CTS) and optimization, the routing step determines the exact pathways for interconnecting standard cells, macros, and I/O pins.
Global Routing
first partitions the routing region into tiles/rectangles called global routing cells (gcells) and decides tile-to-tile paths for all nets while attempting to optimize some given objective function (e.g., total wire length and circuit timing), but doesn’t make actual connections or assign nets to specific paths within the routing regions.
By default, the width of a gcells is same as the height of a standard cell and is aligned with the standard cell rows.
Every gcell having the a number of horizontal routing resources and vertical routing resources.
Global routing assigns nets (logical connectivity not metal connectivity) to specific metal layers and global routing cells.
Track Assignment
Track assignment is a stage wherein the routing tracks are assigned for each global routes. The tasks that are performed during this stage are as follows
Assigning tracks in horizontal and vertical partitions.
Rerouting all overlapped wires.
Track Assignment replaces all global routes with actual metal layers.
Although all nets are routed (not very carefully), there will be many DRC, SI and timing related violations, especially in regions where the routing connects the pins. These violations are fixed in the succeeding stages.
Detail Routing
The detailed router uses the routing plan laid by the router during the Global Routing and Track Assignment and lays actually metal to logically connect pins with nets and other pins in the design.
The violations that were created during the Track Assignment stage are fixed through multiple iterations in this stage.
The main goal of detailed routing is to complete all the required interconnect without leaving shorts or spacing violations.
The detailed routing starts with the router dividing the block into specific areas called switch boxes or Sbox, which are generally expressed in terms of gcells.
Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.
Clock tree network enables in making design clean from a timing perspective. However, it is responsible for more than one third of the total power consumption of the chip. The impact of variations in the clock path is more than 2 times the other paths in the design. These variations in-turn affects the timing paths. Let us take an example; Due to the variation, if the clock path to the launching register is slowed down by 100ps and the clock path to the capturing register is fastened by 100ps then it impacts the setup constraint by adding 200ps more to it, this in-turn affects the timing path by making it more critical. Here we can see the importance of building a balanced clock tree. We will discuss on the timing improvements and methods to reduce the variations in the clock tree. The steps followed in building a customized clock tree and the steps followed to bring down the variations in the clock tree has been depicted in the following sections.
Placement is the process of determining the locations of circuit devices on a die
surface. It is an important stage in the VLSI design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a
design. Traditionally, it is applied after the logic synthesis stage and before the
routing stage. Since the advent of deep submicron process technology around
the mid-1990s, interconnect delay, which is largely determined by placement,
has become the dominating component of circuit delay. As a result, placement
information is essential, even in early design stages, to achieve better circuit performance. In recent years, placement techniques have been integrated into the
logic synthesis stage to perform physical synthesis and into the architecture
design stage to perform physical-aware architecture design
In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally, it is a NP hard problem. So many researchers from time to time have suggested various heuristics and metaheuristic approaches for solving the VLSI Floorplan Problem. The Floorplan representation is another important aspect of the Floorplanning Stage. Representations have a great impact on the complexity of the Floorplan design. In this paper, we survey the VLSI Floorplanning problem which includes studying and comparing the different optimization algorithms and the representations involved in the VLSI Floorplanning problem. Additionally we suggest some of the new approaches for solving the floorplanning problem which has not yet been employed in this regard.
Physical design means --->> netlist (.v ) converted into GDSII form(layout form)
logical connectivity of cells converted into physical connectivity.
During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer, are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers.
Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.
Performance: long routes have significantly longer signal delays.
Area: placing connected modules far apart results in larger and slower chips.
Reliability: A large number of vias can significantly reduce the reliability of the circuit.
Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens
What is the Difference Between the target_library and link_library Variables?Ahmed Abdelazeem
Design Compiler already has the set target_library my_lib.db command.
Why is it necessary to also use the set link_library "* my_lib.db"
command? Can you explain the difference?
Makefiles are used to help decide which parts of a large program need to be recompiled. In the vast majority of cases, C or C++ files are compiled. Other languages typically have their own tools that serve a similar purpose as Make. Make can also be used beyond compilation too, when you need a series of instructions to run depending on what files have changed. This tutorial will focus on the C/C++ compilation use case.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
In VLSI design, Design for Testability (DFT) is an approach that aims to make digital circuits easier to test during the manufacturing and debugging process. DFT in VLSI design involves incorporating additional circuitry and design features such as scan chains, built-in self-test (BIST) circuits, and boundary scan cells into the chip design to facilitate testing. Design for testability in VLSI design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects. It also reduces the overall test time and thereby the cost of testing, and debugging. By incorporating DFT techniques into the chip design, it becomes easier to test the structural correctness of the chip, leading to higher-quality products and faster time-to-market.
Equivalence checking is a portion of a larger discipline called formal verification. This technology uses mathematical modeling techniques to prove that two representations of design exhibit the same behavior. This approach should not be confused with functional verification, which uses exhaustive simulation to verify the correctness of a design.
Once a verified version of a design has been identified, equivalence checking can be used to determine if an alternate representation of the design behaves the same as the verified version. This technique does not use input vectors so it is more efficient.
Equivalence checking is useful to verify that a design’s function has not changed after an operation like synthesis, or after a functional ECO has been applied.
Synthesis in VLSI is the process of converting your code (program) into a circuit. In terms of logic gates, synthesis is the process of translating an abstract design into a properly implemented chip. Hardware Description Languages (HDLs) are specific programming languages that are used to explain the hardware of a circuit, and the computer subsequently builds the circuit depending on the programme you provided. A “Gate Level Netlist” is what you get once you finish synthesising. This is how your circuit will appear. It demonstrates how everything is interconnected. You can alter it if you like; the computer just synthesizes this netlist based on its best judgement. The synthesizer generates better netlists as the abilities improve and they become more proficient at creating HDL programmes.
Routing is an important step in the design of integrated circuits. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. But the connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input. Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by inserting buffers/inverters along the clock routes of an ASIC design. As a result, CTS is used to balance the skew and reduce insertion latency. Before Clock Tree Synthesis, all clock pins were driven by a single clock source. Clock tree synthesis includes both clock tree construction and clock tree balance. Clock tree inverters may be used to create a clock tree that maintains the correct transition (duty cycle), and clock tree buffers (CTB) can balance the clock tree to fulfil the skew and latency requirements. To fulfil the space and power limits, fewer clock tree inverters and buffers should be employed.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
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Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
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1. 1There must always be an initial state for the FSM to start at after a Reset.
1
ECE105: Finite State Machines in Verilog
KAUST College of Engineering
Department of Electrical Engineering and Computer Science
1 Introduction
This document describes how to write a finite state machine (FSM) in Verilog. Specifically, in EECS150,
you will be designing Moore machines for your project. This document only discusses how to describe
Moore machines.
Moore machines are very useful because their output signals are synchronized with the clock. No
matter when input signals reach the Moore Machine, its output signals will not change until the rising
edge of the next clock cycle. This is very important to avoid setup timing violations. For example, if
a Mealy machine’s input signal(s) changes sometime in the middle of a clock cycle, one or more of its
outputs and next state signals may change some time later. “Some time later” might come after the
setup time threshold for the next rising edge. If this happens, the registers that will hold the FSMs next
state may receive garbage, or just incorrect inputs. Obviously, this amounts to a bug(s) in your FSM. A
very painful and difficult-to-find bug at that.
The tradeoff in using the Moore machine is that sometimes the Moore machine will require more
states to specify its function than the Mealy machine. This is because in a Moore machine, output
signals are only dependent on the current state. In a Mealy machine, outputs are dependent on both
the current state and the inputs. The Mealy machine allows you to specify different output behavior for
a single state. In EECS150, however, the FSMs that you will be designing do not typically have enough
states for this to create a significant problem. We will err on the side of caution, and vie for a safe but
sometimes more verbose FSM implementation, in this course.
2 Motivation
EECS150 is concerned with circuit design. You will be using Verilog to describe your circuits. Unfor-
tunately, Verilog, being originally designed to support circuit simulation rather than circuit synthesis, is
chalked full of syntactical idiosyncrasies that, if not properly understood, will create odd bugs in your
designs. This document will show you how to write a Moore FSM in a template-based fashion. This
“cookie-cutter” approach is designed to avoid Verilog’s bug-prone areas, while keeping your code as non-
verbose as possible. Verilog is a means to an end. This document will show you how to get to the point:
designing circuits; while fighting Verilog as little as possible.
3 A Basic FSM
Figure 1 depicts an example Moore FSM. You can tell that this is a Moore machine because the outputs
are shown inside [. . .]s instead of on state transition arcs. The following sections will refer to Figure 1 as
an example use-case for the Moore machine FSM template.
The FSM shown in Figure 1 is useful because it exemplifies the following:
1. The concept of an initial state.1
2. States with non-conditional outward transitions.
3. States with conditional outward transitions.
2. Figure 1 A basic FSM
!(A & B)
!((!A & B) | (A & !B))
A & !B
!A & B
A
!A
A & B
Reset
STATE_1
[Output1]
STATE_2
[Output1,
Output2,
Status = 3'b010]
STATE_3
[Status = 3'b011]
STATE_Initial
STATE_4
& logical and
| logical or
! logical not
4. States that loop back onto themselves.
5. States with no outward transitions.
We would like to be able to express this type of behavior in a Verilog-written FSM.
4 The FSM in Verilog
In looking at Figure 1, we will need a way to express the following in Verilog:
1. A state encoding for each state.
2. A mechanism for keeping track of the current state.
3. Transitions from state to state.
4. Output values based on the current state.
We will construct the FSM one step at a time.
4.1 1: Creating a State Encoding
We will create our state encoding with Verilog parameters. Parameters are symbolic constants with
either global (given by the Verilog keyword parameter) or module (localparam) scope. Because we only
want our state encoding to be visible to the module in which we will write the FSM, we will use the
latter: localparam. With this in mind, we can specify Program 1.
2
3. Program 1 The state encoding (in decimal)
1 localparam STATE_Initial = 3’d0 ,
2 STATE_1 = 3’d1 ,
3 STATE_2 = 3’d2 ,
4 STATE_3 = 3’d3 ,
5 STATE_4 = 3’d4;
In Program 1, the 3’d notation indicates that the number specified is in the decimal radix. If we were
to use 3’b, the encoding would look like that shown in Program 2. Both implementations are equivelent.
Base 10, or 3’d, is typically easier to read.
Because this FSM has 5 total states, we must allocate 3 bits to specify the encoding (hence 3’d
as opposed to 2’d or 4’d. This is extremely important. If you specify too few bits for your state
encoding, Verilog will not warn you. In fact, when synthesized, each state will only get as many bits as
you provide. For example, if STATE_4 was specified like this: STATE_4 = 2’d4, STATE_4 would be specified
as 00, the bottem 2 bits of what was intended, namely 100.
Program 2 The state encoding (in binary)
1 localparam STATE_Initial = 3’b000 ,
2 STATE_1 = 3’b001 ,
3 STATE_2 = 3’b010 ,
4 STATE_3 = 3’b011 ,
5 STATE_4 = 3’b100;
As 3 bits can specify a total of 8 states (0-7), our encoding specifies 3 potential states not specified
as being actual states. There are several ways of dealing with this problem:
1. Ignore it, and always press Reset as a way of initializing the FSM.
2. Specify these states, and make non-conditional transitions from them to the STATE_Initial.
To reduce ambiguity, we will choose the second option, which makes our final state encoding that
shown in Program 3.
Program 3 The state encoding with place-holder states (in decimal)
1 localparam STATE_Initial = 3’d0 ,
2 STATE_1 = 3’d1 ,
3 STATE_2 = 3’d2 ,
4 STATE_3 = 3’d3 ,
5 STATE_4 = 3’d4 ,
6 STATE_5_PlaceHolder = 3’d5 ,
7 STATE_6_PlaceHolder = 3’d6 ,
8 STATE_7_PlaceHolder = 3’d7;
This is a simple encoding: STATE_Initial is assigned 0, STATE_1 is assigned 1, etc. This is not
optimal if state minimization can be performed on the FSM (taught at the end of EECS150). We do
not recommend applying state minimization techniques by hand, however. They have the tendancy to
introduce bugs and create cryptic FSMs that cannot be easily understood by human readers. This defeats
one of the large pros of Verilog: human readability. Furthermore, the Synthesis tools that ‘compile’ an
FSM, written in Verilog, perform state minimization automatically. Only perform state minimization
manually to the extent that the function of the FSM remains clear.
3
4. 4.2 2: Keeping Track of the Current State
We have several options in how to store the current state of our FSM. The first option is to instantiate a
module that acts as a register and use its output value as our current state. Alternatively, we can create
a reg element of the appropriate width and use its value as our current state. We will use the second
method for the remainder of this tutorial, out of personal preference. As such, we will store the current
state as depicted in Program 4.
Program 4 Storing the current state in a reg
1 reg [2:0] CurrentState;
If this material seems unfamilar, read Section 4.2.1, which explains the difference betweeen wire
and reg elements in Verilog. If this material is familiar, feel free to skip to Section 4.3.
4.2.1 wire and reg Elements in Verilog
Sections 4.2.3 to 4.2.5 discuss the difference between wire and reg in Verilog, and when to use each of
them.
4.2.2 Conventions
Throughout this tutorial, similar terms are used to describe different concepts. These possible sources
of confusion are explained below:
Module Instantiation : Refer to modules instantiated in other modules. Program 5 shows examples
of input/output ports for a simple module instantiation.
Module Declaration : Refer to the actual Verilog code written for a module. Program 6 shows
examples of inputs/outputs within a module declaration. Notice that each input and output
is declared twice in the code. This is important so that inputs and outputs can be assigned
parameterizable widths (in this example, ‘Width’ is used as an example parameter).
Program 5 Module instantiation.
1 Register #( .Width( ...))
2 SentReg (. Clock( ...) , // Input port
3 .Reset( ...) , // Input port
4 .Set( ...) , // Input port
5 .Enable (...) , // Input port
6 .In( ...) , // Input port
7 .Out( ...)); // OUTPUT port
Program 6 Module declaration.
1 module MyModule(In , Out);
2 ...
3 parameter Width = 32;
4 ...
5 input [Width -1:0] In , Out;
6 ...
7 endmodule
4
5. 4.2.3 wire Elements (Combinational logic)
wire elements are simple wires (or busses/bit-vectors of arbitrary width) in Verilog designs. The following
are syntax rules when using wires:
1. wire elements are used to connect input and output ports of a module instantiation together with
some other element in your design.
2. wire elements are used as inputs and outputs within an actual module declaration.
3. wire elements must be driven by something, and cannot store a value without being driven. In
other words, wire elements are a stateless way of connecting two peices in a Verilog-based design.
4. wire elements cannot be used as the left-hand side of an = or <= sign in an always@ block.
5. wire elements are the only legal type on the left-hand side of an assign statement.
6. wire elements can only be used to model combinational logic.
Program 7 shows various legal uses of the wire element.
Program 7 Legal uses of the wire element
1 wire A, B, C, D, E; // simple 1-bit wide wires
2 wire [8:0] Wide; // a 9-bit wide wire
3 reg I;
4
5 assign A = B & C; // using a wire with an assign statement
6
7 always @(B or C) begin
8 I = B | C; // using wires on the right -hand side of an always@
9 // assignment
10 end
11
12 mymodule MyModule (.In (D), // using a wire as the input of a module
13 .Out(E)); // using a wire as the output of a module
4.2.4 reg Elements (Combinational and Sequential logic)
reg are similar to wires, but can be used to store information (‘state’) like registers. The following are
syntax rules when using reg elements.
1. reg elements can be connected to the input port of a module instantiation. Note that reg cannot
connect to the output port of a module instantiation.
2. reg elements can be used as outputs within an actual module declaration. Note that reg cannot
be used as inputss within an actual module declaration.
3. reg is the only legal type on the left-hand side of an always@ block = or <= sign.
4. reg is the only legal type on the left-hand side of an initial block = sign (used in Test Benches).
5. reg cannot be used on the left-hand side of an assign statement.
6. reg can be used to create registers when used in conjunction with always@(posedge Clock) blocks.
7. reg can, therefore, be used to create both combinational and sequential logic.
Program 8 shows various legal uses of the reg element.
5
6. Program 8 Legal uses of the reg element
1 wire A, B;
2 reg I, J, K; // simple 1-bit wide reg elements
3 reg [8:0] Wide; // a 9-bit wide reg element
4
5 always @(A or B) begin
6 I = A | B; // using a reg as the left -hand side of an always@
7 // assignment
8 end
9
10 initial begin // using a reg in an initial block
11 J = 1’b1;
12 #1
13 J = 1’b0;
14 end
15
16 always @(posedge Clock) begin
17 K <= I; // using a reg to create a positive -edge -triggered register
18 end
4.2.5 When wire and reg Elements are Interchangable
wire and reg elements can be used interchangably in certain situations:
1. Both can appear on the right-hand side of assign statements and always@ block = or <= signs.
2. Both can be connected to the input ports of module instantiations.
4.3 3: Transitioning from State to State
After we have established our state encoding and a means of storing the current state value (which will
henceforth be referred to as CurrentState), our next task is to create a way for the FSM to actually
change state, and for it to choose how to change state. This material requires that you be comfortable
with always@ blocks. If the always@ block is unfamilar, read Section 4.3.1, which explains always@
block in Verilog. If the always@ block is familiar, feel free to skip to Section 4.3.8.
4.3.1 always@ Blocks in Verilog
Sections 4.3.2 to 4.3.7 discuss always@ blocks in Verilog, and when to use the two major flavors of always@
block, namely the always@( * ) and always@(posedge Clock) block.
4.3.2 always@ Blocks
always@ blocks are used to describe events that should happen under certain conditions. always@ blocks
are always followed by a set of parentheses, a begin, some code, and an end. Program 9 shows a skeleton
always@ block.
Program 9 The skeleton of an always@ block
1 always @( ... sensitivity list ... ) begin
2 ... elements ...
3 end
In Program 9, the sensitivity list is discussed in greater detail in Section 4.3.6. The contents
of the always@ block, namely elements describe elements that should be set when the sensitivity list
6
7. is “satisfied.” For now, just know that when the sensitivity list is “satisfied,” the elements inside the
always@ block are set/updated. They are not otherwise.
Elements in an always@ block are set/updated in sequentially and in parallel, depending on the type
of assignment used. There are two types of assignments: <= (non-blocking) and = (blocking).
4.3.3 <= (non-blocking) Assignments
Non-blocking assignments happen in parallel. In other words, if an always@ block contains multiple <=
assignments, which are literally written in Verilog sequentially, you should think of all of the assignments
being set at exactly the same time. For example, consider Program 10.
Program 10 <= assignments inside of an always@ block
4 always @( ... sensitivity list ... ) begin
5 B <= A;
6 C <= B;
7 D <= C;
8 end
Program 10 specifies a circuit that reads “when the sensitivity list is satisfied, B gets A’s value, C gets
B’s old value, and D gets C’s old value.” The key here is that C gets B’s old value, etc (read: think OLD
value!. This ensures that C is not set to A, as A is B’s new value, at the instant of the always@ block’s
execution. Non-blocking assignments are used when specifying sequential2
logic (see Section 4.3.5).
4.3.4 = (blocking) Assignments
Blocking assignments happen sequentially. In other words, if an always@ block contains multiple =
assignments, you should think of the assignments being set one after another. For example, consider
Program 11.
Program 11 = assignments inside of an always@ block
1 always @( ... sensitivity list ... ) begin
2 B = A;
3 C = B;
4 D = C;
5 end
Program 11 specifies a circuit that reads “when the sensitivity list is satisfied, B gets A, C gets B, and
D gets C.” But, by the time C gets B, B has been set to A. Likewise, by the time D gets C, C has been set
to B, which, as we stated above, has been set to A. This always@ block turns B, C, and D into A. Blocking
assignments are used when specifying combinational logic (see Section 4.3.6).
4.3.5 always@(posedge Clock) Blocks
always@(posedge Clock) (“always at the positive edge of the clock”) or always@(negedge Clock) (“al-
ways at the negative edge of the clock”) blocks are used to describe Sequential Logic, or Registers.
Only <= (non-blocking) assignments should be used in an always@(posedge Clock) block. Never use =
(blocking) assignments in always@(posedge Clock) blocks. Only use always@(posedge Clock) blocks when
you want to infer an element(s) that changes its value at the positive or negative edge of the clock.
For example, consider Figure 2, a recreation of Program 10 that uses posedge Clock as its sensitivity
list. Figure 2 is also known as a shift register. The completed always@ block is shown in Program 12.
2This point might be confusing. We said that non-blocking statements happen in parallel. Yet, they are useful for
specifying sequential logic? In digital design, sequential logic doesn’t refer to things happening in parallel or a sequence,
as we have been discussing, but rather to logic that has state.
7
8. Figure 2 A shift register
A
Clock
B C D
Program 12 A shift register, using <= assignments inside of an always@(posedge Clock) block
1 always @(posedge Clock) begin
2 B <= A;
3 C <= B;
4 D <= C;
5 end
4.3.6 always@( * ) Blocks
always@( * ) blocks are used to describe Combinational Logic, or Logic Gates. Only = (blocking)
assignments should be used in an always@( * ) block. Never use <= (non-blocking) assignments in
always@( * ) blocks. Only use always@( * ) block when you want to infer an element(s) that changes
its value as soon as one or more of its inputs change.
Always use ‘*’ (star) for your sensitivity list in always@( * ) blocks. The sensitivity list specifies
which signals should trigger the elements inside the always@ block to be updated. For example, given 3
wires A, B and C, we can create an and gate through Program 13, and shown graphically in Figure 3.
Program 13 An and gate inside of an always@( * ) block
1 always @(A or B) begin
2 C = A & B;
3 end
Figure 3 The and gate produced by Program 13 (this is a normal and gate!)
A
B
C
Program 13 specifies that “when A or B change values, update the value of every element inside the
always@( * ) block. In this case, the only element inside the always@( * ) block is C, which in this case
is assigned the and of A and B. A very common bug is to introduce an incomplete sensitivity list. See
Program 14 for two examples of incomplete sensitivity lists.
In Program 14, the first example produces an and gate that only updates its output C when A changes.
If B changes, but A does not change, C does not change because the always@(A) block isn’t executed.
8
9. Program 14 An and gate with an incomplete sensitivity list (this is incorrect!)
1 always @(A) begin
2 C = A & B;
3 end
1 always @(B) begin
2 C = A & B;
3 end
Likewise, the second example produces an and gate that doesn’t react to a change in A. Incomplete
sensitivity lists are almost NEVER what you want! They introduce very hard-to-find bugs.
As such, we use always@( * ). The ‘*’ is shorthand for always@(A or B) in our examples. In other
words, ‘*’ sets the sensitivity list to any values that can have an impact on a value(s) determined by the
always@( * ) block. ‘*’ provides a bug-free shorthand for creating complete sensitivity lists.
4.3.7 Pitfalls
You might be wondering what happens if you don’t follow the conventions set forth in Sections 4.3.5 and
4.3.6. The following are some easy-to-make mistakes in Verilog that can have a dramatic [and undesired]
effect on a circuit.
1. Consider the shift register from Figure 2. If you place = assignments inside of an always@(posedge
Clock) block to produce the shift register, you instead get the parallel registers shown in Figure 4
and Program 15. You might also get one register, whose output is tied to B, C and D. Both
possible outcomes are equivelent. These circuit make sense, but don’t create shift registers! (As
shift registers are common construct, we assume that you wanted to create a shift register)
Figure 4 Parallel registers
A
Clock
B C D
Program 15 Parallel registers, using = assignments inside of an always@(posedge Clock) block
1 always @(posedge Clock) begin
2 B = A;
3 C = B;
4 D = C;
5 end
2. The opposite example (shown in Program 16), where we place <= assignments inside of always@(
* ) is less pronounced. In this case, just consider what type of circuit you want to create: do you
want all statements to be executed in parallel or in ‘sequence’ (see Section 4.3.3 and 4.3.4)? In the
9
10. always@( * ), the distinction between <= and = is sometimes very subtle, as the point of always@
( * ) is to trigger at indefinite times (unlike the very definite posedge Clock). We recommend =
in conjunction with always@( * ) to establish good convention (as = was originally meant to be
associated with combinational logic).
Program 16 <= assignments inside of always@( * ) blocks
1 always @( * ) begin
2 B <= A;
3 C <= B;
4 D <= C;
5 end
3. Consider the case of incompletely specified sensitivity lists. An incompletely specified sensitivity
list, as discussed in Section 4.3.6, will create an always@ block that doesn’t always set/update its
elements when it should. In truth, synthesis tools will often know what you mean if you provide
an incomplete sensitivity list, and pretend that your sensitivity list was complete. This is not the
case with simulation tools (like ModelSim), however. ModelSim will not correct your sensitivity
list bugs, and your simulations will be plagued with odd errors. Furthermore, the synthesis tools
catching your errors is not guarenteed. An easy way to avoid these potential problems is to use
always@( * ) as opposed to always@(Input1 or Input 2 or ...).
4. Lastly, a very subtle point which perhaps has the potential to cause the most frustration is latch
generation. If you don’t assign every element that can be assigned inside an always@( * ) block
every time that always@( * ) block is executed, a latch (similar to a register but much harder to
work with in FPGAs) will be inferred for that element. This is never what you want and is a
terrible place for bugs. As this is subtle, it is somewhat hard to visualize. Consider Program 17.
Program 17 An always@( * ) block that will generate a latch for C
1 wire Trigger , Pass;
2 reg A, C;
3
4 always @( * ) begin
5 A = 1’b0;
6 if (Trigger) begin
7 A = Pass;
8 C = Pass;
9 end
10 end
In Program 17, A and C are both assigned in at least one place inside the always@ block.
A is always assigned at least once. This is because the first line of the always@ block specifies a
default value for A. This is a perfectly valid assignment. It ensures that A is always assigned with
each execution of the always@ block.
C on the other hand is not always assigned. When Trigger = 1’b1, the if statement ‘executes’
and both A and C get set. If Trigger = 1’b0, however, the if is skipped. A is safe, as it was given a
default value on the first line of the always@ block. C on the other hand, doesn’t get assigned at all
when this happens. As such, a latch is inferred for C. The erroneous circuit depicted in Program 17
is shown in Figure 5.
To fix this problem, we must make sure that C gets set every time the always@ block is ‘executed.’
A simple way to force this is to add another default value, depicted in Program 18 and shown in
Figure 6.
Default values are an easy way to avoid latch generation, however, will sometimes break the logic
in a design. As such, other ways of ensuring that each value always gets set are going to be worth
10
11. Figure 5 The circuit generated by Program 17 (this is an erroneous circuit!)
Pass
Trigger
C
A
1'b0
0
1
Latch
C
Program 18 An always@( * ) block that will not generate latches
1 wire Trigger , Pass;
2 reg A, C;
3
4 always @( * ) begin
5 A = 1’b0;
6 C = 1’b1;
7 if (Trigger) begin
8 A = Pass;
9 C = Pass;
10 end
11 end
Figure 6 The circuit generated by Program 18 (this is correct!)
Pass
Trigger
C
A
1'b0
0
1
1
0
1'b1
11
12. looking into. Typically, they involve proper use of the Verilog else statement, and other flow
constructs.
Know that setting a reg to itself is not an acceptable way to ensure that the reg always
gets set. For example, C = C; enjected into the top of the always@( * ) block in Program 17
will not supress latch generation. In every ‘execution’ of an always@( * ) block, each value that is
assigned in at least one place must be assigned to a non-trivial value during every ‘execution’
of the always@( * ) block.
4.3.8 Post−always@: Specifying our FSM’s Transition Behavior
At this point, the tutorial assumes that you are familiar with the material starting at
Section 4.3.1.
Specifying an FSM’s transition behavior is done in 3 steps. First, we must choose how to store the
information that will tell the FSM what the next state should be on the next rising edge. Second, we
must create a physical means of transitioning from the CurrentState to the next state. Third, we must
implement the conditional-transitioning mechanism that will choose what the next state should be and
under what conditions a transition should be made.
We will store the next state information in a reg of the same width as the CurrentState reg. This
is because we will assign the next state in an always@( * ) block. The details of this process will be
specified shortly. Our CurrentState and next state (which will henceforth be called NextState) are shown
in Program 19.
Program 19 Storing the current state and next state in reg elements
1 reg [2:0] CurrentState;
2 reg [2:0] NextState;
Once we have established CurrentState and NextState, we can create a means of transitioning at
the positive-edge of the clock through an always@(posedge Clock) block, as shown in Program 20. The
always@(posedge Clock) block in Program 20 is identical, and must be present, in all FSMs. It returns
the FSM to the initial state after a reset, and forces CurrentState to take on the value stored in NextState
at the positive-edge of the clock.
Program 20 The always@(posedge Clock) block
1 always@(posedge Clock) begin
2 if (Reset) CurrentState <= STATE_Initial;
3 else CurrentState <= NextState;
4 end
Once we have established a means of transitioning at the positive-edge of the clock, we are ready
to specify the FSM’s conditional-transitioning behavior, or how it chooses what NextState should be.
We will use an always( * ) block in conjunction with a case statement to accomplish this. Unlike the
always@(posedge Clock) block above, which is the same for every FSM, the always@( * ) block is very
dependant on which FSM it is written for. This is because while every FSM will transition from state to
state on the positive-edge of the clock, different FSMs will have different states and different arcs from
state to state. Again, for this tutorial, we will specify an example always@( * ) block using the FSM
shown in Figure 1.
We will now discuss Program 21 line by line.
On line 2, we establish a default value for the NextState reg. The default value reads: “if NextState
does not get assigned anywhere in the case statement (below), set NextState to the CurrentState (which
means that no state change will occur). This avoids a potential Verilog-introduced bug that we will
explain shortly. It also greatly reduces the amount of code that the always@( * ) block will take to
specify (another perk that will be explained shortly).
12
13. Program 21 The always@( * ) block
1 always@( * ) begin
2 NextState = CurrentState;
3 case (CurrentState)
4 STATE_Initial: begin
5 NextState = STATE_1;
6 end
7 STATE_1: begin
8 if (A & B) NextState = STATE_2;
9 end
10 STATE_2: begin
11 if (A) NextState = STATE_3;
12 end
13 STATE_3: begin
14 if (!A & B) NextState = STATE_Initial;
15 else if (A & !B) NextState = STATE_4;
16 end
17 STATE_4: begin
18 end
19 // ---------------------------------------
20 // Place -holder transitions
21 // ---------------------------------------
22 STATE_5_PlaceHolder : begin
23 NextState = STATE_Initial;
24 end
25 STATE_6_PlaceHolder : begin
26 NextState = STATE_Initial;
27 end
28 STATE_7_PlaceHolder : begin
29 NextState = STATE_Initial;
30 end
31 // ---------------------------------------
32 endcase
33 end
Line 3 specifies the beginning of a Verilog case statement. For all FSMs, this case statement is of
the form: case(CurrentState). This means that the branch of the case statement that is chosen based
on the CurrentState. This makes sense because state transition behavior for Moore machines is based
solely on the CurrentState.
Line 4 specifies the case when the CurrentState is STATE_Initial. This statement is self-explanatory:
“when we are in the initial state, always transition to STATE_1 at the next rising edge of the clock.” This
matches Figure 1, as it should.
Line 7 specifies the case when CurrentState is STATE_1. This case is more interesting because of the
implied transition loop back onto STATE_1. So, if A & B is true, transition to STATE_2. However, if A & B
is not true, stay in STATE_1. This last statement isn’t written in Program 21 anywhere, however, is
an implied else statement because of the default we established in Line 2! This is where the Line
2 default value saves space: whenever a state loops back on itself, we need not specify an else
statement. In fact, we need not write anything at all.
Lines 10-12, describing STATE_2 takes advantage of the Line 2 default value in the same way.
Lines 13-16 also take advantage of the default, but are worth mentioning as they show how a state
(STATE_4 can make different transitions to different states through an else if statement.
Lines 22-30 specify the actions to take if the FSM ever enters one of the unused states described
in Section 3. Specifically, the FSM should return to the initial state so that it can restart its normal
operation. If a state machine has unused states, because its state encoding does not take up every value
in its binary specification, for a given number of bits, and it accidentally enters an unused state, it might
get stuck in an infinite loop of garbage transitions.
13
14. As a closing note on state transitions, there is another very good reason to establish the
default value as was done on Line 2. The latch problem discussed in the tutorial on always@ blocks
(starting at Section 4.3.1) is very common in FSMs because FSMs liberally assign values in potentially
large and complex always@ blocks. Using default values can greatly decrease the chance of generating
latches in FSMs. If not for all of the other convenience-related reasons, you should use them for this
reason.
4.4 4: Outputting Values Based on the CurrentState
The final step in specifying a Moore FSM is assigning output values based on CurrentState. Fortunately,
this is simple with assign statements. See Program 22 for the FSM’s (from Figure 1) output specification.
Program 22 The outputs from Figure 1
1 wire Output1 , Output2;
2 reg [2:0] Status;
3
4 assign Output1 = (CurrentState == STATE_1) | (CurrentState == STATE_2);
5 assign Output2 = (CurrentState == STATE_2);
6
7 always@( * ) begin
8 Status = 3’b000;
9 case (CurrentState)
10 STATE_2: begin
11 Status = 3’b010;
12 end
13 STATE_3: begin
14 Status = 3’b011;
15 end
16 endcase
17 end
Alternatively, the output assignment for Status can be combined into the always@( * ) block that
chooses what the next state should be (see Program 21). It is seperated here for clarity.
4.5 A Complete FSM
In this tutorial we hasve discussed why the Moore machine FSM is useful in digital design and how
to create it in the Verilog HDL. We approached the problem in four different steps, namely defining
an encoding (Section 4.1), establishing a way to store state (Section 4.2), creating a means of choosing
between (possibly) more than one ‘NextState’ (Section 4.3), and outputting both 1-bit and multi-bit
output signals (all synchronous with the clock, Section 4.4). The final product, namely the FSM shown
in Figure 3, is reproduced in its entirety in Program 23 (part 1) and Program 24 (part 2).3
Again, you
can alternatively combine the case statement used to assign the Status output into the always@( * )
used to choose between possible NextState values. Seperating the two is personal preference.
Now that we have constructed the final FSM, notice that it is packaged into a Verilog module. Each
FSM in a design should have its own module for composition and organization purposes. An FSM module
will always have Clock and Reset input signals, almost always have other input signals that manipulate
the NextState, and always have Output signals based on the output. Besides these convention-imposed
constraints, an FSM module is a normal Verilog module.
3The final FSM in Verilog is split into two parts due to its size.
14