Routing is an important step in the design of integrated circuits. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. But the connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Today, ASIC design flow is a very mature process in silicon turnkey design. The ASIC design flow and its various steps in VLSI engineering that we describe below are based on best practices and proven methodologies in ASIC chip designs. This blog attempts to explain different steps in the ASIC design flow, starting from ASIC design concept and moving from specifications to benefits.
To ensure successful ASIC design, engineers must follow a proven ASIC design flow which is based on a good understanding of ASIC specifications, requirements, low power design and performance, with a focus on meeting the goal of right time to market. Every stage of ASIC design cycle has EDA tools that can help to implement ASIC design with ease.
In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
A typical SOC can include many hard- and soft-IP macros, memories, analog blocks, and multiple power domains. Because of the increases in gate count, power domains, power modes, and special architectural requirements, most SOCs these days are hierarchical designs. The SOC interacts with the outside world through sensors, antennas, displays, and other elements, which introduce a lot of analog component in the chip. All of these limitations directly result in various challenges in floorplanning.
Floorplanning includes macro/block placement, design partitioning, pin placement, power planning, and power grid design. What make the job more important is that the decisions taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.
Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.
In hierarchical designs, the quality of the floorplan is analyzed after the blocks are integrated at the top level. That can results in unnecessary iterative work, wasted resource hours, and longer cycle times, which could mean missed market opportunities. This underscores the importance of floorplanning.
In this paper, we will discuss some of the good practices, techniques, and complex cases that arise while floorplanning in an SOC.
The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area (to be used for SOG placement) square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
In this course, you
● Identify and apply timing arc information from a library, such as unateness, delays, and slew
● Identify cell delays from a library and calculate output slew degradation
● Use wire-load information to calculate net delays
● Identify the properties of a clock, including period, edges, and slew, and calculate the duty cycle
● Apply setup and hold checks to diagnose design violations
● Identify timing path types to calculate slack values
● Set environmental constraints, clocks constraints, and path exceptions
● Constrain a design using SDC
● Analyze reports to identify timing problems
Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routabil- ity, performance, heat distribution, and to a less extent, power consumption of a design.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
Before 2000 area, delay and performance were the most important parameters, if anyone design circuit the main focus was on how much less area is occupied by the circuit on the chip and what the speed is. Now situation is changed, the performance and speed is a secondary concern. In all nanometer (deep sub-micron) technology power becomes the most important parameter in the design. Almost all portable devices run on battery power. Power consumption is a very big challenge in modern-day VLSI design as technology is going to shrinks Because of
Increasing transistors count on small chip
Higher speed of operations
Greater device leakage currents
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Today, ASIC design flow is a very mature process in silicon turnkey design. The ASIC design flow and its various steps in VLSI engineering that we describe below are based on best practices and proven methodologies in ASIC chip designs. This blog attempts to explain different steps in the ASIC design flow, starting from ASIC design concept and moving from specifications to benefits.
To ensure successful ASIC design, engineers must follow a proven ASIC design flow which is based on a good understanding of ASIC specifications, requirements, low power design and performance, with a focus on meeting the goal of right time to market. Every stage of ASIC design cycle has EDA tools that can help to implement ASIC design with ease.
In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
A typical SOC can include many hard- and soft-IP macros, memories, analog blocks, and multiple power domains. Because of the increases in gate count, power domains, power modes, and special architectural requirements, most SOCs these days are hierarchical designs. The SOC interacts with the outside world through sensors, antennas, displays, and other elements, which introduce a lot of analog component in the chip. All of these limitations directly result in various challenges in floorplanning.
Floorplanning includes macro/block placement, design partitioning, pin placement, power planning, and power grid design. What make the job more important is that the decisions taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.
Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.
In hierarchical designs, the quality of the floorplan is analyzed after the blocks are integrated at the top level. That can results in unnecessary iterative work, wasted resource hours, and longer cycle times, which could mean missed market opportunities. This underscores the importance of floorplanning.
In this paper, we will discuss some of the good practices, techniques, and complex cases that arise while floorplanning in an SOC.
The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area (to be used for SOG placement) square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
In this course, you
● Identify and apply timing arc information from a library, such as unateness, delays, and slew
● Identify cell delays from a library and calculate output slew degradation
● Use wire-load information to calculate net delays
● Identify the properties of a clock, including period, edges, and slew, and calculate the duty cycle
● Apply setup and hold checks to diagnose design violations
● Identify timing path types to calculate slack values
● Set environmental constraints, clocks constraints, and path exceptions
● Constrain a design using SDC
● Analyze reports to identify timing problems
Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routabil- ity, performance, heat distribution, and to a less extent, power consumption of a design.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
Before 2000 area, delay and performance were the most important parameters, if anyone design circuit the main focus was on how much less area is occupied by the circuit on the chip and what the speed is. Now situation is changed, the performance and speed is a secondary concern. In all nanometer (deep sub-micron) technology power becomes the most important parameter in the design. Almost all portable devices run on battery power. Power consumption is a very big challenge in modern-day VLSI design as technology is going to shrinks Because of
Increasing transistors count on small chip
Higher speed of operations
Greater device leakage currents
https://www.udemy.com/vlsi-academy
Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure.
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input. Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by inserting buffers/inverters along the clock routes of an ASIC design. As a result, CTS is used to balance the skew and reduce insertion latency. Before Clock Tree Synthesis, all clock pins were driven by a single clock source. Clock tree synthesis includes both clock tree construction and clock tree balance. Clock tree inverters may be used to create a clock tree that maintains the correct transition (duty cycle), and clock tree buffers (CTB) can balance the clock tree to fulfil the skew and latency requirements. To fulfil the space and power limits, fewer clock tree inverters and buffers should be employed.
Physical design means --->> netlist (.v ) converted into GDSII form(layout form)
logical connectivity of cells converted into physical connectivity.
During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer, are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers.
Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.
Performance: long routes have significantly longer signal delays.
Area: placing connected modules far apart results in larger and slower chips.
Reliability: A large number of vias can significantly reduce the reliability of the circuit.
Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate).
Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard-cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
Play
Next
Unmute
Current TimeÂ
0:00
/
DurationÂ
18:10
Â
Fullscreen
Backward Skip 10s
Play Video
Forward Skip 10s
Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)VLSI SYSTEM Design
Learning becomes Fun..
When tedious & difficult topics like Chip Design are explained in simple n creative videos....https://www.udemy.com/vlsi-academy
This is the presentation that was shared by Nilesh Ranpura and Vineeth Mathramkote at CDNLIVE 2015. The session briefs about the implementation challenges and covers the solution approach and how to achieve results
As we push through lower technology nodes in the IC and chip design, the wire width goes thinner along with transistor size. This makes the wire resistance more dominant on 16nm and below technology nodes. This increasing resistance and the decreasing width of metal wires introduce many Electromigration and IR drop issues. These two issues play major roles in reducing the lifespan of an electronic device and are the causes of functionality failure in any electronic devices with lower technology nodes.
In this article, we will discuss the problems of electromigration and IR drop, and techniques to prevent the occurrence of these issues in electronic devices.
Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses.
The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. this drop is called as IR drop.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
Equivalence checking is a portion of a larger discipline called formal verification. This technology uses mathematical modeling techniques to prove that two representations of design exhibit the same behavior. This approach should not be confused with functional verification, which uses exhaustive simulation to verify the correctness of a design.
Once a verified version of a design has been identified, equivalence checking can be used to determine if an alternate representation of the design behaves the same as the verified version. This technique does not use input vectors so it is more efficient.
Equivalence checking is useful to verify that a design’s function has not changed after an operation like synthesis, or after a functional ECO has been applied.
Placement is the process of determining the locations of circuit devices on a die
surface. It is an important stage in the VLSI design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a
design. Traditionally, it is applied after the logic synthesis stage and before the
routing stage. Since the advent of deep submicron process technology around
the mid-1990s, interconnect delay, which is largely determined by placement,
has become the dominating component of circuit delay. As a result, placement
information is essential, even in early design stages, to achieve better circuit performance. In recent years, placement techniques have been integrated into the
logic synthesis stage to perform physical synthesis and into the architecture
design stage to perform physical-aware architecture design
https://www.udemy.com/vlsi-academy
Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure.
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input. Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by inserting buffers/inverters along the clock routes of an ASIC design. As a result, CTS is used to balance the skew and reduce insertion latency. Before Clock Tree Synthesis, all clock pins were driven by a single clock source. Clock tree synthesis includes both clock tree construction and clock tree balance. Clock tree inverters may be used to create a clock tree that maintains the correct transition (duty cycle), and clock tree buffers (CTB) can balance the clock tree to fulfil the skew and latency requirements. To fulfil the space and power limits, fewer clock tree inverters and buffers should be employed.
Physical design means --->> netlist (.v ) converted into GDSII form(layout form)
logical connectivity of cells converted into physical connectivity.
During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer, are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers.
Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.
Performance: long routes have significantly longer signal delays.
Area: placing connected modules far apart results in larger and slower chips.
Reliability: A large number of vias can significantly reduce the reliability of the circuit.
Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate).
Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard-cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
Play
Next
Unmute
Current TimeÂ
0:00
/
DurationÂ
18:10
Â
Fullscreen
Backward Skip 10s
Play Video
Forward Skip 10s
Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)VLSI SYSTEM Design
Learning becomes Fun..
When tedious & difficult topics like Chip Design are explained in simple n creative videos....https://www.udemy.com/vlsi-academy
This is the presentation that was shared by Nilesh Ranpura and Vineeth Mathramkote at CDNLIVE 2015. The session briefs about the implementation challenges and covers the solution approach and how to achieve results
As we push through lower technology nodes in the IC and chip design, the wire width goes thinner along with transistor size. This makes the wire resistance more dominant on 16nm and below technology nodes. This increasing resistance and the decreasing width of metal wires introduce many Electromigration and IR drop issues. These two issues play major roles in reducing the lifespan of an electronic device and are the causes of functionality failure in any electronic devices with lower technology nodes.
In this article, we will discuss the problems of electromigration and IR drop, and techniques to prevent the occurrence of these issues in electronic devices.
Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses.
The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. this drop is called as IR drop.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
Equivalence checking is a portion of a larger discipline called formal verification. This technology uses mathematical modeling techniques to prove that two representations of design exhibit the same behavior. This approach should not be confused with functional verification, which uses exhaustive simulation to verify the correctness of a design.
Once a verified version of a design has been identified, equivalence checking can be used to determine if an alternate representation of the design behaves the same as the verified version. This technique does not use input vectors so it is more efficient.
Equivalence checking is useful to verify that a design’s function has not changed after an operation like synthesis, or after a functional ECO has been applied.
Placement is the process of determining the locations of circuit devices on a die
surface. It is an important stage in the VLSI design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a
design. Traditionally, it is applied after the logic synthesis stage and before the
routing stage. Since the advent of deep submicron process technology around
the mid-1990s, interconnect delay, which is largely determined by placement,
has become the dominating component of circuit delay. As a result, placement
information is essential, even in early design stages, to achieve better circuit performance. In recent years, placement techniques have been integrated into the
logic synthesis stage to perform physical synthesis and into the architecture
design stage to perform physical-aware architecture design
Sign off in VLSI is used to represent the completion of the design process. It is the final stage of the design cycle, in which all aspects of the chip are verified to make sure it meets the desired specifications. Sign off includes the physical verification of the design, the timing verification of the design, the power verification of the design, and the electrical verification of the design. Once all these verifications are completed and the chip is deemed to be functioning as expected, the design can be signed off
- Defined the specifications and designed an architecture of the MSDAP chip that performs convolution of two signals in least possible area & power.
- Implemented a RTL model of the MSDAP chip which consists of a Controller, ALU, Memories and Serial communication Unit.
- Synthesized the design in Synopsys Design Vision and functionality was verified using the Modelsim
- Final physical design was generated using the IC Compiler.
KEMET Webinar - Challenging Designs Drive Diverse Form FactorsMarkus Trautz
Ceramic capacitors are a key component in just about any electronic system used today and perform critical functions such as filtering, decoupling, bypass, voltage suppression, just to name a few. The increase in automotive sensors, harsh environment applications, and unique electrical and mechanical requirements has driven ceramic capacitors to take on more unique form factors. This webinar will explore how form factor plays a vital role in electrical and mechanical performance and what to consider when selecting the various options.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1Javed G S, PhD
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
- OTA
- Buffer
- Unity Feedback OTA
- Layout design strategies – 2stage opamp + CMFB
5. Sense and Return mechanisms in Feedback circuits
- Current and Voltage circuits
6. Sub-Threshold Conduction
- Low voltage Operation
7. ADC Design and Simulation
-Near Nyquist performance of Opamp for ADC Circuits
-Spectral Analysis and No. of FFT Points for simulation
-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
When it comes to designing any type of radio frequency product, the footprint of the overall design may need to fit into a predefined package size. This often times causes the overall RF filter to be designed around these constraints.
In this webinar we will review some of the electrical performance and mechanical size issues when designing an RF filter for your application. We will also discuss what techniques should be used and how they affect the overall performance of the product.
For more information on our custom RF products solutions visit http://www.epectec.com/rf-products/
Ultra Low Power Design and High Speed Design of Domino Logic CircuitIJERA Editor
The tremendous success of the low-power designs of VLSI circuits over the past 50 years has significant change
in our life style. Integrated circuits are everywhere from computers to automobiles, from cell phones to home
appliances. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or
NMOS transistors. Dynamic logic circuits are used for their high performance, but their high noise and
extensive leakage has caused some problems for these circuits. Dynamic CMOS circuits are inherently less
resistant to noise than static CMOS circuits. In this paper we proposed different domino logic styles which
increases performance compared to existing domino logic styles. According to the simulations in cadence
virtuoso 65nm CMOS process, the proposed circuit shows the improvement of up thirty percent compared
existing domino logics.
This chapter contains information for memory compilers available in STDL80 cell library. These are
complete compilers that consist of various generators to satisfy the requirements of the circuit at hand. Each
of the final building block, the physical layout, will be implemented as a stand-alone, densely packed,
pitch-matched array. Using this complex layout generator and adopting state-of-the-art logic and circuit
design technique, these memory cells can realize extreme density and performance. In each layout
generator, we added an option which makes the aspect ratio of the physical layout selectable so that the
ASIC designers can choose the aspect ratio according to the convenience of the chip level layout.
Routing in VLSI is making physical connections between signal pins using metal layers. Following Clock Tree Synthesis (CTS) and optimization, the routing step determines the exact pathways for interconnecting standard cells, macros, and I/O pins.
Global Routing
first partitions the routing region into tiles/rectangles called global routing cells (gcells) and decides tile-to-tile paths for all nets while attempting to optimize some given objective function (e.g., total wire length and circuit timing), but doesn’t make actual connections or assign nets to specific paths within the routing regions.
By default, the width of a gcells is same as the height of a standard cell and is aligned with the standard cell rows.
Every gcell having the a number of horizontal routing resources and vertical routing resources.
Global routing assigns nets (logical connectivity not metal connectivity) to specific metal layers and global routing cells.
Track Assignment
Track assignment is a stage wherein the routing tracks are assigned for each global routes. The tasks that are performed during this stage are as follows
Assigning tracks in horizontal and vertical partitions.
Rerouting all overlapped wires.
Track Assignment replaces all global routes with actual metal layers.
Although all nets are routed (not very carefully), there will be many DRC, SI and timing related violations, especially in regions where the routing connects the pins. These violations are fixed in the succeeding stages.
Detail Routing
The detailed router uses the routing plan laid by the router during the Global Routing and Track Assignment and lays actually metal to logically connect pins with nets and other pins in the design.
The violations that were created during the Track Assignment stage are fixed through multiple iterations in this stage.
The main goal of detailed routing is to complete all the required interconnect without leaving shorts or spacing violations.
The detailed routing starts with the router dividing the block into specific areas called switch boxes or Sbox, which are generally expressed in terms of gcells.
Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.
Clock tree network enables in making design clean from a timing perspective. However, it is responsible for more than one third of the total power consumption of the chip. The impact of variations in the clock path is more than 2 times the other paths in the design. These variations in-turn affects the timing paths. Let us take an example; Due to the variation, if the clock path to the launching register is slowed down by 100ps and the clock path to the capturing register is fastened by 100ps then it impacts the setup constraint by adding 200ps more to it, this in-turn affects the timing path by making it more critical. Here we can see the importance of building a balanced clock tree. We will discuss on the timing improvements and methods to reduce the variations in the clock tree. The steps followed in building a customized clock tree and the steps followed to bring down the variations in the clock tree has been depicted in the following sections.
In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally, it is a NP hard problem. So many researchers from time to time have suggested various heuristics and metaheuristic approaches for solving the VLSI Floorplan Problem. The Floorplan representation is another important aspect of the Floorplanning Stage. Representations have a great impact on the complexity of the Floorplan design. In this paper, we survey the VLSI Floorplanning problem which includes studying and comparing the different optimization algorithms and the representations involved in the VLSI Floorplanning problem. Additionally we suggest some of the new approaches for solving the floorplanning problem which has not yet been employed in this regard.
What is the Difference Between the target_library and link_library Variables?Ahmed Abdelazeem
Design Compiler already has the set target_library my_lib.db command.
Why is it necessary to also use the set link_library "* my_lib.db"
command? Can you explain the difference?
Makefiles are used to help decide which parts of a large program need to be recompiled. In the vast majority of cases, C or C++ files are compiled. Other languages typically have their own tools that serve a similar purpose as Make. Make can also be used beyond compilation too, when you need a series of instructions to run depending on what files have changed. This tutorial will focus on the C/C++ compilation use case.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
In VLSI design, Design for Testability (DFT) is an approach that aims to make digital circuits easier to test during the manufacturing and debugging process. DFT in VLSI design involves incorporating additional circuitry and design features such as scan chains, built-in self-test (BIST) circuits, and boundary scan cells into the chip design to facilitate testing. Design for testability in VLSI design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects. It also reduces the overall test time and thereby the cost of testing, and debugging. By incorporating DFT techniques into the chip design, it becomes easier to test the structural correctness of the chip, leading to higher-quality products and faster time-to-market.
Synthesis in VLSI is the process of converting your code (program) into a circuit. In terms of logic gates, synthesis is the process of translating an abstract design into a properly implemented chip. Hardware Description Languages (HDLs) are specific programming languages that are used to explain the hardware of a circuit, and the computer subsequently builds the circuit depending on the programme you provided. A “Gate Level Netlist” is what you get once you finish synthesising. This is how your circuit will appear. It demonstrates how everything is interconnected. You can alter it if you like; the computer just synthesizes this netlist based on its best judgement. The synthesizer generates better netlists as the abilities improve and they become more proficient at creating HDL programmes.
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.
1. Intro Routing Crosstalk ECO DFM
Routing
How to Route your own chip
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, March 2022
Ahmed Abdelazeem ASIC Physical Design
2. Intro Routing Crosstalk ECO DFM
Table of Contents
1 Introduction
2 Routing Operations
3 Crosstalk
4 Engineering change order (ECO)
5 Chip Finishing and DFM
Ahmed Abdelazeem ASIC Physical Design
3. Intro Routing Crosstalk ECO DFM Routing Route
Table of Contents
1 Introduction
2 Routing Operations
3 Crosstalk
4 Engineering change order (ECO)
5 Chip Finishing and DFM
Ahmed Abdelazeem ASIC Physical Design
4. Intro Routing Crosstalk ECO DFM Routing Route
Design Status, Start of Routing Phase
Placement - completed
CTS – completed
Power and ground nets – prerouted
Estimated congestion - acceptable
Estimated timing - acceptable ( 0ns slack)
Estimated max cap/transition – no violations
Ahmed Abdelazeem ASIC Physical Design
5. Intro Routing Crosstalk ECO DFM Routing Route
Routing Fundamentals: Goal
Routing creates physical connections to all clock and signal
pins through metal interconnects
Routed paths must meet setup and hold timing, max
cap/trans, and clock skew requirements
Metal traces must meet physical DRC requirements
Ahmed Abdelazeem ASIC Physical Design
6. Intro Routing Crosstalk ECO DFM Routing Route
Grid-Based Routing System
Metal traces (routes) are built
along and centered upon
routing tracks based on a grid.
Each metal layer has its own
grid and preferred routing
direction:
M1: Horizontal
M2: Vertical, etc. . .
The tracks and preferred
routing directions are defined in
a ”unitTile” cell in the standard
cell library
Ahmed Abdelazeem ASIC Physical Design
7. Intro Routing Crosstalk ECO DFM Routing Route
Peculiarities of Grid-Based Routing System in IC Compiler
The ”unitTile” shown as a screen shot is used to define and
store routing tracks and preferred directions information.
unitTile cell is part of the standard cell library.
The unitTile is similar to a site. It defines several things:
The minimum height and width a cell can occupy
The pitches in the preferred direction
Power and ground rail locations for standard cells
The height of the unitTile is based on the metal 1 pitch
(vertical) and must be a multiple of it.
The width is based on the metal 2 pitch (horizontal) and
must be a multiple of it.
The metal 2 routing track defined in it must either be along
the left side boundary or centered in the unitTile.
Ahmed Abdelazeem ASIC Physical Design
8. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Table of Contents
1 Introduction
2 Routing Operations
3 Crosstalk
4 Engineering change order (ECO)
5 Chip Finishing and DFM
Ahmed Abdelazeem ASIC Physical Design
9. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Routing Operations
PnR Compiler performs:
1 Global Routing
2 Track Assignment
3 Detail Routing
4 Search and Repair
After global routing, track assignment and detail routing
all clock/signal nets will be completely routed and
should meet all timing, and most all DRC, requirements
Any remaining DRC violations can be fixed by Search &
Repair
Ahmed Abdelazeem ASIC Physical Design
10. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Route Operations: Global Route
Global Route (GR) is the first step in routing
GR gives more accurate parasitic and delay estimates
compared to VR.
The Global Route that is performed during routing will
be used by the subsequent Track Assign operation
Determining overall path of all routes
Seeking to reduce delay, channel widths
Ahmed Abdelazeem ASIC Physical Design
11. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Route Operations: Global Route
Ahmed Abdelazeem ASIC Physical Design
12. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Route Operations: Global Route Summary
Answer: False!
GR does not lay
down any metal
traces.
Ahmed Abdelazeem ASIC Physical Design
13. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Route Operations: Track Assignment
Ahmed Abdelazeem ASIC Physical Design
14. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Route Operations: Detail Routing
Detail route attempts to clear DRC violations using a
fixed size Sbox
Due to the fixed Sbox size, detail route may not be able
to clear all DRC violations
Ahmed Abdelazeem ASIC Physical Design
15. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Route Operations: Search&Repair
Search&Repair fixes remaining DRC violations through
multiple loops using progressively larger SBox sizes
Note: Even if the design is DRC clean after S&R, you
must still run a sign-off DRC checker (Caliber).
Routing DRC rules are a subset of the complete technology
DRC rules
IC Compiler works on the FRAM view, not the detailed
transistor-level (CEL) view
Ahmed Abdelazeem ASIC Physical Design
16. Intro Routing Crosstalk ECO DFM Operations Global Track Detail S&R
Routing over Macros
Ahmed Abdelazeem ASIC Physical Design
17. Intro Routing Crosstalk ECO DFM Crosstalk
Table of Contents
1 Introduction
2 Routing Operations
3 Crosstalk
4 Engineering change order (ECO)
5 Chip Finishing and DFM
Ahmed Abdelazeem ASIC Physical Design
18. Intro Routing Crosstalk ECO DFM Crosstalk
What is Crosstalk?
Ahmed Abdelazeem ASIC Physical Design
21. Intro Routing Crosstalk ECO DFM ECO Functional
Table of Contents
1 Introduction
2 Routing Operations
3 Crosstalk
4 Engineering change order (ECO)
5 Chip Finishing and DFM
Ahmed Abdelazeem ASIC Physical Design
22. Intro Routing Crosstalk ECO DFM ECO Functional
Engineering change order
Ahmed Abdelazeem ASIC Physical Design
23. Intro Routing Crosstalk ECO DFM ECO Functional
Two Types of ECO Flows
Ahmed Abdelazeem ASIC Physical Design
24. Intro Routing Crosstalk ECO DFM ECO Functional
Functional ECO Flows
Non-Freeze silicon ECO
Pre-tapeout, no restriction on placement or routing
Minimal disturbances to the existing layout
ECO cells are placed close to their optimal locations
Freeze silicon ECO
Post-tapeout, metal masks change only using previously
inserted spare cells
Cell placement remains unchanged
ECO cells are mapped to spare cells that are closest to the
optimal location
Deleted cells become spare cells
Ahmed Abdelazeem ASIC Physical Design
25. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Table of Contents
1 Introduction
2 Routing Operations
3 Crosstalk
4 Engineering change order (ECO)
5 Chip Finishing and DFM
Ahmed Abdelazeem ASIC Physical Design
26. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Chip Finishing Flow
PnR Compiler can address several issues to increase
manufacturing yield:
Gate Oxide integrity → antenna fixing
Via resistance and reliability → extra contacts
Random Particle defect → Wire spreading
Metal erosion → metal slotting
Metal liftoff → metal slotting
Metal Over-Etching → metal fill
Ahmed Abdelazeem ASIC Physical Design
27. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Manufacturability Issues
In deep submicron VLSI, some manufacturing steps, like
photo-resist exposure, development and etch and Chemical
Mechanical Polishing (CMP) have detrimental effects on
interconnect structures. These effects can vary based on local
characteristics of the layout.
To make these effects predictable, the layouts must be made
“uniform” with respect to certain density standards across
very small localized areas of the die. In the past, foundries
performed the post processing needed to provide this
uniformity. The techniques they used were filling (selective
insertion of shapes) or slotting (selective reduction of shapes).
In today’s processes, the design tools doing RC extraction,
delay calculation, IR drop analysis, timing/noise/crosstalk
analysis must be aware of these slotting/filling activities or
suffer significant inaccuracy.
Ahmed Abdelazeem ASIC Physical Design
28. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Manufacturability Issues
PnR Compiler attempts to move all these into the design
stage and out of the Fab post processing regime.
To minimize the impact of the manufacturing process on
device yields, foundries impose various density rules to make
the layouts more uniform. For instance, the foundry may
impose a density rule on an interconnect layer such that in
any 10 um x 10 um window, there must be at least 35 um2 of
metal features, but no greater than 70 um2 of metal.
Spare areas must be filled, but wide metal stripes must be
slotted to meet the density rules.
Ahmed Abdelazeem ASIC Physical Design
29. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Problem: Gate Oxide Integrity
Metal wires (antennae) placed in an EM field generate
voltage gradients
During the metal etch stage, strong EM fields are used
to stimulate the plasma etchant
Resultant voltage gradients at MOSFET gates can
damage the thin oxide
Ahmed Abdelazeem ASIC Physical Design
30. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Antenna Rules
As length of wire increases during processing, the
voltage stressing the gate oxide increases
Antenna rules define acceptable length of wires
Ahmed Abdelazeem ASIC Physical Design
31. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Fixing Antenna Problems
Ahmed Abdelazeem ASIC Physical Design
32. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Voids in Vias During Manufacturing
Voids in vias is a serious issue in manufacturing
Two solutions are available:
Reduce via count: via optimization techniques are employed in
routing stage
Add backup vias: known as redundant vias
Ahmed Abdelazeem ASIC Physical Design
33. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Via Resistance and Reliability
Replacing one via with multiple vias can improve yield &
timing (series R reduction)
Inserts multiple vias without rerouting
Ahmed Abdelazeem ASIC Physical Design
34. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Wire Spreading: Random Particle Defects
Random missing or extra material causes opens or shorts
during the fabrication process
Wires at minimum spacing are most susceptible to shorts
Minimum-width wires are most susceptible to opens
Ahmed Abdelazeem ASIC Physical Design
35. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Filler Cell Insertion
Metal fill insertion helps
To fill layers of choice including poly
To insert floating vias
To do area based metal fill
To specify required width (timing driven metal fill doesn’t fill
wire tracks around critical nets)
For better yield, density of the chip needs to be uniform
Some placement sites remain empty on some rows
Ahmed Abdelazeem ASIC Physical Design
36. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Problem: Metal Over-Etching
A narrow metal wire separated from other metal receives
a higher density of etchant than closely spaced wires
The narrow metal can get over-etched
Minimum metal density rules are used to control this
Too much etchant in contact with too little metal →
over-etched metal
Ahmed Abdelazeem ASIC Physical Design
37. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Solution: Metal Fill
Fills empty tracks with metal shapes to meet the
minimum metal density rules
Uses up most of the remaining routing resource:
No further routing or antenna fixes can be done
Metal filling is done to improve process planarization,
which is important for processes with a large number of
metal layers.
Ahmed Abdelazeem ASIC Physical Design
38. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Problem: Metal Erosion
The wafer is made flat (planarized) by a process called
Chemical Mechanical Polishing (CMP)
Metals are mechanically softer than dielectrics:
CMP leaves metal tops with a concave shape - dishing
The wider the metal the more pronounced the dishing
Wide traces with little intervening dielectric and can become
quite thin – dishing this severe is called erosion
Process rules specify maximum metal density per layer
to minimize erosion
Ahmed Abdelazeem ASIC Physical Design
39. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Problem: Metal Liftoff
Conductors and Dielectrics have different coefficients of
thermal expansion:
Stress builds up with temperature cycling
Metals can delaminate (lift off) with time
Wide metal traces are more vulnerable than narrow ones
Maximum metal density rules also address this issue
Ahmed Abdelazeem ASIC Physical Design
40. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Solution: Metal Slotting
Slotting wide wires reduces the metal density
Slots minimize stress buildup, reducing liftoff tendency
Primarily used on Power and Ground traces:
Can apply to any other net if wide enough
Slotting parameters can be set layer by layer
Ahmed Abdelazeem ASIC Physical Design
41. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
Final Validation
Ahmed Abdelazeem ASIC Physical Design
42. Intro Routing Crosstalk ECO DFM Flow Antenna Via Wire Filler Metal Slotting Validation
....
ÕækQË@ áÔgQË@ éÊË@ Õæ„.
C
JÊ
¯ B
@ Õ
Ϊ
Ë@ áÓ Õ
æJKð@ AÓð
Ahmed Abdelazeem ASIC Physical Design