The document describes a study and performance analysis of the Modified Gate Diffusion Input (MGDI) technique. It provides details on MGDI logic, including how it overcomes limitations of the Gate Diffusion Input (GDI) technique. Various logic gates and circuits like full adders, flip-flops, and finite state machines are designed using MGDI. Simulation results show that MGDI outperforms GDI and traditional CMOS logic in terms of transistor count, power dissipation, and delay. While self-resetting logic has higher transistor count and power, it provides an alternative to dynamic logic by removing the need for a global clock.

1. STUDY AND PERFORMANCE ANALYSIS OF MODIFIED
GATE DIFFUSION INPUT (MGDI) TECHNIQUE
M.TECH PROJECT PRESENTATION
BY
SHUBHAM JHA
ROLL NUMBER: MT/16/ECE/11
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
NORTH EASTERN INSTITUTE OF SCIENCE AND TECHNOLOGY, NIRJULI, ARUNACHAL
PRADESH
UNDER THE SUPERVISION
OF
MR. ANIL KUMAR GAUTAM

2. CONTENTS
Introduction
Modified Gate Diffusion Input (MGDI)
Literature Review
Design of Full Adder
Design of Flip- Flop
Design of Finite State Machine (FSM)
Conclusion
References

3. INTRODUCTION
The rapid growth in the use of portable system has triggered the research effort in low power
microelectronic. This is due to the fact that the battery technology is not increasing with the same
pace as the microelectronics technology. Only a limited power is available for the mobile system.
Therefore low power design has become a major design consideration. Modified Gate Diffusion
Input (MGDI) is a low power design which is a modification of Gate Diffusion Input (GDI).GDI is
the lowest design technique, which is suitable for designing fast, low power circuit using reduced
number of transistor. The main drawback associated with GDI is that the bulk terminal is not
properly biased thereby the circuit exhibits threshold drop and it can be fabricated only in Twin well
CMOS or Silicon on Insulator (SOI) process. So to overcome this MGDI is introduced.
1

4. GATE DIFFUSION INPUT (GDI)
• The GDI basic cell seems like an inverter build in SOI or dual
well CMOS process.
• The GDI cell contains three input
• G(common gate input of NMOS and PMOS)
• P(input to the source/drain of PMOS)
• N(input to the source/drain of NMOS)
• Bulk of both NMOS and PMOS are connected to N and P
respectively.
• GDI cell has (n+2) inputs when compared to CMOS
2

5. BASIC GATES USING GDI
N P G OUT FUNCTION
0 B A 𝐴 B F1
B 1 A 𝐴 + B F2
1 B A A+B OR
B 0 A AB AND
C B A AB+A
C
MUX
0 A A 𝐴 NOT
3

6. MODIFIED GATE DIFFUSION INPUT (MGDI)
MGDI is a modified version of GDI
4

7. MODIFIED GDI
• In the Mod-GDI cell
 The bulk node of PMOS transistor is connected to the high
constant voltage referred to as supply voltage or Vdd and
 The bulk of NMOS transistor is connected to low constant
voltage referred to as GND.
• Mod-GDI cell can be implemented with all current CMOS process
of fabrication.
• This arrangement of Mod-GDI cell provides considerable reduction
of both sub-threshold and gate leakage compared to static CMOS
gate. 5

8. BASIC GATES USING MGDI
N P G OUT FUNCTIO
N
0 𝐵 𝐴 𝐴B F1
B 1 𝐴 𝐴 + 𝐵 𝐹2
A 𝐵 𝐴 𝐴 + 𝐵 OR
B 𝐴 𝐴 𝐴𝐵 𝐴𝑁𝐷
C 𝐵 𝐴 𝐴𝐵 + 𝐴𝐶 𝑀𝑈𝑋
0 1 𝐴 𝐴 NOT
6

9. ADVANTAGES OF MGDI
 MGDI is appropriate for design of high-speed, low power circuits, using reduced number
of transistors.
 Improves swing degradation and static power characteristics.
 Allow easy top-down design by using a small cell library.
 Allows realization of a broad variety of multifaceted logic functions by means of only two
transistors.
 MGDI gates lower the transistor count and in turn the silicon area required is small when
compared to standard static CMOS and domino CMOS based approaches.
 Leakage power and switching power of MGDI gates is lower than the traditional logic
styles.
7

10. Literature review
A new low power design technique, GDI has been
introduced. This technique allows implementation of a
wide range of complex logic function using only two
transistor which makes this suitable for design of fast low
power circuit, using a reduced number of transistor while
improving static power characteristics and allowing
simple top down design by using small cell library.[1]
Arkaidy Morgenshtein et
al. (2002)
Massimo Alioto et al.
(2003)
Another technique for high speed low power circuit was implemented which was
based on mixing different logic styles to implement arithmetic circuit. Here fast full
adders chains without driving capability interrupted by full adders with driving
capability are considered and optimized for minimum delay.[2]
8

11. D-FF was implemented by using GDI technique [1]. Performance comparison with
other D-FF design was done with respect to gate area, delay and power dissipation and
the proposed structures showed upto 45% reduction in PDP and the reduction in gate
area.[3]
Arkaidy Morgenshtein et
al. (2004)
Massimo Alioto et al.
(2007)
Adder was designed using mixed topology [2] and compared it with single topology
for technology spanning five technology nodes( from 90 nm to 0.35 um). Results show
that the mixed topology is very efficient over single topology and its advantage
increases as down-scaling the technology.[4]
Based on mixed topology full adder based on mixed GDI has been designed. As
compared to the previous [1] here GDI full adders are followed by inverters in the
long full adder chains to alleviate the problem of signal degradation during
propagation through long chain.[5]
Adarsh Kumar Agarwal
et al. (2009)
9

12. 4-Bit full adder was designed using SRL, here SRL is compared with dynamic logic at
gate level and performance comparison.Dynamic logic lacks in the application of
clock distribution grid and routing to dynamic gates that presents a problem to CAD
tools and introduces issues of delay and skew into the circuit design process, this is
solved by SRL. The only deficit is that it occupies more Si area.[6]
R. Uma (2011)
R. Uma et al. (2012)
Modified-GDI is introduced , earlier GDI can be fabricated only in twin well CMOS
process or SOI process to realize a chip, this increases the complexity as well as the
cost of fabrication. But MGDI can be fabricated in any standard CMOS fabrication
process.[7]
Here the nMOS block of conventional SRL[6] is replaced by the Mod-GDI block.
This structure reduces the transistor count and dynamic power dissipation. In
conventional CMOS the upper pMOS and the lower nMOS stack is connected to VDD
and GND , which provides a low impedance path between VDD and gnd. This situation
is eliminated in this logic. So by combining SRL and MGDI the circuit produces high
speed and low power output.[8]
R. Uma et al. (2012)
10

13. Three low power full adders are designed with full swing AND, OR and XOR gates
to alleviate threshold voltage problem which is commonly encountered in Gate Diffusion
Input (GDI) logic. The enhanced driving capability also facilitates lower voltage and
faster operation which leads to less energy consumption. The performance of the
proposed designs is compared with the other full adder designs, namely CMOS, CPL,
hybrid and GDI through SPICE simulations using 45 nm technology models.[10]
Mrs. K.Kalaiselvi et al.
(2014)
Mohan Shoba et al.
(2016)
In the proposed paper the adder circuits is designed in Self resetting logic and the
number of transistors in the modified design is reduced. The goal is to obtain a family
of adders that could simplify the implementation of fast processing circuit which
overcomes the restriction due to the pulses being elongated and shortened as signal
traverse the logic stages. The circuits are designed in 120nm processing CMOS
processing technology. [9]
R. Uma et al.
(2017)
Design of low power adder is done using SRLGDI.In the proposed design structure , the
pull down tree is implemented with (GDI) with level restoration which apparently
eliminates the conductance overlap between nMOS and pMOS devices which was
encountered in the case of conventional SRL [6], thereby reducing the short circuit
power dissipation and providing High Output Voltage.[11]
11

14. FULLADDER USING MGDI
 A combinational circuit which adds two bit and a
carry and outputs sum and carry is known as a full
adder.
 The full adder adds the bit A and B and the carry
from the previous column called carry-in Cin and
outputs the sum bit S and carry-out called the Cout.
 The variable S is 1 when any one of the input is 1 or
when all the input is 1 and Cout is 1 when two of the
input is 1 or when all the input is 1.
12

15. TRUTH TABLE OF FULLADDER
Input Output
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
13

16. FULLADDER USING MGDI SUM= A ⨁ B ⨁ C
CARRY= (A ⨁ B )C +AB
14

17. FULLADDER USING GDI SUM= (A ⨁ B) 𝑪 +(A ⨁ B) C
CARRY= (A ⨁ B)B + (A ⨁ B )C
15

18. FULLADDER USING SELF- RESETTING
LOGIC
• Circuits that can automatically precharge themselves(i.e. reset
themselves ) after a prescribed delays, these circuit are called
postcharge or self resetting logic.
• Widely used in dynamic logic circuit
• They find application where a small percentage of gate switch in a
cycle , such as memory decoder circuits.
• It is a form of logic in which the signal being propagated
is buffered and used as precharge or reset signal.
• No global clock is required.
16

19. SELF RESETTING LOGIC WITH GATE DIFFUSION
INPUT
 the pull down tree is implemented with GDI with level restoration.
 in this logic no global clock is required and all the operation is controlled through the inverter chain between
PMOS and output.
 the output stage of SRLGDI has been incorporated with an inverter to produce both true and complementary
output function. 17

20. FULLADDER USING SRLGDI
SUM= (A ⨁ B) 𝑪 +(A ⨁ B) C
CARRY= (A ⨁ B)B + (A ⨁ B )C
18

21. OUTPUT WAVEFORM
19

22. 250nm MGDI GDI SRLGDI
TRANSISTOR
COUNT
12 14 34
POWER
DISSIPATION
(WATT)
3.4346x10-6 5.1345x10-5 3.8215x10-3
DELAY
(SECOND)
4.923x10-9 1.29x10-8 2.18383x10-
7
COMPARISON OF SIMULATED LOGIC STYLE
180nm MGDI GDI SRLGDI
TRANSISTO
R COUNT
12 14 34
POWER
DISSIPATIO
N
(WATT)
7.3937x10-7 9.5219x10-6 9.9421x10-4
DELAY
(SECOND)
4.806x10-9 1.289x10-8 2.33x10-8
20

23. SIMULATION ANALYSIS
From the simulation and result it has been found that
 Delay, power dissipation and transistor count are lowest in case of MGDI and highest in case of
SRL.
 MGDI and GDI are better design choice when we want to design an efficient alternate of CMOS
static circuit as it is superior in every way when compared to static CMOS logic circuit.
 From the results it can be inferred that SRL has the highest delay, power dissipation and
transistor count when compared to GDI and MGDI. But it is a better design option as an
alternate of dynamic logic circuits as it reduces the clock overhead and solves the other problem
such as monotonicity requirement , charge leakage , single event upset etc.
21

24. DESIGN OF FLIP - FLOP USING MGDI
 Flip–Flop is memory element which is made up of an
assembly of logic gates.
 It is known more formally as Bistable Multivibrator as it
has two stable states
 A Flip–Flop can have one or more input .The input signals
which command Flip flop to change state are called
excitations.
 Flip–Flop serves as a storage element , it stores 1 when its
output is 1 and stores 0 when its output is 0.
 Fundamental component of shift register and counter.
FF
Q
QBAR
General Flip-Flop symbol
22

25. S-R LATCH
 Simplest type of Flip–Flop
 It has two input S and R and two output Q ( HIGH
or LOW , 1 or 0) and QBAR is complement of that
state.
 Can be constructed using two cross- coupled NOR
gate( an active- HIGH S-R latch) or two cross
coupled NAND gate(an active-LOW S-R
latch).name of the latch , S-R or SET-RESET is
derived from the name of its input.
 Output can change state any time the input are
changed so it is asynchronous Flip-Flop.
S-R
Q
QBAR
S
R
Logic symbol
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 ?
Truth Table
Logic Diagram
23

26. S-R LATCH USING CMOS AND MGDI
24S-R using CMOS S-R using MGDI

27. OUTPUT WAVEFORM OF S-R LATCH
25

28. GATED S-R LATCH
 Gated S-R latch require an ENABLE (EN) input.
 S and R input will control the state of flip flop only if
ENABLE is HIGH, the ENABLE input may be a clock.
 When EN is low , the inputs become ineffective and no
change of states can take place.
 So a Gated S-R latch is also called a clocked S-R latch or a
synchronous latch.
 Since this type of circuit responds to the change in input as
long as the clock is high so they are known as Level-
triggered Flip-Flop.
S-R
Q
QBAR
S
R
EN
Logic symbol
Logic diagram
26

29. GATED S-R LATCH USING CMOS
27

30. GATED S-R LATCH USING MGDI
28

31. OUTPUT WAVEFORM OF GATED S-R
LATCH
29

32. GATED D-LATCH
 Gated D latch has only one input D in addition to
ENABLE (EN) input
 It is constructed by using S-R latch where the input S
is inverted .
 When D=1 , we have S=1 and R=0, causing the latch
to set
 When D=0 , we have S=0 and R=1, causing the latch
to reset.
 When EN is low the latch is ineffective.
 Output follows the input when EN is high so this
latch is said to be transparent.
S-R
Q
QBAR
D
EN
Logic symbol
D Qn+1
1 Set
0 Reset
Logic diagram Truth Table
30

33. GATED D-LATCH USING CMOS
31

34. GATED D-LATCH USING MGDI
32

35. OUTPUT WAVEFORM OF GATED D-
LATCH
33

36. SIMULATION RESULT
CONFIGURATION CMOS S-R LATCH MGDI S-R LATCH
POWER DISSIPATION(WATT) 5.6579x10-6 5.2811x10-5
DELAY 1.014006x10-8 1.020327x10-8
CONFIGURATION CMOS GATED S-R LATCH MGDI GATED S-R
LATCH
POWER DISSIPATION(WATT) 3.1354x10-5 3.0008x10-4
DELAY 1.99205x10-8 3.05657X10-8
CONFIGURATION CMOS GATED D-LATCH MGDI GATED D-LATCH
POWER DISSIPATION(WATT) 1.0774x10-5 6.8544x10-5
DELAY 1.9775x10-8 1.9177x10-8
34

37. SIMULATION ANALYSIS
From the simulation and result it has been found that
 Delay, power dissipation is not improved when Flip flop is designed using MGDI.
 Only in case of gated- D latch delay is reduced in MGDI case and remaining in all other case both
power dissipation and delay is almost same or more in case of MGDI.
 So in the next chapter design of finite sate machine is done which is a combination of both
sequential circuit and combinational circuit. Here sequential circuit is designed using CMOS
while combinational circuit is designed using MGDI
 As from previous simulation it can be seen MGDI reduces power dissipation and delay in case of
combinational circuit but it does not reduce power dissipation and delay much in case of
sequential circuit 35

38. DESIGN OF FINITE STATE MODEL USING
MGDI
 FSM is a synchronous sequential machine.
 FSM are sequential circuit whose past histories can affect their future behavior in finite number of
ways.
 They have fixed number of states
 Every FSM consist of finite number of memory device.
 FSM is of two types:
 Mealy type model
 Moore type model
36Block diagram of finite state model

39. MEALY MODEL
It is a sequential circuit whose output on both the present state of the flip flop and on the input. The D input of the
flip flop determines the value of the next state, the state equation for the model can be written as
𝑦1(𝑡 + 1) = 𝑦1 𝑡 𝑥 𝑡 + 𝑦2 𝑡 𝑥(𝑡)
𝑦2(𝑡 + 1) = 𝑦1 𝑡 𝑥(𝑡)
And the output equation is
𝑧 𝑡 = {𝑦1 𝑡 + 𝑦2 𝑡 } 𝑥 𝑡 37

40. Based on the equation state table and state diagram is shown
PS NS O/P
x=0 x=1 x=0 x=1
𝑦1 𝑦2 𝑌1 𝑌2 𝑌1 𝑌2 z z
0 0 0 0 0 1 0 0
0
1 0 0 1 1 1 0
1
0 0 0 1 0 1 0
1
1 0 0 1 0 1 0
1000
01 11
1/0 0/1
0/1
1/0
1/0
0/0 1/0
(a) State Table
(b) State Diagram
0/1
38

41. DESIGN OF MEALY MODEL USING CMOS
39

42. OUTPUT WAVEFORM
40

43. DESIGN OF MEALY MODEL USING MGDI
41

44. OUTPUT WAVEFORM
42

45. SIMULATION RESULT
CMOS Mealy model MGDI Mealy model
Transistor count 58 34
Power dissipation 1.0544x 10-3 7.9813x10-4
Delay 1.23257x10-7 1.017083x10-7
Both the technique is compared on the basis of area, power dissipation and delay and from the
simulation result it has been found that MGDI has less transistor count hence less area, less power
dissipation and delay. The result is presented below in the tabular form.
43

46. CONCLUSION
Based on the work it can be concluded that Modified gate diffusion input technique is considerable while
designing low power device.
 As the most basic principle of designing low power is to lessen the transistor count so more transistor can be
accommodated in smaller area and as a result the devices which are designed will be more portable. In most
of the case it has been observed that MGDI reduces the transistor count to a considerable amount.
 Another factor which effects the low power device is power dissipation which depends on the switching
activity, the node capacitance and leakage current . MGDI in most of the cases dissipates less power as
compared to another technique.
 Delay is another parameter which depends on the number of transistor in series transistor sizes and inter cell
wiring and it is also improved when MGDI technique is used. Hence it can be concluded that MGDI is an
appropriate choice while designing low power devices
44

47. REFERENCES
1. A. Morgenshtein et al., “Gate- Diffusion Input (GDI) - A Power Efficient Method for Digital Combinatorial Circuits”
IEEE trans. VLSI, Vol. 10, no. 5, pp. 566-581, October 2002.
2. M. Alioto et al.“Mixed Logic Styles for High-Speed Low –Power Arithmetic Circuits”, Proc. of ECCTD 2003, pp.
101-104, Krakow (Poland), Sept. 2003.
3. A. Morgenshtein et al., “An Efficient Implementation of D- Flip Flop using GDI Technique” Proceedings of IEEE
International Symposium on Circuits and Systems (ISCAS), pp. 673-676, 2004.
4. Massimo Alioto et al. “High –Speed/ Low-Power Mixed Full Adder Chains: Analysis and Comparison versus
Technology” Proc. of ISCAS, pp. 2998-3001, 2007.
5. Adarsh Kumar Agrawal et al. , “A New Mixed Gate Diffusion Input Full Adder Topology for High Speed Low Power
Digital Circuits” , World Applied Sciences Journal 7( Special Issue of Computer & IT) pp.138-144, 2009
6. R.Uma, “ 4- Bit Fast Adder Design :Topology and Layout with Self-Resetting Logic for Low Power VLSI Circuit” ,
International Journal of Advanced Engineering Science and Technology, Vol. 7, Issue no. 2, pp. 197-205, 2011
45

48. 7. R.Uma et al., “Modified Gate Diffusion Input Technique: A new Technique for Enhancing
Performance in Full Adder Circuits” , International Conference on Communication, Computing and
Security, ICCS, Vol.6, pp. 74-81, 2012.
8. Uma ramadass et al., “New Low Power Delay Element in Self Resetting Logic with Modified Gate
Diffusion Input Technique”, IEE-ICSE, 2012
9. Mrs. K. Kalaiselvi, et. al.,” Design of Area Optimized High Speed Adder Circuit in Self Resetting
Logic”, IOSR Journal of VLSI and Signal , vol.4 , issue 2, pp31-38 , 2014
10. Mohan Shoba, “ GDI based Full Adder for Energy Efficient Arithmetic Applications” , Engineering
Science and Technology an International Journal, vol.19 pp. 485-496, 2016
11. R.Uma et al. “New Low Power Adders in Self Resetting Logic with Gate Diffusion Input
Technique”, Journal of King Saud University, Engineering Sciences, Vol. 29, pp.118-134, 2017.
12. Manuals of Mentor Graphics Tanner EDA Tools v 14.1
46

49. THANK YOU FOR YOUR KIND ATTENTION
47