Resume

1. BHIMSEN PRAKASH SANGAL
720 West 27th street Apt 5, Los Angeles, CA – 90007 ● 213-810-0760 ● sangal@usc.edu (sangalbp9@gmail.com)
EDUCATION
M.S., Electrical Engineering B.Eng., Electronics and Communications
University of Southern California, Dec 2017 Visvesvaraya Technological University, June 2011
GPA - 3.75 (scale 4) GPA – 80 (scale 100)
Coursework: Computer Systems Organization, MOS VLSI Digital Circuit Design, Digital System Design.
PROFESSIONAL EXPERIENCE AND SKILLS
Experience: 4+ years of experience as ASIC Verification Engineer.
Protocols Knowledge AXI4, ACE, AHB, APB, SATA 3.2, I2C, UART, SPI,
MOESI, Basic understanding of DDR and PCI.
Technical Languages System-Verilog, SV-UVM, SVA, Verilog, and VHDL
Scripting Languages Perl, Bash, and Tcl
PROJECTS
VC-Static Tool Validation in Synopsys India Pvt. Ltd., Hyderabad Mar-2015 to Dec-2015
from Einfochips Pvt. Ltd., Ahmedabad, India
 Involved in development of test-suite for validation of the tool.
 Validation is performed in SEQ (Equivalence Check), Connectivity Check (CC), UI/GUI Interface.
 Language – SV, Verilog, VHDL for design, and Assertions (SVA) for constraints.
SATA 3.2 Verification IP Development for IBM, Bangalore Aug-2014 to Mar-2015
in Einfochips Pvt. Ltd., Ahmedabad, India
 Developed Driver and Monitor components for physical and link layer.
 Language – SV-UVM.
 Tool – QuestaSim and VCS.
ARM based SoC Verification in Qualcomm, Bangalore Feb-2014 to Mar-2014
from Waferspace Pvt. Ltd., Bangalore, India
 Involved in complete SoC Verification which had 8-core processor – CORTEX A53.
 Tests planned and developed for processor subsystem with intention to communicate with
other components in the SoC System.
 Language – ARM Assembly.
Processor Verification in ARM, Bangalore Aug-2012 to Oct-2013
from Sasken Communication Technologies, Bangalore, India
 Involved in v8 Architecture based CORTEX A53 and CORTEX A57 processor verification.
 Planned and developed tests for Register set Verification, Debug, and Translation System.
 Language – ARM Assembly.
AXI4 Verification IP Development Jan-2012 to April-2012
in Sasken Communication Technologies, Bangalore, India
 Developed Driver, Monitor, Sequences/tests, Scoreboard, and Coverage.
 VIP is configurable in terms of Scoreboard, Coverage, Virtual sequencer etc.
 Language – System Verilog
AXI4-Lite to APB Translator/Interconnect Development (Design Project) May-2012 to July-2012
in Sasken Communication Technologies, Bangalore, India
 Involved in planning Architecture on FPGA.
 Developed AXI4 Side interface requirement and synchronizer module.

2. I2C Verification IP Development Jun-2014 to July-2014
in Einfochips Pvt. Ltd., Ahmedabad, India
 Developed Assertions or protocol checkers.
 Language – SVA
ACADEMIC PROJECTS
5-Stage and 7-Stage pipelined CPU Design in coursework Jan-2016 to Apr-2016
Computer Systems Organization.
 Complete design understanding of late and early branch.
 Branch prediction from Instruction Decode and Instruction Fetch stages.
 Memory Management Unit (MMU) – VA to PA translation, exceptions.
 Physically tagged and physically indexed (PTPI) Cache, Intra-core Cache coherency.
 External main memory organization.
 Language – Verilog.
Multi-Cycle CPU Design in coursework Jan-2016 to Aug-2016
Computer Systems Organization and Digital System Design.
 Instruction specific sequence of steps (ISSS) way of executing.
 Micro-programmed control unit design.
 Language – Verilog.
Tomaslu Out of Order (OoO) CPU Design in coursework Jan-2016 to Aug-2016
Computer Systems Organization and Digital System Design.
 Tomaslu algorithm for Register Renaming.
 In order commitment of executed instructions.
 Restoration from mis-predicted branch and exceptions.
 Language – Verilog.
Multi-Core Multi-Threaded CPU Design in coursework Jan-2016 to Aug-2016
Computer Systems Organization and Digital System Design.
 Cache coherency between multiple threads and multiple cores.
 MIPS atomic (exclusive) accesses – LL and SC.
 Cache control unit (CCU) and Snoopy control unit (SCU) with 2-level prioritizer.
 Non-Hidden and Hidden arbitration mechanism for arbiters.
 Language – Verilog.
Digital Phase Locked Loop (DPLL) Physical Design (PD) in coursework Jan-2016 to Apr-2016
 DPPL synchronizes at 100MHz.
 Charge pump and Voltage Controlled Oscillator (VCO) design.
 Hierarchical way of design for D-FF, Phase detector (PD) component design.
 Frequency divider (%5) design.
 Tools used – Cadence (Virtuoso).
RECOGNITIONS
 Top Performer of the Year 2013-14, Sasken Communications Technologies for working in ARM.
 Spot Awards and Pat on the back Awards, Einfochips Private Ltd.