This document is a resume for Duo Liu summarizing his education, skills, work experience, publications, and academic projects. Liu has a Master's degree in Computer Engineering from UMass Amherst and a Bachelor's degree from Jiangnan University in China. He has over 6 years of industry experience in logic verification at Intel and Synopsys. His research focused on formal verification of integer arithmetic circuits. He has published papers in top conferences and contributed to projects in regular expressions, circuit extraction, and BIST design.

1. duoliu@ecs.umass.edu DUO LIU Cell phone: 413-362-4878
http://people.umass.edu/duo 32 W Main St., Apt. 202, MARLBOROUGH, MA
EDUCATION
 University of Massachusetts Amherst, ECE Department, School of Engineering
Master of Science in Computer Engineering GPA: 3.6 May 2015
 Jiangnan University, School of Internet of Things, Wuxi, Jiangsu, China
Bachelor of Science in Microelectronics GPA: 82.5/100 Sep. 2008 – Jun. 2012
SKILLS
 Programming Languages: Python, C++, C, Verilog, VHDL, Java, SystemVerilog.
 Tools: Design Compiler, Formality, Xilinx ISE, Altium Designer, Eclipse, Cadence Virtuoso, ABC, VCS, HSPICE, Git, GDB.
 Courses: Computer Architecture, Synthesis & Verification, VLSI, Algorithms, Computer Arithmetic, Reconfigurable Computing.
RESEARCH AND INDUSTRY EXPERIENCE
 Logic Validation Engineer (Oct/5/2016 - ) Intel Corp. Hudson, MA
o Work in DDR design group as a verification engineer to provide solid and sophisticated designs to server industry
 Technical Intern (May/11/2015- Oct/2/2015) Synopsys Corp., Marlborough, MA
o Work in verification R&D group to help improve performance of industry-leading logic design compiler VCS
 Research Assistant (Jan. 2014 – Jan. 2015) ECE Dept., University of Massachusetts Amherst.
 Area: Functional Formal Verification (FFV) of Integer Arithmetic Circuits
o Implemented part of weight propagation algorithm (to do FFV of linear arithmetic circuits) and ran performance tests.
o Developed substitution algorithm (more efficient FFV method to verify datapath circuits) using Python and C++.
 Used Python to write parsers for file format conversions (Verilog, LP, equation, Excel, etc.).
 Optimized algorithmic data structure to verify large-scale arithmetic circuits (100,000+ gates).
 Implemented levelization algorithm to levelize gates (100,000+) in circuit.
 Compared performance with other tools (ABC, Formality, GLPK) and studied on FFV of synthesized circuits.
 Developed software that integrates benchmark generator, parsers, verifier and schematic generator.
 Digital Circuit Engineer (Dec. 2011 – Feb. 2012) Mu2pak Semiconductor Equipment Corp. (www.mu2pak.com), Wuxi, China.
o Developed a digital motion control card using FPGAchip Cyclone and TI chip OMAPL138 for a die bonder machine.
o Realized communication between CPUs and peripheral components like AD converters (using I2
C, UART protocols).
o Attended FPGAtraining in Ultrawise Inc. Wuxi Branch (Jun. 2011 – Jul. 2011).
PUBLICATIONS
 Duo Liu, Cunxi Yu, Daniel Holcomb "Oracle-Guided Incremental SAT Solving to Reverse Engineer Camouflaged Logic Circuits",
Design, Automation and Test in Europe (DATE'16) March 2016, Dresden, Germany.
 Samaneh Ghandali, Cunxi Yu, Duo Liu, Maciej Ciesielski "Logic Debugging of Arithmetic Circuits", 2015 IEEE Computer Society
Annual Symposium on VLSI. (ISVLSI'15).
 M. Ciesielski, C. Yu, D. Liu, and W. Brown, “ Verification of Gate-level Arithmetic Circuits by Function Extraction”, Design
Automation Conference, DAC ’15, June 07 - 11, 2015 ACM.
 M. Ciesielski, W. Brown, D. Liu, A. Rossi, “ Function Extraction using Network Flow Model”, interactive presentation/poster,
Design Automation Conference, DAC-2014, June 2014.
 M. Ciesielski, W. Brown, D. Liu, A. Rossi, “Function Extraction from Arithmetic Bit-level Circuits”, IEEE Computer Society Annual
Symposium on VLSI (ISVLSI), 356 - 361, July 2014.
ACADEMIC PROJECTS
 Regular Expression Matching Circuit (Nov. 2013)
o Built a regular expression matching circuit based on Deterministic Finite Automata (DFA) technique using VHDL.
o Ran functional, performance, power simulation in Xilinx ISE; the circuit can correctly detect target expressions.
 Steering Logic Extraction (Feb. 2013 – Apr. 2013)
o Synthesized and optimized a Finite Impulse Response (FIR8) filter circuit using GAUT and TDS.
o Wrote a parser (in Python) that extracts steering logic from Verilog file and convert it to dot (graph description language).
 8-bit multi-functional Build-In Self-Testing (BIST) Circuit (Apr. 2013)
o Integrated scan chain with linear feedback shift register (LFSR) to build a BIST with reset, normal, scan and test modes.
o Built architecture using Cadence Virtuoso and ran functional, performance and power simulation using HSPICE.
 Built Johnson Counters with different flip-flops and compared their performances (schematic to layout). (Dec. 2012)
 Built Calendar Scheduler for visually impaired on Android platform using Eclipse. (Oct. 2012 – Dec. 2012)
 Designed the front-end signal receiving circuit for The Automated Defogging System for Automobiles. (Jul. 2011 – Sep. 2011)