1. Pavan Anand Vivekananda
600, 10th
Avenue, SE, Apt #106 Minneapolis, MN-55414
Email: vivek005@umn.edu http://www.linkedin.com/in/pavananandv/ Phone: +1 612 707 4976
OBJECTIVE: Seeking Fulltime opportunity in a VLSI industry that will utilize my work experience in ASIC design and
verification.
EDUCATION:
Master of Science in Electrical Engineering Expected Graduation: Dec 2015
University of Minnesota – Twin Cities, Minneapolis, Minnesota CGPA: 3.87/4.0
 Coursework: VLSI Design I, VLSI Design Automation (CAD), Basic Computer Architecture, VLSI Design Lab.
Bachelor of Engineering in Electronics and Communication Engineering Graduated: June 2011
R.V. College of Engineering, Bangalore, India CGPA: 9.37/10
VLSI Domain Skills:
 Programming Languages: System Verilog, Verilog, System Verilog Assertions, C, C++.
 Verification Methodologies: UVM, Assertion Based Verification, Coverage Driven Verification.
 Scripting Language: Perl.
 EDA Tools: ModelSim, NCSim, Incisive Coverage Tool 8.10, eManager regression tool.
 Protocols Known: eMMC4.5, UFS, SCSI, APB, AHB.
 Domain Experience: ASIC Verification, Palladium PXP.
WORK EXPERIENCE:
Freescale Semiconductors, Austin, Texas, USA [May 2015 – Aug 2015]
Functional Verification Intern – 3 Months
Project: Verification of SOC designs used in automotive applications:
 Coded a script for automating the regression report generation.
 Measured and analyzed performance results from an emulation build.
 Measured and analyzed micro-benchmark in RTL simulation on Automotive SOC design with flash.
Samsung Research India Bangalore, India
Senior Hardware Engineer – 3years [July 2011-July 2014]
Profile: ASIC Design and Verification Engineer
Projects:
 Development of Verification Environment for Asynchronous FIFO: July’11 – Nov’11
Description: In this project Asynchronous FIFO RTL was verified by developing an UVM based verification environment.
 Development of eMMC4.5 Accelerated VIP and Integration into SOC: Dec’11 – Sep’12
Description: To verify this complex SOC that consists of eMMC device controller and NAND flash, an UVM based
verification environment is developed using SCE-MI protocol. This project is targeted for Cadence Palladium PXP.
 Development of Verification Environment for UFS (Universal Flash Storage) IP: Oct’12 – Feb’13
Description: This project aimed at verifying UFS IP by developing UVM based verification environment.
 Development of UFS Accelerated VIP and Integration into SOC: Mar’12 – Oct’13
Description: In this project synthesizable components such as command decoder and driver BFM were developed. This
project is targeted for Cadence Palladium PXP.
Responsibilities:
 Designed AVIPs for verifying eMMC4.5 on Cadence Palladium PXP. It involved developing synthesizable driver and
collector BFM (Bus Functional Model).
 Developed UVC for verifying UFS controller using UVM (Universal Verification Methodology).
 Worked on DPI for importing C-test cases from C-environment to UVM environment.
 Presented a paper on “Acceleration Based Verification” at Samsung.
GRADUATE PROJECTS:
RTL Design and Verification of Out-of-Order Processor using TOMASULO's Algorithm [Feb 2015 –May 2015]
 Implemented Instruction dispatch unit that handles Out Of Order execution of instructions using Tomasulo's Algorithm.
 Handled RAW, WAR and WAW hazards by synchronizing all the Functional Blocks with Instruction Dispatch unit.
 Developed System Verilog based layered test bench and Constrained Randomized test cases to verify the design.
 Designed a Coverage driven test environment using System Verilog.
Implemented Iterated 1-Steiner Algorithm for Routing in Physical design [Sep 2014 – Oct 2014]
 Implemented the Iterated 1-Steiner algorithm for routing in physical design using C++.
 Obtained optimal simulation results and minimum wire length for the routing of given set of input vertices.
Implemented Vanginneken Buffer Insertion Algorithm [Nov 2014- Dec 2014]
 Implemented Vanginneken buffer insertion algorithm using C++ in order to reduce long wire delays.
 Simulations are done on net-list and optimal delay values at the driver are obtained.
Full custom ASIC design of 16-bit Kogge-Stone adder [Nov 2014 –Dec 2014]
 Designed the schematic and Layout of 16-bit Kogge_stone adder and optimized the layout for operating frequency of 1Ghz.