1. SAGAR PRADIP PATIL
Dallas, Texas 75252 sagar.patil1@utdallas.edu
Mob. 972-408-8783
OBJECTIVE: Self-motivated, diligent individual actively seeking a summer internship in physical layout design, RTL design, logic
verification to gain hands on project experience and benefit the company while developing skills under experienced professionals.
EDUCATION:
Master of Science in Electrical Engineering (Digital Systems) GPA 3.67/4
The University of Texas at Dallas, Richardson, TX, USA (Aug 2015 - May 2017)
Bachelor of Technology in Electrical Engineering CGPA 8.37/10 (Jun 2009 – May 2013)
Walchand College of Engineering, Sangli, India Academic Bronze Medalist
COMPUTER / HARDWARE SKILLS:
Programming Languages: C, C++, Verilog, VHDL, Python, Perl, Tcl, System Verilog
Layout, Simulation and Synthesis Tools: Cadence Virtuoso, HSPICE, ModelSim, Xilinx ISE, P-Spice, Design Vision
Additional Tools Used: Synopsys, Tetramax, Cplex, Code Composer Studio, AutoCAD 2013, MATLAB, Simulink, AVR Studio, Keil
Operating Systems: Windows 95/7/8/10, UNIX
Hardware: Xilinx Nexys3, MSP430, MSP432, ATMEGA 16, ATMEGA 32, 8051, Arduino, PLC (Allen-Bradley, Siemens), Picoblaze
WORK EXPERIENCE:
Research Student, University of Texas at Dallas, USA (Jan 2016 – Apr 2016)
 Physical object tracking by camera installed in head of humanoid robot. Visual servoing implementation using OpenCV.
 Activating humanoid hand servo motor determined by reverse kinematics to pick up object tracked by Firewire stereo camera.
Assistant System Engineer (Design), Tata Consultancy Services, Pune, India (Sept 2013 - Jun 2015)
 Delivered critical design projects under stringent deadlines for the client, General Electric India Pvt. Ltd, in office and on-site.
 Designed vibration and temperature monitoring electrical system, signal wiring, network architecture in AutoCAD 2013.
 Received client appreciations for quality, timely projects delivery, innovation and achieved customer satisfaction index of 99%.
RELEVANT TECHNICAL PROJECTS:
 Design & Synthesis of Digital Phase Lock Loop (Sep 2015 – Nov 2015) – Designed RTL in Verilog and synthesized final design in
Synopsys Design compiler by using newly created standard cell library. Automatic placement and routing of cells by EDI
Encounter. Performed DRC and LVS on final layout of chip. Performed STA by Primetime to calculate slack and finalized freq.
 Design and Testing of Digital Circuit (Oct 2015) – Modeled digital structural combinational circuits in VHDL code and imported
generated netlist in Tetramax to find out all stuck at faults, test patterns/vectors by ATPG and fault coverage.
 Standard Cell Library (Oct 2015) – Designed standard cells layouts of INV, NAND2, NOR2, AOI22, OAI2221, MUX21, D flip-flop,
XNOR2, OAI21 in Cadence Virtuoso layout editing tool (IBM 130nm design rules) and verified functionality of each cell on
Hspice. Minimized energy delay product (EDP) of an INV. Created new library file using SiliconSmart ACE and Library Compiler
by Synopsys. Optimized height and maintained pin pitch for all cells.
 Reverse Engineering of 32bit ARM Processor (Nov 2015) – Designed ALU, Register, Multiplier, Shifter, Control unit, Memory
modules in Verilog and implemented on Xilinx Spartan-6 Nexys 3 FPGA board. Tested and verified for sampled instruction set.
 Designing Customizable Microprocessor µUT (Jan 2016 – Apr 2016) – Designed a simple 16-bit customizable microprocessor
called µUT. IS, processor architecture and micro-operation cycles have been customized. Implemented using Xilinx Spartan-6.
 Cache Hierarchy Optimization (Feb 2016 – Mar 2016) – Fine tuning of cache hierarchy on x86 architecture based gem5
simulator, wrote python script to calculated CPI & try out various cache configurations for benchmarks, defined cost function.
 Implementation of Tomasulo’s Algorithm (Mar 2016 – Apr 2016) – Designed hardware architecture in Verilog as proposed by
Tomasulo to implement out of order execution. Planned to implement it on Xilinx Spartan-6 FPGA to verify functionality.
RELEVANT TECHNICAL COURSEWORK: VLSI Design, Advanced Digital Logic, Microprocessor Systems, Testing and Testable Design,
Computer Architecture, Real Time Systems.
PUBLICATIONS and CERTIFICATIONS:
 Proposed IEEE Case Paper – “Dancing Humanoid Robot ‘Buddy’ for Rehabilitation” (Apr 2016)
 Published IJIRSET research paper – “Electrical Power Theft Detection and Wireless Meter Reading” (Apr 2013)
 Physical Design Flow (Udemy) – Floorplanning steps, Netlist binding and placement optimization, Static timing analysis with
ideal and noisy real clock, Setup and hold timing analysis with multiple clocks, Power planning (Jan 2016 – Mar 2016)
 Building OVM and UVM Testbenches (Udemy) – Building testbench components (Mar2016 – May 2016)
HONORS AND ACTIVITIES:
 Member – Institute of Electrical and Electronics Engineers, UT Dallas (Aug 2015 - Present)
 One of the founder members of WCE robotics club and led college team at national level ROBOCON, India 2013 (Mar 2013)