Resume

1. Rajas Mhaskar
LinkedIn: RajasMhaskar Email: rajas.mhaskar@gmail.com Phone: 424-527-9680
Education
Master of Science, Computer Science Sept’19 – Dec’20
University of California, Los Angeles | GPA : 4.0 / 4.0
Bachelors & Masters of Technology, Engineering Design in Industrial Electronics July’12 –May’17
Indian Institute of Technology, Kharagpur | GPA: 8.41 / 10
Work Experience
Cadence Design Systems ,Tensilica IP, Pune June’17 –Sept’19
Design Engineer II, June ’17 – June’19 | Lead Design Engineer, July’19 – Sept’19
 Vision Software: Developed optimized vision software for Tensilica Vision DSPs
o Monocular Visual SLAM: Reference C++ and DSP optimized code for modules such as Key point Detection,
Pose Estimation, Bundle Adjustment, Loop Closure and Bag of Words.
o Stereo Global Block Matching: Performance and memory optimization of the local cost computation modules.
o Alexnet: Performance optimization of the Alexnet network for Vision P6 processor
 DSP Architecture: Worked on VLIW and SIMD Vision DSP architectures
o Vision Benchmarks: Analyzing the benchmark performance deviations due to pipeline changes in different
families of processors.
o Core Architecture: Experimenting with Instruction Set Architectures (ISA) by writing TIE to improve
benchmark performance cycles.
o Power Analysis: Analysed unit level power reports for Vision P6 and Vision Q6 DSP cores and improved the
core design to reduce power consumption for some benchmarks.
o ISS vs RTL: Debugged cycle performance deviations between instruction set simulators& RTL.
Cadence Design Systems ,Tensilica IP, Pune (Design Engineering Intern) Jan’16- June’16
 Introduced MISRA-C embedded coding guidelines in the Audio DSP group.
 Optimized multiple modules of the OPUS 1.1.2 audio codec for the HiFi3 audio DSP core.
 Developed a Python based FFT tool for comparing two audio signals in frequency domain
 Developed a Perl based systematic corruption technique for corrupting audio frame headers.
National Instruments India , Bangalore (Applications Engineering Intern) May ’15 – July ’15
 Developed LabVIEW data acquisition modules for FPGA based NI myRIO.
Projects
Fault Detection & Diagnosis of Digitally Controlled Analog Circuits atPost-Silicon Level (Thesis Project, IIT)
 Generated a fault table for mixed signal circuits by adding formal assertions, injecting faults and simulating on
Cadence Virtuoso.
 Developed algorithms and implemented a C++ tool for producing optimal set of test vectors which can diagnose
and detect the faults in the fault list given the fault table.
Software Engineering Lab Term Project- Online Sales Portal
 Designed (UML, SRS) and developed in Java an online portal for multiple buyers and sellers
Case Study for Acceleration of Graph Convolutional Networks on CPU and GPU
 Achieved upto 100X gain on an Intel Xeon Gold CPU using AVX512 intrinsics and multi-threading using OpenMP.
 Achieved a 200X gain on a Tesla P4 GPU by developing an optimized CUDA kernel for feature convolution
Term Paper – Improved TLB coverage by Exploiting Contiguous Memory Allocations
 Analyzed & performed a comparative study of hardware and software (OS) based techniques for coalescing multiple
TLB page table entries for improving the TLB coverage as a part of the Advanced Computer Architecture course.
Publications/Presentations:
 Co-author for the presentation titled ‘Fundamentals of Monocular SLAM’ presented at the Embedded Vision
Summit 2019 under the Fundamentals track in May 2019. (EVS 2019)
 Delivered a Cadence Brown Bag presentation on Visual SLAM in July 2019.
Academic Achievements:
 Graduated with Branch Rank 1 in the Engineering Design dual degree course, IIT Kharagpur.
 Cleared the Indian National Mathematics Olympiad (INMO) in 2011 and was among the top 30 students selected
from India to attend the International Mathematics Olympiad Training Camp.
 Honourable Mention at ACM Online Regional Contest in 2016 and 2017
Software Skills
Debuggers: GDB , Visual Studio. Programming Languages: C, C++, Java, Python, Perl
Softwares: Netbeans IDE. Scilab, Matlab, Simulink Parallel Programming Frameworks: CUDA, OpenMP
Teaching & Other Activities
 Teaching Assistant for CS-M182 Systems Biomodelling and Simulation Basics, Fall 2019 at UCLA.
 Delivered a lecture on Euclidean Geometry to high school students. (PreRMO camp IIT KGP)
 Cleared CFA (Chartered Financial Analyst) Level 1 in December 2017