1. Pratik Chaudhary
85 Rio Robles East, 1209, San Jose - 95134, 716-445-2023, pratikmc@usc.edu, www.linkedin.com/in/pratikchaudhary/
EDUCATION
MS in Electrical Engineering - Viterbi School of Engineering Expected May 2015
University of Southern California, Los Angeles GPA: 3.50/4.0
Relevant Coursework: Operating Systems (CS402), Digital Systems Designs Tools and Techniques (EE560), Network
Processor Design and Programming (EE533), Computer Systems Architecture (EE557), Computer Networks (EE450),
Computer Systems Organization (EE457), Internet and Cloud Computing (EE543).
BE in Electronics Engineering - University of Mumbai, India (Rank: 7/75) June 2009 - May 2013
TECHNICAL PROFICIENCIES
 Programming Languages: C, VHDL, Verilog, Perl and Python (basics).
 Tools: GDB, Xilinx, AWS, Wireshark, ModelSim, Matlab, SPSS, OPNET, MS-Office, Picoblaze, Chipscope.
RESEARCH
 Working on Cache coherency in a system where cores are connected to the banks of L2 cache via memory
Interconnection Network using AXI and ACE protocols under the guidance of Prof. Gandhi Puvvada.
 Designing directory based MOESI implementation for the same, using LL (Load Linked) and SC (Store Conditional)
instructions on the multithreaded core of a CMT and implementing it on FPGA (Verilog).
PROJECTS
Weenix Kernel Nov 2014
 Programmed modules of bootstrap loader like process creation, thread creation, scheduling and synchronization
primitives using C and QEMU emulator.
 Implemented Virtual File System and Virtual Memory Management System Modules as well.
DNS caching on Multi-Core Multi-Thread Network Processor (www.nvprocessor.weebly.com) May 2014
 Designed a multi-core multi-threaded network processor on NetFPGA which performs all basic operations of ALU,
by using an inter-convertible FIFO for Data Memory, using Xilinx ISE and Verilog.
 Executed Hardware DNS caching to reduce the DNS query time and controlled Data Metering.
 A Team of 4 formulated our own ISA and Compiler(C and Assembly Language).
Tomasulo Algorithm based Processor (ModelSim, Xilinx, Digilent Adept) July 2014
 Designed and Implemented 32-bit Out-of-Order (Tomasulo) execution processor to dynamically schedule
instructions, and commit in order on Nexys4 LX45 FPGA board using VHDL.
 Developed modules like store buffer, address buffer, Issue unit, Branch Prediction Buffer, Dispatch Unit, Re-Order
Buffer, Free Register List and Copy Free Check-pointing for speculative execution and handle branch miss
prediction.
Multi-threading - Token Bucket Emulation (POSIX Threads) Sept 2014
 Emulated a traffic shaper who transmits packets controlled by a token bucket filter using multi-threading within a
single process (C).
Chip Multi-Threading Processor June 2014
 Implemented a 4 threaded processor which consisted of Store Buffer, Thread Scheduler and Rotating Buffer and
non-blocking cache using miss status handling registers (MSHR’s) on Xilinx FPGA (VHDL).
MIPS 5-Stage Pipeline with BRAMs June 2014
 Modeled a CPU with two clock FIFO using BRAMs, avoiding any dummy stages (VHDL).
Inter-Convertible FIFO March 2014
 Simulated an inter-convertible FIFO along with Single Core Processor on NetFPGA. The FIFO initially operates as a
data memory of the single core and stores the incoming packet, then by making the write enable pin high we can
modify the data in FIFO if and as needed. The modified packet is forwarded hereafter (VERILOG).