1. Vinaya B Adiga
E-Mail: adigabvinaya@gmail.com
Phone: +91-9035920073
P R O F I L E S U M M A R Y
 Post Graduated in VLSI Design from Manipal Centre for Information Sciences (MCIS) Manipal.
 Acquainted with various EDA Tools like Questasim, Modelsim v10, Riviera PRO, BluePearl (Linting). 
 Possess VLSI domain skills such as Verilog, System Verilog with UVM, familiar with Perl. 
 Acquainted with protocols such as APB, AXI 3.0, AXI 4.0 and PCIe 3.0. 
 Good understanding of ASIC design flow. 
P R O F E S S I O N A L S K I L L S
 HDL: Verilog.
 HVL (Methodology): System Verilog (Universal Verification Methodology).
 EDA Tools: Questasim, Modelsim v10, Riviera PRO, BluePearl (Linting), 
Familiar with VCS. 
 VLSI Domain Skills: Front-End Designing (RTL Coding Using Verilog), Digital Designing, SVA.
 Scripting Language: Familiar with Perl.
 Protocols Known: APB, AXI 3.0, AXI 4.0 and PCIe 3.0.
E X P E R I E N C E
Company/Institute: Veriedge Technologies Pvt Ltd
Role: VLSI Design Verification Engineer
Duration: Since April 2015 to till date
Description: Executed the Project “Everest – Design and Verification of NVMe Controller”
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Company/Institute: CVC Pvt Ltd
Role: VLSI Design Verification Trainee
Duration: From Aug 2014 to April 2015
Description: Executed the Project “Design of SD Card Controller”,
Development of UVM environment for Memory Controller.

Company/Institute: Yokogawa India Ltd
Role: System Engineer Trainee
Duration: From Aug 2011 to Feb 2012 
Description: Development of Logics using Functional Block Diagrams for Process Plants (DCS)
A C A D E M I C D E T A I L S
 M Sc Tech (VLSI Design) from Manipal Centre for Information Sciences, Manipal in 2014 with 8.22 CGPA. 
 BE (Instrumentation Technology) from M S Ramaiah Institute of Technology, Bangalore in 2011 with 8.32
CGPA.
P U B L I C A T I O N
TOPIC: Verification Framework for IO Accelerators using SV Models
Publisher: IP-SOC 2015 Conference, Grenoble
Description: Co-author of the technical paper presented on IP-SOC 2015 Conference, Grenoble
Targeting a position as Design and Verification Engineer in VLSI Domain

2. P R O J E C T S
Title: Everest Controller (NVMe Controller) (Currently Working)
Tools used: Questasim.
Description:
 Understanding of High Level Architecture of NVMe on PCIe Fabric. 
 Understanding of NVMe 1.2 Specification.
 Building UVM based environment using System Verilog. 
 Implementation of Reactive Slave Verification Components. 
 Development of PCIe Bus Function Models.
 Good understanding of PCIe topology, Transaction Layer and Data Link Layer. 
 Understanding and analyses of ARM interfaces like APB, AXI 4.0.
 Writing test cases for the same environment. 
 Development of Test Plan for Verification of NVMe Controller.

P R O J E C T S
Title: SD Card Controller
Tools used: Modelsim, BluePearl, Quartus.
Description:
 Understanding of operation and command set in SD card. 
 Design of Card Detection and Initialization Sequence FSM.
 Use of BluePearl Tool for Linting. 
 Verification of the Design using Verilog. 
 Synthesized the Design using Quartus Tool. 

P R O J E C T S
Title: Memory Controller
Tools used: Questasim.
Description:
 Understanding of Memory Controller Design. 
 Building UVM based environment using System Verilog. 
 Test Plan Development for Memory Controller Design.
 Code and Functional Coverage analysis.
 Writing test cases for the same environment. 
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Father’s Name: U Bhaskar Adiga
Date of Birth: 18th October 1989
Languages Known: Kannada, English, Hindi and Telugu
Sex: Male
Current Address: #1775, 21st Main, Fourth Floor, Agara, HSR Layout, Sector 1, Bangalore - 560102
Permanent Address: “Manjugiri Nilaya” Near SLV Temple 3rd Main, 1st Cross Shanthinagar Tumkur - 572104