1. Zhenyu Xu
13 North Coleman Rd, Centereach, NY11720, 631-800-6008, zhenyu.xu@stonybrook.edu
Objective
Candidate with comprehensive experience in Digital Design Research pursuing a full-time job in ASIC/FPGA design or verification
Education
December 2015 MS Electrical and Computer Engineering, Stony Brook University, NY, 3.91/4.0
 Courses: Advanced Digital System Design and Generation, Computer Architecture, Advanced VLSI System Design, Hardware-
Software Co-Design of Embedded Systems, Advanced VLSI System Testing, Nanoscale Integrated Circuit Design, Digital Signal
Processing, Integrated Electronic Devices and Circuits (in progress)
July 2014 B.E. Integrated circuit design and integrated system, Tianjin University, Tianjin, China, 85/100
 Courses: Verilog, C++ and Data Structure, Digital IC, FPGA, EDA, SoC, VLSI Interconnect, Mixed-signal Circuit, IC Layout
 Graduation Thesis: Digital Circuits Pipelining Based on Logic-level Analysis (Excellent graduation thesis top 10%)
Skills
 Deep understanding in ASIC, SoC, FPGA logic/physical design, verification, testing and high-level synthesis
 In-depth knowledge of computer architecture, operating system, memory and cache structure
 3+ years experiences in Verilog, 1+ year for SystemVerilog, knowledge of SystemC
 Programming languages: 3+ years experiences in C/C++, knowing assembly language, java and Python
 EDA tools: Pspice, Hspice, Cadence Virtuoso, Modelsim, Quartus, ISE, Vivado, Synopsis Design Suite, Matlab
 In-depth understanding of transistors, analog and mixed signal circuits design, semiconductor properties and manufacture techniques
Academic Projects
Research Assistant in CEWIT (Automatic Hardware Generation & Optimization Lab) Jan. 2015—Present
 Used Xilinx Zedboard to generate a digital system which aims at accelerating k-mer counting in DNA
 Designed an out-of-order two level cache-structured kmer counter with AXI interface, which can do DMA access and adjust itself to
several gigabytes of kmer data and sort them efficiently
 Generated the system in Vivado and using debugging tool and checked the data in memory to test it
Research Assistant in Tianjin University (Hardware EDA Lab) March. 2013—May. 2014
 Did some research on the structure of FPGA, especially optimizing the efficiency and security of AES on FPGA
 Implemented AES on image encryption/decryption and using Xilinx Chipscope during on board debugging
 My research papers are published by ICFPT and IET Computers & Digital Techniques
Selected Course Projects
Dual-issue multimedia processor architecture Feb. 2015—April. 2015
 Designing a dual-issue multimedia processor with floating point unit which has the same pipeline stages as CELL SPU to support
SIMD functionality using Verilog, which detect data hazard, structure hazard and control hazard
 Using python to design a parser of the processor, which transfers assembly code into binary code
 Successfully simulating the processor with some sets of assembly code including branch and hazard controlling
Hardware generator for a multi-stage pipelined ALU Nov.2014
 Designed a hardware generator in C that can automatically generates SystemVerilog code of pipelined ALU as well as testbench
based on user’s requirement
 Used C code to test the correctness of the generated code and testbench
Full-custom 8-bit processor design Dec. 2014
 Devised a full-custom 8-bit single cycle processor with adder, shifter, MUX, latches, SRAM and control unit for both schematic and
layout in Cadence Virtuoso and verified it with several instructions
 Minimized the area and power consumption and increased clock frequency for post-layout simulation
PODEM ATPG April. 2015—May. 2015
 Used C++ to construct PODEM algorithm, an automatic test pattern generation (ATPG) tool
 Implemented different techniques to optimize the algorithm, such as event driven simulation, calculating SCOAP metrics, etc
 After evaluating the optimized version, the speed up is more than 15X comparing to the original algorithm
Interaction sound recording badge Oct. 2014—Dec. 2014
 Built a system with microphone front end circuit, PGA, ADC, LPF and UART module on PSoC1
 Implemented Maximum likelihood algorithm to detect the angle of arrival of the sound source in C
 Implemented FFT and frequency analysis to realize voice recognition in C, also simulated in Matlab
Clock distribution network design May. 2015
 Devised a clock distribution network with strict constraints on clock frequency, clock skew, and clock slew in Cadence Virtuoso
 Minimized the power of the network
Publications
 A 66.1 Gbps Throughput Single-pipeline AES on FPGA
 High Throughput and Secure AES on FPGA with Fine Pipelining and Enhanced Key Expansion
Honors & Awards
 “Merit Student” Scholarship, Tianjin University 2012