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Manjunath Kudari
No 134, Nobo Nagar
Bannerghatta Road, Email: manjunath_k@live.in
Bangalore- 560076 Mobile: +91 9611729906...
Bachelor of Engineering SJB Institute of Technology, Bangalore
Visvesvaraya Technological University Belgaum, Karnataka, I...
 Implemented the Dual Port Ram using Verilog HDL.
 Architected the class based verification environment using system Ver...
 Firstly trial samples are created and stored in the database.
 When a command is given it is compared with the samples ...
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Cv of manjunath kudari

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Cv of manjunath kudari

  1. 1. Manjunath Kudari No 134, Nobo Nagar Bannerghatta Road, Email: manjunath_k@live.in Bangalore- 560076 Mobile: +91 9611729906 _______________________________________________________________________ Summary of Qualifications  Good understanding of the ASIC and FPGA design flow  Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog.  Very good knowledge in verification methodologies, UVM  Experience in using industry standard EDA tools for the front-end design and verification Languages : Basics of C, C++, Verilog, System Verilog. Areas of interest : VLSI, ASIC Design, FPGA, System Verilog, Embedded Systems, Microcontrollers Operating systems : Windows Server 2008 R2, Windows 7, Windows XP, Windows 8 Mac OS 10.7(Lion), Linux Red hat 6, Ubuntu. VLSI Domain Skills HDLs: Verilog HVL: SystemVerilog Verification Methodologies: Coverage Driven Verification TB Methodology: UVM EDA Tool: Modelsim/Questa sim and ISE Domain: ASIC/FPGA Design Flow, Digital Design methodologies Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, Assertion Based Verification. Professional Qualification Maven Silicon Certified Advanced VLSI Design and Verification course Maven Silicon VLSI Design and Training Center, Bangalore Year: June 2013 – October 2013
  2. 2. Bachelor of Engineering SJB Institute of Technology, Bangalore Visvesvaraya Technological University Belgaum, Karnataka, India Discipline: Electronics and Communication Engineering. Aggregate Percentage: 65% . Year: 2007 - 2011. Technical Papers: . Adaptive approach for safety control & security system modification in computer systems and networks. Experience Dec 2011 – Feb 2013, TCS Mumbai, System Engineer. Roles and Responsibilities:  Installed, upgraded and maintenance of server hardware components as per requirement.  Creating standard process for group policy deployment.  Active Directory users and groups management.  Implementation and administration of DNS, DHCP.  Creating standard Net-backup policies for servers.  Patch management – Installing Patches on Servers and Client Computers.  Business Continuity Process (BCP) Co-ordination & Support.  Conducting monthly meetings with Team Lead’s . Achievements:  Awarded for setting up a project by handling activities end-to-end.  On the Spot Award for solving an issue relating to Server.  ITIL Certification(TCS internal) VLSI Projects Dual Port RAM – verification HVL: System Verilog EDA Tools: Model sim, Questa – Verification Platform and ISE
  3. 3.  Implemented the Dual Port Ram using Verilog HDL.  Architected the class based verification environment using system Verilog.  Verified the RTL module using System Verilog.  Generated functional and code coverage for the RTL verification. Router 1x3 – RTL design and Verification HDL: Verilog HVL: SystemVerilog EDA Tools: Model sim, Questa -- Verification Platform and ISE Description: The router accepts data packets on a single 8-bit port from the source and routes the packets to one of the three output clients depending on the destination address present in the header byte.  Architected the design and described the functionality using Verilog HDL.  Synthesized the design.  Architected the class based verification environment using system Verilog.  Verified the RTL model using UVM.  Generated functional and code coverage for the RTL verification. SPI Controller Core - Verification HVL: System Verilog EDA Tools: Modelsim, Questa -- Verification Platform Description : The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock. This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register. The SPI Core RTL is technology independent and fully synthesizable.  Architected the class based verification environment using system Verilog  Verified the RTL module using System Verilog  Generated functional and code coverage for the RTL verification sign-off Engineering Project Voice Controlled Automation System. Jan 2011 – June 2011 , SJB Institute of Technology, Bangalore.  Used to automate the tasks that require hands-on human interaction using Speech Recognition Method.
  4. 4.  Firstly trial samples are created and stored in the database.  When a command is given it is compared with the samples present in the database created, the task is executed if it matches with the any of the samples present.  Tool used is MatLab. Personal Details: Date of Birth : 15th Oct 1989 Father name : S.B.Kudari Permanent address : # 30 Vijayananda Nagar, near R C Nagar, Dharwad 580001 Nationality : Indian Language Known : Kannada, English, Hindi. References On Request

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