1. Pavankumar Banakar
2809, Avent Ferry Road, Apt #103 Raleigh, NC-27606
Email: pbanaka@ncsu.edu www.linkedin.com/in/pavankumarbanakar/ Phone: +1 919 675 9193
OBJECTIVE:
Actively looking for full time opportunity in the field of ASIC design, verification or validation.
EDUCATION:
Master of Science in Electrical and Computer Engineering Expected Graduation: Dec 2015
North Carolina State University, Raleigh, North Carolina GPA 3.945/4.0
 Coursework: ASIC Design(2015), VLSI Design (Fall 2014), Computer Design and Technology (Fall 2014) and
Architecture of parallel computers (Fall 2014), Topics in Advanced Computer Architecture: Data Parallel Processors
(2015), Embedded Systems (2015)
Bachelor of Engineering in Electronics and Communication Engineering Graduated: June 2011
R.V. College of Engineering, Bangalore, India GPA 9.01/10
TECHNICAL SKILLS:
Programming Languages: C, C++, Verilog
Operating Systems: Windows, Linux
Scripting Language: Python, Perl
Tools: ModelSim, Synopsys design_vision, HSPICE, Cadence (Virtuoso schematic and layout), cscope
IDE: Keil uVision, PSoC Creator, Eclipse
WORK EXPERIENCE:
Cypress Semiconductor India Pvt. Ltd [Aug 2011-Aug 2014]
Senior Systems Engineer, Kits and Development Team
 Contributed in design, hardware definition, post silicon validation and manufacturing support in Cypress development kits.
 Designed a protection circuit for low voltage PSoC devices on development kits, which is published in Embedded.com
 Part of “Failure Analysis“ team and completed the failure analysis of returned kits within 48 hours of receipt.
Validation of PSoC4 SoC: [June 2013 – Dec 2013]
 Created a test list and validated SPI communication block using Python
 Automated the SPI validation process using Aardvark and Beagle tool.
 Validated the Capacitive Sense IP Block on PSoC 4 device and coordinated to get EMC/EMI certification for the product.
Validation of PSoC 5LP SoC: [Nov 2012 – May 2013]
 Created a test list and validated the I2C communication IP block using Python, Aardvark and Beagle tools.
 Validated the Capacitive Sense IP block on PSoC 5LP/Panther LP device and coordinated to get EMC/EMI certification for
the product.
GRADUATE PROJECTS:
ASIC design of Equation Solver using Jacobi Iteration [Feb 2015 – March 2015]
 We are solving a system of equations (YV=I) using Jacobi Iteration method. The matrix Y and I are made up of complex 24
bit floating point numbers. The aim of the project is to achieve maximum throughput per unit area.
Verilog and ModelSim [Dec 2014 – April 2015]
 In depth learning of verilog language by doing KIRK lab exercises from hdlexpress.com
 Down counter: Design and synthesize the down counter in Verilog and created a test bench to test it using ModelSim and
Design_vision.
2 Port 16x4 SRAM Memory with Sleep mode Design [Nov 2014 – Dec 2014]
 The memory was designed using 8T bit cell to optimize the product of active energy, total delay and inactive energy.
Implementation of Tomasulo Algorithm for out of order execution [Nov 2014 – Dec 2014]
 Implementation of Tomasulo algorithm on an out of order super scalar execution pipeline.
 Simulate the dependence of Cycles Per Instruction (CPI) on the scheduling size and fetch size of a superscalar out of order,
imprecise state processor.
Simulation of Branch Predictors [Oct 2014- Nov 2014]
 Measurement of bimodal, gshare and hybrid branch predictor performance on gcc and perl trace files.
Simulation of Cache and Memory Hierarchy Design [Sep 2014 – Oct 2014]
 Implementation of replacement policies Least Recently Used (LRU), Least Frequently Used (LFU) and write policies
(WBWA & WTWNA).
 Measurement of cache performance (average access time, miss rates) in different cache configurations (L1 + victim, L1+L2,
L1+L2+victim).
Simulation of MSI, MESI and Dragon Cache Coherence Protocol [Nov 2014 – Dec2014]
 Measurement of performance like miss rates, number of memory operations with varying cache size and associativity.
Optimization of Roll & Pitch Calculation on Freedom Kit: [Feb 2015 – Feb 2015]
 Optimize the program on Freedom board (ARM Cortex M0) to read accelerometer Data over I2C and calculate roll & pitch
angles less than 200us which was taking 10ms without any optimization.