SlideShare a Scribd company logo
1 of 55
Group Members
 12063122-011 ( M.Noman
)
 12063122-017 ( Hafiz
Hamid )
 12063122-029 ( Salah
Uddin Ayubi )
 12063122-037 ( Mubashar
Naeem )
 12063122-023 ( Safi ur
rehman Tabasum )
 University Of Gujrat
(Pakistan)
Internal microprocessor
architecture
 ON the basis of programing
Microprocessor’s type
Internal structure of microprocessor should be known
Single core 1. single task at any time
2.access whole memory at
the same time by any program
Dual core 1.multiple task at any time
2.access specific memory by
any task
Programing model
Program visible : 8086,8088
Registers are used directly
during programing
Program invisible : 80286 and above
1. Registers are not accessible
directly during programing
2. Can be used indirectly
Programing model
Program visible : 8086,8088
Registers are used directly
during programing
Program invisible : 80286 and above
1. Registers are not accessible
directly during programing
2. Can be used indirectly
Only for 64 bit
cont.….
 We can’t access these register with the instruction used
to access general purpose register AX,BX etc….
 To access the low order byte of R8 use R8B
 To access the low order word of R10 use R10W
Cont.……
Condition flag
Special purpose flag
 The 6 Segment Registers are:
 Stack Segment (SS). Pointer to
the stack.
 Code Segment (CS). Pointer to
the code.
 Data Segment (DS). Pointer to
the data.
 Extra Segment (ES). Pointer to
extra data ('E' stands for 'Extra').
 F Segment (FS). Pointer to more
extra data ('F' comes after 'E').
 G Segment (GS). Pointer to still
more extra data ('G' comes after
'F').
Details about registers
Remember
 R_ _ used in 64 bit MP
 E_ _ used in 32 bit MP
 (E stand for extended)
 Register can access as R_ _ , E_ _ , _ _ , _L ,_ H
Multipurpose or general purpose
register
Accumulator (RAX)
 Used for IO operation, rotate, shift, multiplication
and division
Base index (RBX)
 Hold the offset address of a location In a memory
system
 Also address the memory data
Count Register (CX)
 Used as default counter for various instruction like
repeated string, shift, rotate(CL), loop etc…
 Hold the offset address of memory data
 Address memory data
Data Register (DX)
 Hold the part of the result from a multiplication or
part of the dividend before division.
 Address memory data
Stack Pointer : pointing the top of the stack
in stack segment
Base Pointer: contain the offset address within
data segment
Source index : Used as a pointer to a source in
stream operations
Destination index : used as a pointer to
destination in stream
operations
 All these register also used for based
indexed, register indirect addressing
R8-R15
These register are only found in Pentium 4 and core2 if
64-bit extensions are enables
Used as general purpose register
In most application these registers remain unused
Special Purpose Register
Instruction pointer (IP) :
point to the next
instruction in a program located within
the code segment
Stack Pointer :
pointing the top of the stack
in stack segment to store data
Flag Register
Determine the current state of the process
Modified automatically after M.Operations
Conditional Flag
Carry flag:
indication of overflow condition for
unsigned integer and hold carry
Auxiliary flag :
indication the carry/borrow from
lower nibble to high nibble(D3-D4)
Parity flag : indication of parity of the result
Zero : set if result is zero
Sign flag: In signed magnitude format, if the
result of the operation is negative,
sign flag is set
Control Flag
Control the operation of the execution unit
 Trap flag : if set, then debugging operation
is allow
 Interrupt flag: control the operation of interrupt
request.
note : set by instruction STI
clear by instruction CLI
 Direction flag : used in string operation. if it is set,
string byte is accessed from higher memory
address to lower memory address
Flags for 32,64-bit
 IOPL (IO privilege level) :
used to select the privilege level for IO
devices.
 if the current privilege level is 00 ,IO
execute without hindrance
 if 11 then an interrupt occur and
suspended the execution
 NT (nested task) :
 indicate whether the task is nested with
other or not
RF (resume) :
 resume flag is used with debugging to
control the resumption of execution after
the next instruction
VM (virtual mode) :
 This allow the system program to execute
multiple DOS operation
AC (alignment check) :
 if the word or double word
Is addressed on a non-word or
non-double word boundary
VIF (virtual interrupt flag) :
 copy the interrupt flag bit
(in Pentium 4)
VIP (virtual interrupt pending) :
 Give the information about virtual mode
interrupt. Set if interrupt is pending
ID (identification) :
 The ID flag indicate that Pentium 4 micro-
processor support the CPUID or not.
 The CPUID instruction provides the system
with information about microprocessor such
as its version number and manufacturer
Segment Register
CS (code segment) :
 area of memory that hold the code
(executable program) used by MP
 Have the starting address of the memory
that hold code
 CS:IP used to access the whole 64k
memory of code segment
 SS (stack segment) :
 area of memory used for the stack
 stack is used to store data
 memory 64k can be access by SS:SP
 DS (data segment) :
 area of memory that hold all data
refer by general purpose register
(AX, BX etc. )
64k memory Accessed by using DS and offset
address register
ES (extra segment) :
 additional data segment that is used by
some of the string instructions to hold
destination data
 FS and GS :
 supplemental register used as most
extra segment in 64-bit MP. Window use
these segments for internal operation. But
no definition for their usage is available
REAL MODE MEMORY ADDRESSING
 The only mode available on the 8086-8088.
20 bit address bus  1 MB, 16 bit data bus, 16 bit registers
 80286 and above operate in either the real or
protected mode.
 Real mode operation allows addressing of only the
first 1M byte of memory space—even in Pentium 4
or Core2 microprocessor.
 the first 1M byte of memory is called the real memory,
conventional memory, or DOS memory system
Segment registers hold the base address of where a
particular segment begins in memory. There is the
 code segment (CS)
 data segment (DS)
 stack segment (SS)
 extra segment (ES).
Segments and Offsets
 All real mode memory addresses must consist of a
segment address plus an offset address.
 segment address defines the beginning address of any
64K-byte memory segment
 offset address selects any location within the
64K byte memory segment
Segments and Offsets
16-bit each
Appended 4 bits (0H)
Segment Start Address
in Segment Register
0
Then the Effective memory Address (EA) =
20-bit segment start address +
16-bit offset address
– this shows a memory
segment beginning at
10000H, ending at
location IFFFFH
• 64K bytes in length
– also shows how an offset
address, called a
displacement, of F000H
selects location 1F000H
in the memory
Segments and Offsets
Segments and Offsets
 Once the starting address is known, the ending
address is found by adding FFFFH.
 because a real mode segment of memory is 64K in
length
 The offset address is always added to the segment
starting address to locate the data.
[1000:2000H]
 a segment address of 1000H; an offset of 2000H
Effective Address Calculations
• EA = segment register (SR) x 10H + offset
(a) SR: 1000H
10000 + 0023 = 10023H
(b) SR: AAF0H
AAF00 + 0134 = AB034H
(c) SR: 1200H
12000 + FFF0 = 21FF0H
Default Segment and Offset Registers
 The microprocessor has rules that apply to
segments whenever memory is addressed.
 These define the segment and offset register
combination
[CS:IP]
 The code segment register defines the start of the
code segment.
 The instruction pointer locates the next
instruction within the code segment.
Default Segment and Offset Registers
 Another of the default combinations is the stack.
 stack data are referenced through the stack segment at
the memory location addressed by either the stack pointer
(SP) or the base pointer (BP)
 a memory segment can touch or overlap if 64K bytes of
memory are not required for a segment
– think of segments as
Windows that can be
moved over any area of
memory to access data or
code
– a program can have more
than four or six segments,
• but only access four or six
segments at a time
Default Segment and Offset Registers
00000
Stack
Code
Data
Extra
0FFFF
10000
1FFFF
20000
2FFFF
30000
33FFF
34000
43FFF
44000
48FFF
49000
58FFF
59000
FFFFF
Memory
1 0 0 0 DS
2 0 0 0 CS
3 4 0 0 SS
4 9 0 0 ES
Default Segment and Offset Registers
Code should be limited to
only this portion of the
code segment, to avoid
effects of segment
overlap.
 They can occupy completely separate parts of
memory.
 Multiple segments could even coincide because
there are multiple segment registers, the CPU can
keep track of.
 A program can use, multiple segments at the same
time.
Default Segment and Offset
Registers
 Default segment numbers in:
 CS for program (code)
 SS for stack
 DS for data
 ES for string (destination) data
 Default offset addresses that go with them
Convention Example: EA = CS:[IP]
Segment Start
in Segment register
Offset: Literal
or in a CPU register
TPA
 The Transient Program Area (TPA) holds the DOS
(disk operating system) operating system; other
programs that control the computer system.
 TPA is the first available area of memory above
drivers and other TPA programs
 Area is indicated by a free-pointer maintained by
DOS
 program loading is handled automatically by the
program loader within DOS
The TPA also stores any currently active
or inactive DOS application programs.
Real Mode Addressing Scheme Allows
Relocation
 A relocatable program is one that can be placed
into any area of memory and executed without
change.
 Segment plus offset addressing allows DOS
programs to be relocated in memory.
 This mainly means using relative offsets for data
accesses and jump instructions. If this is easy/possible is
based on the type of architecture, the size of the address
space and the size of the program..
 Relocatable data are data that can be placed in any
area of memory and used without any change to the
program
Real Mode Addressing Scheme Allows
Relocation
 Because memory is addressed within a segment
by an offset address, the memory segment can be
moved to any place in the memory system without
changing any of the offset addresses.
.
 Only the contents of the segment register must be
changed to address the program
in the new area of memory.
 Windows programs are written assuming that the first 2G
of memory are available for code and data.
Internal microprocessor architecture

More Related Content

What's hot

Instruction Set Architecture
Instruction Set ArchitectureInstruction Set Architecture
Instruction Set ArchitectureDilum Bandara
 
8086 modes
8086 modes8086 modes
8086 modesPDFSHARE
 
8257 DMA Controller
8257 DMA Controller8257 DMA Controller
8257 DMA ControllerShivamSood22
 
Computer architecture input output organization
Computer architecture input output organizationComputer architecture input output organization
Computer architecture input output organizationMazin Alwaaly
 
8259 Programmable Interrupt Controller
8259 Programmable Interrupt Controller8259 Programmable Interrupt Controller
8259 Programmable Interrupt Controllerabhikalmegh
 
Input Output Organization
Input Output OrganizationInput Output Organization
Input Output OrganizationKamal Acharya
 
Addressing Modes
Addressing ModesAddressing Modes
Addressing ModesMayank Garg
 
8086 microprocessor-architecture
8086 microprocessor-architecture8086 microprocessor-architecture
8086 microprocessor-architectureprasadpawaskar
 
Addressing modes (detailed data path)
Addressing modes (detailed data path)Addressing modes (detailed data path)
Addressing modes (detailed data path)Mahesh Kumar Attri
 
Associative memory 14208
Associative memory 14208Associative memory 14208
Associative memory 14208Ameer Mehmood
 
8086 pin diagram description
8086 pin diagram description8086 pin diagram description
8086 pin diagram descriptionAkhil Singal
 
Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)Gaditek
 
Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1) Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1) Subhasis Dash
 
80286 microprocessor
80286 microprocessor80286 microprocessor
80286 microprocessorAvin Mathew
 
Introduction to Embedded Systems
Introduction to Embedded SystemsIntroduction to Embedded Systems
Introduction to Embedded SystemsSudhanshu Janwadkar
 

What's hot (20)

Instruction Set Architecture
Instruction Set ArchitectureInstruction Set Architecture
Instruction Set Architecture
 
8255 PPI
8255 PPI8255 PPI
8255 PPI
 
8086 modes
8086 modes8086 modes
8086 modes
 
8257 DMA Controller
8257 DMA Controller8257 DMA Controller
8257 DMA Controller
 
Computer architecture input output organization
Computer architecture input output organizationComputer architecture input output organization
Computer architecture input output organization
 
8259 Programmable Interrupt Controller
8259 Programmable Interrupt Controller8259 Programmable Interrupt Controller
8259 Programmable Interrupt Controller
 
Input Output Organization
Input Output OrganizationInput Output Organization
Input Output Organization
 
Addressing Modes
Addressing ModesAddressing Modes
Addressing Modes
 
8086 microprocessor-architecture
8086 microprocessor-architecture8086 microprocessor-architecture
8086 microprocessor-architecture
 
Addressing modes
Addressing modesAddressing modes
Addressing modes
 
Addressing modes (detailed data path)
Addressing modes (detailed data path)Addressing modes (detailed data path)
Addressing modes (detailed data path)
 
Associative memory 14208
Associative memory 14208Associative memory 14208
Associative memory 14208
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
 
8086 pin diagram description
8086 pin diagram description8086 pin diagram description
8086 pin diagram description
 
Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)
 
Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1) Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1)
 
8086 ppt
8086 ppt8086 ppt
8086 ppt
 
80286 microprocessor
80286 microprocessor80286 microprocessor
80286 microprocessor
 
Introduction to Embedded Systems
Introduction to Embedded SystemsIntroduction to Embedded Systems
Introduction to Embedded Systems
 
Input & Output
Input & OutputInput & Output
Input & Output
 

Viewers also liked

A presentation on Evaluation of Microprocessor
A presentation on Evaluation of MicroprocessorA presentation on Evaluation of Microprocessor
A presentation on Evaluation of MicroprocessorShah Imtiyaj
 
8085 Architecture
8085 Architecture8085 Architecture
8085 Architecturedeval patel
 
8085 Microprocessor Architecture
8085 Microprocessor Architecture8085 Microprocessor Architecture
8085 Microprocessor Architecturedeval patel
 
Hardware implementation of cots avionics system on unmanned
Hardware implementation of cots avionics system on unmannedHardware implementation of cots avionics system on unmanned
Hardware implementation of cots avionics system on unmannedUniversity of Gujrat, Pakistan
 
Multiplication & division instructions microprocessor 8086
Multiplication & division instructions microprocessor 8086Multiplication & division instructions microprocessor 8086
Multiplication & division instructions microprocessor 8086University of Gujrat, Pakistan
 
microprocessor Lec 02 mic
microprocessor Lec 02 micmicroprocessor Lec 02 mic
microprocessor Lec 02 miciqbal ahmad
 
Introduction to random variables
Introduction to random variablesIntroduction to random variables
Introduction to random variablesHadley Wickham
 
The Intel 8086 microprocessor
The Intel 8086 microprocessorThe Intel 8086 microprocessor
The Intel 8086 microprocessorGeorge Thomas
 
The microprocessor and it's architecture
The microprocessor and it's architectureThe microprocessor and it's architecture
The microprocessor and it's architecturesamaa ali
 
Discrete Probability Distributions
Discrete Probability DistributionsDiscrete Probability Distributions
Discrete Probability Distributionsmandalina landy
 

Viewers also liked (20)

A presentation on Evaluation of Microprocessor
A presentation on Evaluation of MicroprocessorA presentation on Evaluation of Microprocessor
A presentation on Evaluation of Microprocessor
 
Chapter2.3 4-mikroprocessor
Chapter2.3 4-mikroprocessorChapter2.3 4-mikroprocessor
Chapter2.3 4-mikroprocessor
 
AVR arduino dasar
AVR arduino dasarAVR arduino dasar
AVR arduino dasar
 
8085 Architecture
8085 Architecture8085 Architecture
8085 Architecture
 
8085 Microprocessor Architecture
8085 Microprocessor Architecture8085 Microprocessor Architecture
8085 Microprocessor Architecture
 
Wireless sensors network in Avionic control system
Wireless sensors network in Avionic control systemWireless sensors network in Avionic control system
Wireless sensors network in Avionic control system
 
Hardware implementation of cots avionics system on unmanned
Hardware implementation of cots avionics system on unmannedHardware implementation of cots avionics system on unmanned
Hardware implementation of cots avionics system on unmanned
 
An autonomous uav with an optical flow sensor
An autonomous uav with an optical flow sensorAn autonomous uav with an optical flow sensor
An autonomous uav with an optical flow sensor
 
Probability And Random Variable Lecture 1
Probability And Random Variable Lecture 1Probability And Random Variable Lecture 1
Probability And Random Variable Lecture 1
 
Dual combustion cycle
Dual combustion cycleDual combustion cycle
Dual combustion cycle
 
Bus interface 8086
Bus interface 8086Bus interface 8086
Bus interface 8086
 
Multiplication & division instructions microprocessor 8086
Multiplication & division instructions microprocessor 8086Multiplication & division instructions microprocessor 8086
Multiplication & division instructions microprocessor 8086
 
microprocessor Lec 02 mic
microprocessor Lec 02 micmicroprocessor Lec 02 mic
microprocessor Lec 02 mic
 
Protected mode memory addressing 8086
Protected mode memory addressing 8086Protected mode memory addressing 8086
Protected mode memory addressing 8086
 
Natural disasters of pakistan
Natural disasters of pakistanNatural disasters of pakistan
Natural disasters of pakistan
 
Diesel cycle
Diesel cycleDiesel cycle
Diesel cycle
 
Introduction to random variables
Introduction to random variablesIntroduction to random variables
Introduction to random variables
 
The Intel 8086 microprocessor
The Intel 8086 microprocessorThe Intel 8086 microprocessor
The Intel 8086 microprocessor
 
The microprocessor and it's architecture
The microprocessor and it's architectureThe microprocessor and it's architecture
The microprocessor and it's architecture
 
Discrete Probability Distributions
Discrete Probability DistributionsDiscrete Probability Distributions
Discrete Probability Distributions
 

Similar to Internal microprocessor architecture

microprocessor_part_3_compressed_1588259301.pdf
microprocessor_part_3_compressed_1588259301.pdfmicroprocessor_part_3_compressed_1588259301.pdf
microprocessor_part_3_compressed_1588259301.pdfssuserd21262
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01jemimajerome
 
26677766 8086-microprocessor-architecture
26677766 8086-microprocessor-architecture26677766 8086-microprocessor-architecture
26677766 8086-microprocessor-architectureSaurabh Jain
 
N_Asm Assembly registers (sol)
N_Asm Assembly registers (sol)N_Asm Assembly registers (sol)
N_Asm Assembly registers (sol)Selomon birhane
 
Presentation on 8086 microprocessor
Presentation on 8086 microprocessorPresentation on 8086 microprocessor
Presentation on 8086 microprocessorDiponkor Bala
 
Assembly programming
Assembly programmingAssembly programming
Assembly programmingOmar Sanchez
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01destaw belay
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01Siva Raman
 
3 organization of intel 8086
3 organization of intel 80863 organization of intel 8086
3 organization of intel 8086ELIMENG
 
8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd year8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd yearBharghavteja1
 
INTEL 8086 MICROPROCESSOR
INTEL 8086 MICROPROCESSORINTEL 8086 MICROPROCESSOR
INTEL 8086 MICROPROCESSORSagar Kuntumal
 

Similar to Internal microprocessor architecture (20)

x86_1.ppt
x86_1.pptx86_1.ppt
x86_1.ppt
 
microprocessor_part_3_compressed_1588259301.pdf
microprocessor_part_3_compressed_1588259301.pdfmicroprocessor_part_3_compressed_1588259301.pdf
microprocessor_part_3_compressed_1588259301.pdf
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01
 
[ASM] Lab2
[ASM] Lab2[ASM] Lab2
[ASM] Lab2
 
26677766 8086-microprocessor-architecture
26677766 8086-microprocessor-architecture26677766 8086-microprocessor-architecture
26677766 8086-microprocessor-architecture
 
intel 8086 introduction
intel 8086 introductionintel 8086 introduction
intel 8086 introduction
 
Advanced micro -processor
Advanced micro -processorAdvanced micro -processor
Advanced micro -processor
 
COA_UNIT_I.pptx
COA_UNIT_I.pptxCOA_UNIT_I.pptx
COA_UNIT_I.pptx
 
N_Asm Assembly registers (sol)
N_Asm Assembly registers (sol)N_Asm Assembly registers (sol)
N_Asm Assembly registers (sol)
 
Presentation on 8086 microprocessor
Presentation on 8086 microprocessorPresentation on 8086 microprocessor
Presentation on 8086 microprocessor
 
Assembly programming
Assembly programmingAssembly programming
Assembly programming
 
Register & Memory
Register & MemoryRegister & Memory
Register & Memory
 
Chapter 2
Chapter 2Chapter 2
Chapter 2
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01
 
8086
8086 8086
8086
 
3 organization of intel 8086
3 organization of intel 80863 organization of intel 8086
3 organization of intel 8086
 
8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd year8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd year
 
INTEL 8086 MICROPROCESSOR
INTEL 8086 MICROPROCESSORINTEL 8086 MICROPROCESSOR
INTEL 8086 MICROPROCESSOR
 
Arch 8086
Arch 8086Arch 8086
Arch 8086
 

More from University of Gujrat, Pakistan

Constitutional development of pakistan since 1947 to thereayf
Constitutional development of pakistan since 1947 to thereayfConstitutional development of pakistan since 1947 to thereayf
Constitutional development of pakistan since 1947 to thereayfUniversity of Gujrat, Pakistan
 
Passive Thermal management for avionics in high temperature environment
Passive Thermal management for avionics in high temperature environmentPassive Thermal management for avionics in high temperature environment
Passive Thermal management for avionics in high temperature environmentUniversity of Gujrat, Pakistan
 
Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...
Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...
Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...University of Gujrat, Pakistan
 
A wireless sensors network in Aircraft Control Systems
A wireless sensors network in Aircraft Control SystemsA wireless sensors network in Aircraft Control Systems
A wireless sensors network in Aircraft Control SystemsUniversity of Gujrat, Pakistan
 
Towards Automating Interface Control Documents Elaboration and Management
Towards Automating Interface Control Documents Elaboration and ManagementTowards Automating Interface Control Documents Elaboration and Management
Towards Automating Interface Control Documents Elaboration and ManagementUniversity of Gujrat, Pakistan
 
APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...
APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...
APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...University of Gujrat, Pakistan
 
Rapid Start-Up / Restart Avionics Provide Robust Fault Tolerance with SCp (S...
Rapid Start-Up / Restart Avionics Provide Robust Fault  Tolerance with SCp (S...Rapid Start-Up / Restart Avionics Provide Robust Fault  Tolerance with SCp (S...
Rapid Start-Up / Restart Avionics Provide Robust Fault Tolerance with SCp (S...University of Gujrat, Pakistan
 
Improving Avionics using aircraft Information Sharing Network(Research Paper)
Improving Avionics using aircraft Information Sharing Network(Research Paper)Improving Avionics using aircraft Information Sharing Network(Research Paper)
Improving Avionics using aircraft Information Sharing Network(Research Paper)University of Gujrat, Pakistan
 

More from University of Gujrat, Pakistan (20)

Carnot cycle
Carnot cycleCarnot cycle
Carnot cycle
 
Brayton cycle
Brayton cycleBrayton cycle
Brayton cycle
 
Constitutional development of pakistan since 1947 to thereayf
Constitutional development of pakistan since 1947 to thereayfConstitutional development of pakistan since 1947 to thereayf
Constitutional development of pakistan since 1947 to thereayf
 
Essay writing
Essay writingEssay writing
Essay writing
 
Letter writing (Communication Skills)
Letter writing (Communication Skills)Letter writing (Communication Skills)
Letter writing (Communication Skills)
 
Architecture of high end processors
Architecture of high end processorsArchitecture of high end processors
Architecture of high end processors
 
Architecture of pentium family
Architecture of pentium familyArchitecture of pentium family
Architecture of pentium family
 
Passive Thermal management for avionics in high temperature environment
Passive Thermal management for avionics in high temperature environmentPassive Thermal management for avionics in high temperature environment
Passive Thermal management for avionics in high temperature environment
 
Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...
Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...
Future Integrated Systems Concept for Preventing Aircraft Loss-of-Control (L...
 
A wireless sensors network in Aircraft Control Systems
A wireless sensors network in Aircraft Control SystemsA wireless sensors network in Aircraft Control Systems
A wireless sensors network in Aircraft Control Systems
 
Helicopter Automation Using Low Cost Sensors
Helicopter Automation Using Low Cost SensorsHelicopter Automation Using Low Cost Sensors
Helicopter Automation Using Low Cost Sensors
 
Towards Automating Interface Control Documents Elaboration and Management
Towards Automating Interface Control Documents Elaboration and ManagementTowards Automating Interface Control Documents Elaboration and Management
Towards Automating Interface Control Documents Elaboration and Management
 
APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...
APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...
APPLICATION OF WIRELESS SENSOR NETWORKS TO AIRCRAFT CONTROL AND HEALTH MANAGE...
 
AVIONIC CONTROL SYSTEMS FOR EDUCATION & DEVELOPMENT
AVIONIC CONTROL SYSTEMS FOR EDUCATION & DEVELOPMENTAVIONIC CONTROL SYSTEMS FOR EDUCATION & DEVELOPMENT
AVIONIC CONTROL SYSTEMS FOR EDUCATION & DEVELOPMENT
 
Flight control and system 100
Flight control and system 100Flight control and system 100
Flight control and system 100
 
Helicopter automation using low cost sensors
Helicopter automation using low cost sensorsHelicopter automation using low cost sensors
Helicopter automation using low cost sensors
 
Rapid Start-Up / Restart Avionics Provide Robust Fault Tolerance with SCp (S...
Rapid Start-Up / Restart Avionics Provide Robust Fault  Tolerance with SCp (S...Rapid Start-Up / Restart Avionics Provide Robust Fault  Tolerance with SCp (S...
Rapid Start-Up / Restart Avionics Provide Robust Fault Tolerance with SCp (S...
 
Improving Avionics using aircraft Information Sharing Network(Research Paper)
Improving Avionics using aircraft Information Sharing Network(Research Paper)Improving Avionics using aircraft Information Sharing Network(Research Paper)
Improving Avionics using aircraft Information Sharing Network(Research Paper)
 
Probability And Random Variable Lecture (Lec10)
Probability And Random Variable Lecture (Lec10)Probability And Random Variable Lecture (Lec10)
Probability And Random Variable Lecture (Lec10)
 
Probability And Random Variable Lecture(Lec9)
Probability And Random Variable Lecture(Lec9)Probability And Random Variable Lecture(Lec9)
Probability And Random Variable Lecture(Lec9)
 

Recently uploaded

pipeline in computer architecture design
pipeline in computer architecture  designpipeline in computer architecture  design
pipeline in computer architecture designssuser87fa0c1
 
IVE Industry Focused Event - Defence Sector 2024
IVE Industry Focused Event - Defence Sector 2024IVE Industry Focused Event - Defence Sector 2024
IVE Industry Focused Event - Defence Sector 2024Mark Billinghurst
 
Work Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvvWork Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvvLewisJB
 
Application of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptxApplication of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptx959SahilShah
 
Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.eptoze12
 
EduAI - E learning Platform integrated with AI
EduAI - E learning Platform integrated with AIEduAI - E learning Platform integrated with AI
EduAI - E learning Platform integrated with AIkoyaldeepu123
 
main PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfidmain PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfidNikhilNagaraju
 
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETEINFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETEroselinkalist12
 
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdfCCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdfAsst.prof M.Gokilavani
 
What are the advantages and disadvantages of membrane structures.pptx
What are the advantages and disadvantages of membrane structures.pptxWhat are the advantages and disadvantages of membrane structures.pptx
What are the advantages and disadvantages of membrane structures.pptxwendy cai
 
An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...Chandu841456
 
Introduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptxIntroduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptxk795866
 
Biology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptxBiology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptxDeepakSakkari2
 
Concrete Mix Design - IS 10262-2019 - .pptx
Concrete Mix Design - IS 10262-2019 - .pptxConcrete Mix Design - IS 10262-2019 - .pptx
Concrete Mix Design - IS 10262-2019 - .pptxKartikeyaDwivedi3
 
Call Girls Delhi {Jodhpur} 9711199012 high profile service
Call Girls Delhi {Jodhpur} 9711199012 high profile serviceCall Girls Delhi {Jodhpur} 9711199012 high profile service
Call Girls Delhi {Jodhpur} 9711199012 high profile servicerehmti665
 
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...VICTOR MAESTRE RAMIREZ
 

Recently uploaded (20)

pipeline in computer architecture design
pipeline in computer architecture  designpipeline in computer architecture  design
pipeline in computer architecture design
 
IVE Industry Focused Event - Defence Sector 2024
IVE Industry Focused Event - Defence Sector 2024IVE Industry Focused Event - Defence Sector 2024
IVE Industry Focused Event - Defence Sector 2024
 
Work Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvvWork Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvv
 
Application of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptxApplication of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptx
 
Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.
 
EduAI - E learning Platform integrated with AI
EduAI - E learning Platform integrated with AIEduAI - E learning Platform integrated with AI
EduAI - E learning Platform integrated with AI
 
main PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfidmain PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfid
 
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETEINFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
 
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
 
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdfCCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
 
What are the advantages and disadvantages of membrane structures.pptx
What are the advantages and disadvantages of membrane structures.pptxWhat are the advantages and disadvantages of membrane structures.pptx
What are the advantages and disadvantages of membrane structures.pptx
 
An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...
 
🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...
🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...
🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...
 
young call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Service
young call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Serviceyoung call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Service
young call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Service
 
Introduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptxIntroduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptx
 
Biology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptxBiology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptx
 
Concrete Mix Design - IS 10262-2019 - .pptx
Concrete Mix Design - IS 10262-2019 - .pptxConcrete Mix Design - IS 10262-2019 - .pptx
Concrete Mix Design - IS 10262-2019 - .pptx
 
young call girls in Green Park🔝 9953056974 🔝 escort Service
young call girls in Green Park🔝 9953056974 🔝 escort Serviceyoung call girls in Green Park🔝 9953056974 🔝 escort Service
young call girls in Green Park🔝 9953056974 🔝 escort Service
 
Call Girls Delhi {Jodhpur} 9711199012 high profile service
Call Girls Delhi {Jodhpur} 9711199012 high profile serviceCall Girls Delhi {Jodhpur} 9711199012 high profile service
Call Girls Delhi {Jodhpur} 9711199012 high profile service
 
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
 

Internal microprocessor architecture

  • 1.
  • 2. Group Members  12063122-011 ( M.Noman )  12063122-017 ( Hafiz Hamid )  12063122-029 ( Salah Uddin Ayubi )  12063122-037 ( Mubashar Naeem )  12063122-023 ( Safi ur rehman Tabasum )  University Of Gujrat (Pakistan)
  • 4. Microprocessor’s type Internal structure of microprocessor should be known Single core 1. single task at any time 2.access whole memory at the same time by any program Dual core 1.multiple task at any time 2.access specific memory by any task
  • 5. Programing model Program visible : 8086,8088 Registers are used directly during programing Program invisible : 80286 and above 1. Registers are not accessible directly during programing 2. Can be used indirectly
  • 6. Programing model Program visible : 8086,8088 Registers are used directly during programing Program invisible : 80286 and above 1. Registers are not accessible directly during programing 2. Can be used indirectly
  • 7.
  • 9. cont.….  We can’t access these register with the instruction used to access general purpose register AX,BX etc….  To access the low order byte of R8 use R8B  To access the low order word of R10 use R10W
  • 12. Special purpose flag  The 6 Segment Registers are:  Stack Segment (SS). Pointer to the stack.  Code Segment (CS). Pointer to the code.  Data Segment (DS). Pointer to the data.  Extra Segment (ES). Pointer to extra data ('E' stands for 'Extra').  F Segment (FS). Pointer to more extra data ('F' comes after 'E').  G Segment (GS). Pointer to still more extra data ('G' comes after 'F').
  • 14. Remember  R_ _ used in 64 bit MP  E_ _ used in 32 bit MP  (E stand for extended)  Register can access as R_ _ , E_ _ , _ _ , _L ,_ H
  • 15. Multipurpose or general purpose register
  • 16. Accumulator (RAX)  Used for IO operation, rotate, shift, multiplication and division
  • 17. Base index (RBX)  Hold the offset address of a location In a memory system  Also address the memory data
  • 18. Count Register (CX)  Used as default counter for various instruction like repeated string, shift, rotate(CL), loop etc…  Hold the offset address of memory data  Address memory data
  • 19. Data Register (DX)  Hold the part of the result from a multiplication or part of the dividend before division.  Address memory data
  • 20. Stack Pointer : pointing the top of the stack in stack segment Base Pointer: contain the offset address within data segment Source index : Used as a pointer to a source in stream operations Destination index : used as a pointer to destination in stream operations  All these register also used for based indexed, register indirect addressing
  • 21. R8-R15 These register are only found in Pentium 4 and core2 if 64-bit extensions are enables Used as general purpose register In most application these registers remain unused
  • 22. Special Purpose Register Instruction pointer (IP) : point to the next instruction in a program located within the code segment Stack Pointer : pointing the top of the stack in stack segment to store data
  • 23. Flag Register Determine the current state of the process Modified automatically after M.Operations Conditional Flag Carry flag: indication of overflow condition for unsigned integer and hold carry Auxiliary flag : indication the carry/borrow from lower nibble to high nibble(D3-D4)
  • 24. Parity flag : indication of parity of the result Zero : set if result is zero Sign flag: In signed magnitude format, if the result of the operation is negative, sign flag is set
  • 25. Control Flag Control the operation of the execution unit  Trap flag : if set, then debugging operation is allow  Interrupt flag: control the operation of interrupt request. note : set by instruction STI clear by instruction CLI  Direction flag : used in string operation. if it is set, string byte is accessed from higher memory address to lower memory address
  • 26. Flags for 32,64-bit  IOPL (IO privilege level) : used to select the privilege level for IO devices.  if the current privilege level is 00 ,IO execute without hindrance  if 11 then an interrupt occur and suspended the execution
  • 27.  NT (nested task) :  indicate whether the task is nested with other or not RF (resume) :  resume flag is used with debugging to control the resumption of execution after the next instruction
  • 28. VM (virtual mode) :  This allow the system program to execute multiple DOS operation AC (alignment check) :  if the word or double word Is addressed on a non-word or non-double word boundary VIF (virtual interrupt flag) :  copy the interrupt flag bit (in Pentium 4)
  • 29. VIP (virtual interrupt pending) :  Give the information about virtual mode interrupt. Set if interrupt is pending ID (identification) :  The ID flag indicate that Pentium 4 micro- processor support the CPUID or not.  The CPUID instruction provides the system with information about microprocessor such as its version number and manufacturer
  • 30. Segment Register CS (code segment) :  area of memory that hold the code (executable program) used by MP  Have the starting address of the memory that hold code  CS:IP used to access the whole 64k memory of code segment
  • 31.  SS (stack segment) :  area of memory used for the stack  stack is used to store data  memory 64k can be access by SS:SP  DS (data segment) :  area of memory that hold all data refer by general purpose register (AX, BX etc. ) 64k memory Accessed by using DS and offset address register
  • 32. ES (extra segment) :  additional data segment that is used by some of the string instructions to hold destination data  FS and GS :  supplemental register used as most extra segment in 64-bit MP. Window use these segments for internal operation. But no definition for their usage is available
  • 33. REAL MODE MEMORY ADDRESSING  The only mode available on the 8086-8088. 20 bit address bus  1 MB, 16 bit data bus, 16 bit registers  80286 and above operate in either the real or protected mode.  Real mode operation allows addressing of only the first 1M byte of memory space—even in Pentium 4 or Core2 microprocessor.  the first 1M byte of memory is called the real memory, conventional memory, or DOS memory system
  • 34. Segment registers hold the base address of where a particular segment begins in memory. There is the  code segment (CS)  data segment (DS)  stack segment (SS)  extra segment (ES).
  • 35. Segments and Offsets  All real mode memory addresses must consist of a segment address plus an offset address.  segment address defines the beginning address of any 64K-byte memory segment  offset address selects any location within the 64K byte memory segment
  • 36. Segments and Offsets 16-bit each Appended 4 bits (0H) Segment Start Address in Segment Register 0 Then the Effective memory Address (EA) = 20-bit segment start address + 16-bit offset address
  • 37. – this shows a memory segment beginning at 10000H, ending at location IFFFFH • 64K bytes in length – also shows how an offset address, called a displacement, of F000H selects location 1F000H in the memory Segments and Offsets
  • 38. Segments and Offsets  Once the starting address is known, the ending address is found by adding FFFFH.  because a real mode segment of memory is 64K in length  The offset address is always added to the segment starting address to locate the data. [1000:2000H]  a segment address of 1000H; an offset of 2000H
  • 39. Effective Address Calculations • EA = segment register (SR) x 10H + offset (a) SR: 1000H 10000 + 0023 = 10023H (b) SR: AAF0H AAF00 + 0134 = AB034H (c) SR: 1200H 12000 + FFF0 = 21FF0H
  • 40.
  • 41. Default Segment and Offset Registers  The microprocessor has rules that apply to segments whenever memory is addressed.  These define the segment and offset register combination [CS:IP]  The code segment register defines the start of the code segment.  The instruction pointer locates the next instruction within the code segment.
  • 42. Default Segment and Offset Registers  Another of the default combinations is the stack.  stack data are referenced through the stack segment at the memory location addressed by either the stack pointer (SP) or the base pointer (BP)  a memory segment can touch or overlap if 64K bytes of memory are not required for a segment
  • 43. – think of segments as Windows that can be moved over any area of memory to access data or code – a program can have more than four or six segments, • but only access four or six segments at a time Default Segment and Offset Registers 00000 Stack Code Data Extra 0FFFF 10000 1FFFF 20000 2FFFF 30000 33FFF 34000 43FFF 44000 48FFF 49000 58FFF 59000 FFFFF Memory 1 0 0 0 DS 2 0 0 0 CS 3 4 0 0 SS 4 9 0 0 ES
  • 44. Default Segment and Offset Registers Code should be limited to only this portion of the code segment, to avoid effects of segment overlap.
  • 45.  They can occupy completely separate parts of memory.  Multiple segments could even coincide because there are multiple segment registers, the CPU can keep track of.  A program can use, multiple segments at the same time.
  • 46.
  • 47. Default Segment and Offset Registers  Default segment numbers in:  CS for program (code)  SS for stack  DS for data  ES for string (destination) data  Default offset addresses that go with them Convention Example: EA = CS:[IP] Segment Start in Segment register Offset: Literal or in a CPU register
  • 48.
  • 49. TPA  The Transient Program Area (TPA) holds the DOS (disk operating system) operating system; other programs that control the computer system.  TPA is the first available area of memory above drivers and other TPA programs  Area is indicated by a free-pointer maintained by DOS  program loading is handled automatically by the program loader within DOS
  • 50. The TPA also stores any currently active or inactive DOS application programs.
  • 51. Real Mode Addressing Scheme Allows Relocation  A relocatable program is one that can be placed into any area of memory and executed without change.  Segment plus offset addressing allows DOS programs to be relocated in memory.
  • 52.  This mainly means using relative offsets for data accesses and jump instructions. If this is easy/possible is based on the type of architecture, the size of the address space and the size of the program..  Relocatable data are data that can be placed in any area of memory and used without any change to the program
  • 53. Real Mode Addressing Scheme Allows Relocation  Because memory is addressed within a segment by an offset address, the memory segment can be moved to any place in the memory system without changing any of the offset addresses. .
  • 54.  Only the contents of the segment register must be changed to address the program in the new area of memory.  Windows programs are written assuming that the first 2G of memory are available for code and data.