Computer architecture course------> protected mode and paging

1. Protected Addressing Mode
and Paging
Presented by Rauf

2. Protected Addressing Mode
• It allows system software to use features such as virtual memory, paging, and multi-
tasking designed to increase an operating system's control over application software.
Also real mode code is never in 32 bits whereas protected mode code can be 16 bits
or 32 bits. Every x86 CPU starts in real mode. Protected mode starts after OS sets up
several descriptor tables and enables the Protection Enable (PE) bit in the control
register 0.
• Allows access to data and programs located within and above the first 1M byte of
memory.
• Addressing this extended section of the memory system requires a change to the
segment plus an offset addressing scheme used with real mode memory addressing.
• Protected mode is where Windows operates.
• Used by Windows NT, 2000, XP, Linux

3. Logical to Physical Address
Translation in Pentium
• CPU generates Logical address and it is given to SEGMENTATION UNIT
• SU produces Linear address and it is given to PAGING UNIT
• PU converts linear address into Physical and stores it in the main memory
• If no paging is used Linear address = Physical address

4. Intel Pentium Segmentation
In place of a segment address, the segment
register contains a selector that selects a
descriptor from a descriptor table.
The descriptor describes the memory
segment’s location, length, and access rights.
- it selects one of 8192 descriptors from one of two tables of
descriptors
Descriptors are placed in descriptor tables in
main memory
Protection is provided by restricting access to
memory segments through:
- Privilege levels,
- and Access rights
Logical address
32-bit16-bit
Segment register Offset

5. 16 bits segment register = 13 bit descriptor selector + 1 bit descriptor table
selector + 2-bit requested privilege

6. Descriptor Tables (Segment Table)
• each descriptor is 8 bytes in length
• Each table holds 8192 descriptors
• Table can range in size from 8 bytes to 64KB (8192 descriptor requires
8*8192=64kb of memory) (213 x 23) (3 bits are implied as descriptor size is
fixed)
• Global descriptors contain segment definitions that apply to all
programs.
• Local descriptors are usually unique to an application.
– a global descriptor might be called a system descriptor, and local
descriptor an application descriptor

7. • Limit – specifies the length
of the segment
• Base– specifies start
address of the segment
• Access rights– controls access to
the segment
-Defines how the segment will function

8. Base
Address
[B0-B15]
Limit
[L0-L15]
Base
Address
[B24-B31]
Flag
Limit
[L16-L19]
Access Rights
Base
Address
[B16-B23]
15 01631
32394047485152555663
2 bytes 2 bytes
2 bytes2 bytes

9. DPL will be compared with
the request privilege level
(RPL) in the segment
register
specifying this segment.
Allow access to the
segment only if RPL has
higher or equal privilege
to the DPL, subject to the
state of C bit if applicable
TYPE of segment

10. =1 32-bit
=0 16-bit
AVL=1: segment is available (e.g. not
being accessed by another thread)
AVL=0: segment is NOT available

11. Descriptor Tables (Segment Table)
• The G, or granularity bit allows a segment length of 4K to 4G bytes in steps of
4K bytes.
– G = 0, the limit is from 1 to 1MB in length
– G = 1, the limit is multiplied by 4K bytes (appended with 000H). So segment
length is 4K to 4G bytes in steps of 4K bytes
– G=granularity bit: • G=0: limit is 1B-1MB (00000h to
FFFFFh) • G=1: limit is multiplied by 4K (00000xxxh to
FFFFFxxxh = 4KB-4GB)
• With limit specifying 1 MB segments and G=1 (i.e. 4K multiplier): Max Segment size = 4K
x 1 MB = 4 GB

12. Examples
00H 00H
01H
00H
0H
FFH FFH
7
5
3
1
6
4
2
0
0 D O
A
V
Start = 01000000H
Limit = 0FFFFH
End = 0100FFFFH

13. Examples
00H 00H
00H
28H
0H
00H 10H
7
5
3
1
6
4
2
0
1 D O
A
V
Start = 00280000H
Limit =
End =
00010H000
00390000H

14. Requested Privilege Level
Highest
Lowest
Hardware
Privilege
ComparatorDPL
(in descriptor)
RPL
(In Seg Reg)
RPL  DPL
Allow
Access
to segment
00: Highest Privilege
01
10
11: Lowest Privilege

16. Protected Mode: Segmentation Examples
CPU 1007H 00000088H
CS EBX
0001 0000 0000 0111
index
RPLTI
00019212000000FF 00002510000001FF
…
…
…
…
LDT GDT

17. Protected Mode: Segmentation Examples
CPU 1007H 00000088H
CS EBX
0001 0000 0000 0111
index
RPLTI
00019212000000FF
…
…
LDT
< +
Trap: addressing error
limit base
yes
no
Physical memory
00120000
00120088
00000000
FFFFFFFF
Access rights byte=92h
1001 0010
P=1: all is valid
DPL=00; you better have high privileges!
S=1: this is code or data (not a system routine)
E=0: compliments S, it is data (not code)
ED=0: it is data not stack data, so increment data
pointers upward when applicable
W=1: Data may be written
A=0: The segment is free, go for it!
Data Segment

18. Protected Mode: Segmentation Examples
Logical address = 1234:11223344
Segment selector = 1234
Base address = 00000000 (from descriptor table)
Then linear address = base address + offset = 0 + 11223344 = 11223344

19. Paging
• Paging is used for virtual memory multitasking operating system.
• Through paging to the hard disk drive and paging to the memory
through the memory paging unit, any Windows application can be
executed.
• In the paging memory-management scheme, the operating system
retrieves data from secondary storage in same-size blocks called
pages.
• The Paging unit organizes the physical memory in terms of pages of
4kbytes size each.
• Paging unit works under the control of the segmentation unit, i.e.
each segment is further divided into pages.

21. The paging unit is controlled by the microprocessors control
registers:

22. • CR4, controls extensions to the basic architecture provided in the Pentium
or newer microprocessor.
• CR0 contains the system control flags.
• CR3 contains the page directory base or root address.
• CR2 contains the Page Fault linear address code
• Page Fault interrupt signal enable.
• (PG) bit, enables paging when placed at a logic 1 level.
- If PG=1, then linear address transferred into physical address
- If PG=0, then linear address is physical address
• The PCD and PWT bits, control the operation of the PCD and PWT pins on
the microprocessor.
• The page directory base address, locates the directory for the page
translation unit, contains 1024 directory entries of 4 bytes.

23. The format for the linear address

24. • Only one page directory in the system.
• The page directory contains 1024 doubleword
addresses that locate up to 1024 page tables.
• Page directory and each page table are 4K bytes in
length
• Each entry in the page directory corresponds to 4M
bytes of physical memory.
• Each entry in the page table repages 4K bytes of
physical memory.

25. END

26. BLOCK DIAGRAM OF PAGING MECHANISM WITH 4KB EACH PAGE
offset
01112212231
Page Table entryDirectory
Page Directory
entry(PDE) table
1024 PDEs
PDE
Page Table
1024 PTEs
PTE
Physical Page
4KB
Physical Address
1210
10
CR3(PDBAR)
Page table
base address
20bit
Page base address 20bit
Page directory
table base address
32bit
32bit
32bit
Linear address
PDBAR-Page Directory Base Address Register
PDE--Page directory entry ,32 bits
PTE --Page Table entry,32 bits
CR3 -- control register3
(1024x4B)=4KB Page Directory
(1024x4B) =4KB each Page Table
1024x4KB=4MB for all Page Tables
4MB+4KB for page directory and page tables
Each of PDE and PTE is 32bits control structure that consist of:
base address that indicates in PDE start address ofpage table,in
PTE start address of physical page
and any flags: P(present), A(accessed), O(over page from RAM to
HD), PS(Page Size) , PSE(Page size Extention)