Pravesh Kumar is a VLSI verification engineer with over 2 years of experience in ASIC design and verification. He has worked on various projects involving AMBA protocols, coverage-driven verification, SystemVerilog, and UVM. His skills include Verilog, SystemVerilog, UVM methodology, functional coverage, and debugging. He holds a Bachelor of Technology degree in Electronics and Communication.

1. CURRICULUM VITAE
PRAVESH KUMAR
Mobile: +91 8901575190 E-mail:pravesh.pkr@gmail.com
CAREER OBJECTIVE
To take up an inspiring career growth with loyalty, innovation and persistence, and translate my
experiences, knowledge, skills into values for the organization.
PROFESSIONAL SUMMARY
 1+ year of experience in VLSI industry + 6 months professional training in VLSI.
 2 years of experience in SV language and UVM methodology.
 Good knowledge of RAL in both UVM and VMM.
 Strong knowledge of AMBA protocols (AXI, AHB, APB).
 Hand-on experience in coverage driven verification (functional and code coverage).
 Proficiency with VCS, Questa, Xilinx ISE tools.
 Having good experience in verification debug feature at IP level.
 Good knowledge of ASIC design flow.
 Good analytical skills to debug the syntactical and logical error.
PROFESSIONAL WORK EXPERIENCE
MediaTek pvt. Ltd., R&D centre, Bangalore
Job role : Asic verification Intern, from April 27,2015 to till date.
Maven Silicon pvt. Ltd., Bangalore
Job role : Project Intern, from January,2015 to april,2015 .
PROFESSIONAL QUALIFICATIONS
 Internship on Advanced VLSI Design and Verification
Maven Silicon VLSI Design and Training Center, Bangalore in March,2015
 Maven Silicon Certified Advanced VLSI Design and Verification course
Maven Silicon VLSI Design and Training Center, Bangalore in January,2015
 Six weeks Internship on VLSI design and FPGA implementation
CDAC, Mohali, Punjab in June,2013
 Bachelor of technology in Electronics and communication
Lovely Professional University, Punjab with 70.74% in 2014.
 HSC with 72.4 % in 2010.
 SSC with 83% in 2008.

2. TECHNICAL SKILLS
Name Description
HDL Verilog, VHDL
HVL System Verilog
EDA Tool Synopsis VCS and Verdi, QuestaSim, Xilinx ISE
TB Methodology UVM(RAL also), VMM(RAL also)
Scripting language/
language
Perl (tk also), C++
Operating system Linux, windows
Protocols AMBA- AXI, AHB, APB
Verification
Methodology
Coverage Driven Verification, Assertion Based Verification - SVA
Domain ASIC/FPGA front-end Design and Verification
PROJECTS
 Common Bus IP (CBIP)
Oraganisation : MediaTek
Tools/Methodology : VCS, Verdi, DVE, UVM, VMM
All the Common Bus IP follow a generic UVM environment structure which based on
infraTBA. CBIP is a bridge between two domains sync/async or a protocol to other
protocol.
1. IP name : CBIP_SMI_SUB_COMMON
CBIP_SMI_SUB_COMMON have multiple axi master (2 to 8) and a axi slave i.e having
seven different configuration (2x1, 3x1, 4x1, 5x1, 6x1, 7x1, 8x1) and having many
registers. It is used for pre-merge arbiter in MMSys, priority arbiter for non-
MM_sub_sys usage. APB is used for reading and writing of registers.
Contribution:
 Conversion of environment from VMM to UVM.
 Generated UVM environment from scratch using infratba for all configurations.
 Successful conversion of RAL and verified all registers using inbuild and user
build tests for all seven configurations.
 Completed axi traffic for a random test and working on user build tests.
 Designed and maintained the project related documents.
2. IP name : CBIP_AXI_SLPPROTECT_CTRL
Cbip_slpprotect_ctrl is used to reduce the power of axi. By monitoring handshake
signals it determine when axi bus is in idle state. It also protects the safety of axi bus
signals to make sure transaction are unbroken and prevent the glitch from axi master
spreading in axi bus.
Contribution:
 Debugging the VIP for new VCS version.
 Updated script for running the tests.
 Assertion based verification using VCS dve tool.
 Regressions and coverage based verification.
 Documentation for VIP and every change and results.
3. IP name : CBIP_AXI_UPSIZER

3. Upsizer is used to transfer axi signals from small data width to large data width. The axi
upsizer converts 2m
bits axi bus transactions into 2m+1
bits axi transactions. It support
different data size transfers 32 to 64, 64 to 128, 128 to 256.
Contribution:
 Debug warning from the logs.
 Functional and code coverage using VCS, dve tools by updating the el file.
4. IP name : CBIP_AXI_DOWNSIZER
Downsizer is used to transfer axi signals from large data width to small data width. The
axi downsizer converts 2m+1
bits axi bus transactions into 2m
bits axi transactions. It
support different data size transfers 64 to 32, 128 to 64,256 to 128.
Contribution:
 Debug warning from the logs.
 Written logic for flush for pipe and non-pipe (code of QOS signal).
 Functional and code coverage using VCS dve tool by updating the el file.
5. IP name : CBIP_CABGEN
Cabgen is an AXI interconnect IP. It provides two dimension freedom of configuration
one for component combination and another for component option. Cabgen have six
configurations.
Contribution:
 Added covergroups and coverpoints for non – axi signals.
 Functional coverage is made to 100%.
 OTHER PROECTS
Organization : Maven silicon
Tools/Methodology : QuestaSim, Xilinx ISE, UVM
1. AXI4 Protocol Verification
The AMBA AXI protocol is targeted at high-performance, high-frequency system and
includes a number of features that make it suitable for a high-speed submicron
interconnects.
Responsibilities:
 Architected the class based verification environment in UVM.
 Verified the protocol with single master single slave environment.
 Generated functional coverage for verification sign-off.
2. AHB2APB Bridge IP Core Verification
The AHB to APB bridge is an AHB slave which works as an interface between the high
speed AHB and the low performance APB buses.
Responsibilities:
 Architected the class based verification environment in UVM.
 Verified the RTL module with single master and single slave.
 Generated functional for the RTL verification.

4. 3. UART- IP Core – design
The UART IP core provides serial communication capabilities, which allow
communication with modem or other external devices.
Responsibilities:
 Architected the design.
 Implemented and Verified RTL using Verilog HDL.
 Synthesized the design.
4. Router – RTL design and Verification
Description: The router accepts the packet on input port and based on the destination
address it routes toone of the client network among client-1,client-2 and client-3
respectively.
Responsibilities:
 Architected the design , Implemented RTL using Verilog HDL.
 Verified the RTL model using Verilog and UVM.
 Generated functional and code coverage for the RTL verification.
 Synthesized the design.
ACHIEVEMENTS
 Captain of school cricket team -Under fourteen, 2004 and 2005.
- Under sixteen, 2007.
 Two silver medals in 100m race at school, 2003 and 2006.
HOBBIES
 Reading books.
 Watching videos.
 Writing diary.
PERSONAL INFORMATION
 Gender: Male
 Date of Birth: 05-11-1991
 Language: Hindi, English
I hereby declare that the information provided here is complete and correct to the best of my
knowledge and belief.
Place: Bangalore
Date: Pravesh Kumar