Lokesh Mistry is seeking a position as an ASIC Design and Verification Engineer. He has 6 months of training and 2 months of internship experience in ASIC verification using UVM and SystemVerilog, including testbench development, test planning, and functional coverage. His skills include SystemVerilog, UVM methodology, Perl scripting, and EDA tools like Questasim and RiveraPro. He has experience verifying AXI-4 BFM, designing an AMBA AHB-APB bridge, and verifying SPI protocols by developing UVM environments and writing test cases. He holds a B.E. in electronics engineering and has received honors in various academic exams.