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![GFP client data frame
• Composed of a frame header and payload
• Core header intended for data link management
– payload length indicator (PLI, 2 octets), HEC (CRC-16, 2 octets)
• Payload field divided into payload header, payload and optional FCS
(CRC-32) sub-fields
• Payload header includes:
– payload type (2 octets) and type HEC (2 octets) sub-fields
– optional 0 - 60 octets of extension header
• Payload:
– variable length (0 - 65 535 octets, including payload header and FCS) for
frame mapping mode (GFP-F) - frame multiplexing
– fixed size Nx[536, 520] for transparent mapping mode (GFP-T) - no frame
multiplexing
© P. Raatikainen
Switching Technology / 2005
L2 - 61
GFP frame structure
Payload length indicator
Core
header
Core HEC
PFI
EXI
UPI
Type HEC
CID
Payload header
Payload
area
PTI
Payload type
0 – 60 bytes
extension header
(optional)
Spare
Extension HEC MSB
Extension HEC LSB
Payload
[N x 536, 520 bytes
or variable length
packet]
Payload FCS
CID - Channel identifier
FCS - Frame Check Sequence
EXI - Extension Header Identifier
HEC - Header Error Check
PFI - Payload FCS Indicator
PTI - Payload Type Indicator
UPI - User payload Identifier
Source: IEEE Communications Magazine, May 2002
© P. Raatikainen
Switching Technology / 2005
L2 - 62](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-57-2048.jpg)
![Throughput
• Throughput gives forwarding/switching speed/efficiency of a
switch fabric
• It is measured in bits/s, octets/s, cells/s, packet/s, etc.
• Quite often throughput is given in the range (0 ... 1.0], i.e. the
obtained forwarding speed is normalized to the theoretical
maximum throughput
© P. Raatikainen
Switching Technology / 2003
3 - 11
Switch fabrics
•
•
•
•
•
•
Basic concepts
Time and space switching
Two stage switches
Three stage switches
Cost criteria
Multi-stage switches and path search
© P. Raatikainen
Switching Technology / 2003
3 - 12
6](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-65-2048.jpg)
![Blocking probability (cont.)
•
•
•
Under the assumption of uniformly distributed load,
probability that a path between any two switching blocks
≥
is engaged is p = an/k (k≥n)
Probability that a certain path from an input block to an
output block is engaged is 1 - (1-p)2 where the last term is
the probability that both (input and output) links are
disengaged
Probability that all k paths between an input switching
block and an output switching block are engaged is
B = [1 - (1- an/k )2 ]k
which is known as Lee’s approximation
© P. Raatikainen
Switching Technology / 2003
4-7
Control complexity
•
Give a graph G , a control algorithm is needed to find and set up
paths in G to fulfill connection requirements
•
Control complexity is defined by the hardware (computation and
memory) requirements and the run time of the algorithm
•
Amount of computation depends on blocking category and degree of
blocking tolerated
•
In general, computation complexity grows exponentially as a function
of the number of terminal
•
There are interconnection networks that have a regular structure for
which control complexity is substantially reduced
•
There are also structures that can be distributed over a large number
of control units
© P. Raatikainen
Switching Technology / 2003
4-8
4](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-85-2048.jpg)
![Management complexity
•
•
Network management involves adaptation and maintenance of a
switching network after the switching system has been put in place
Network management deals with
• failure events and growth in connectivity demand
• changes of traffic patterns from day to day
• overload situations
• diagnosis of hardware failures in switching system, control system
as well as in access and trunk network
- in case of failure, traffic is rerouted through redundant built-in
hardware or via other switching facilities
- diagnosis and failure maintenance constitute a significant part of
software of a switching system
•
In order for switching cost to grow linearly in respect to total traffic,
switching functions (such as control, maintenance, call processing and
interconnection network) should be as modular as possible
© P. Raatikainen
Switching Technology / 2003
4-9
Example 1
•
A switch with
•
•
•
•
a capacity of N simultaneous calls
average occupancy on lines during busy hour is X Erlangs
Y % requirement for internal use
notice that two (one-way) connections are needed for a call
requires a switch fabric with M = 2 x [(100+Y)/100] x(N/X) inputs
and outputs.
•
If N = 20 000, X = 0.72 and Y = 10%
=> M = 2 x 1.1 x 20 000/0.72 = 61 112
=> corresponds to 2038 E1 links
1
2
2
M
© P. Raatikainen
Switching Technology / 2003
1
M
4 - 10
5](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-86-2048.jpg)
![Example 2
•
An exchange for 2000 subscribers is to be installed and it is
required that the blocking probability should be below 10 %.
If E2 links are used to carry the subscriber traffic to
telephone network, how many E2 links are needed ?
- average call lasts 6 min
- a subscriber places one call during a 2-hour busy period
(on the average)
• Amount of offered traffic is (2000x6 min /2x60 min) = 100 Erl.
• Erlang 1st formula gives for 10 % blocking and load of 100 Erl.
that n = 97
=> required number of E1 links is ceil(97/30) = 4
© P. Raatikainen
Switching Technology / 2003
4 - 13
Example 3
•
•
•
Suppose driving current of a switching gate (cross-point) is 100 mA
and its maximum input current is 8 mA
How many output gates can be connected to a bus, driven by one
input gate, if the capacitive load of the bus is negligibly small ?
Fan-out = floor[100/8] = 12
c
c
• How many output gates can be connected
to a bus driven by one input gate if load of
the bus corresponds to 15 % of the load of
a gate input) ?
• Fan-out = floor[100/(1.15x8)] = 10
© P. Raatikainen
Switching Technology / 2003
c
1
c
2
…
M
4 - 14
7](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-88-2048.jpg)
![Cantor network strict-sense
non-blocking (cont.)
•
Cantor network is symmetrical at the middle
=> the same number of center stage nodes are reachable by an
output of a Cantor network
•
Total number of SBs in center stages is Nm/2 (m Benes networks)
•
If the number of center stage SBs reached by an input and an
output exceeds Nm/2 then there must be a SB reachable from both
•
Hence strict-sense non-blocking is achieved if
2 [1 Nm - 1 (log 2 N - 1)N ] >
2
4
Nm
2
=> m > log2N - 1
Notice that a strict-sense non-blocking Cantor network is
constructed of log2N rearrangeably non-blocking Benes networks
© P. Raatikainen
Switching Technology / 2003
5-7
N INPUTS
N OUTPUTS
Visualization of proof
© P. Raatikainen
Switching Technology / 2003
5-8
4](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-107-2048.jpg)
![Merge-sorting algorithm (cont.)
• Merging of two sorted lists (N/2 numbers in each) requires N
binary sorts
• Total complexity of sorting N numbers is given by
C(N) = 2C(N/2) = N + 2(N/2 + 2C(N/4)) = … = Nlog2N
• Due to sequential nature of procedure Merge the sorting takes at
least O(N) time
1
4
6
10
11
15
17
20
© P. Raatikainen
Compare numbers
at the top of lists
then merge
2
5
7
9
12
14
16
24
Switching Technology / 2003
6 - 11
Odd-even merging
Recursive construction of an odd-even merger
...
¥ ¥
...
...
...
e0
e1
e2
e3
e4
eN/2-5
eN/2-4
eN/2-3
eN/2-2
eN/2-1
cN/2-2
cN/2-1
Odd
merger
N/2 dN/2-3
...
bN/2-4
bN/2-3
bN/2-2
bN/2-1
...
...
...
d0
d1
...
b0
b1
© P. Raatikainen
¥ ¥
...
aN/2-2
aN/2-1
Even
merger
N/2
c0
c1
c2
...
a0
a1
a2
a3
...
- number of sorting stages is log2N
- number of sorting elements is 0.5N [log2N-1]+1
dN/2-2
dN/2-1
Switching Technology / 2003
6 - 12
6](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-134-2048.jpg)
![Sorting by merging
Recursive construction of a sorting by merging network
- number of sorting stages is 0.5Nlog2N(log2N + 1)
¥
¥
Merger
N/2
¥
¥
¥
© P. Raatikainen
Merger
N
...
Merger
N/4
...
Merger
N/2
¥
Merger
N/4
...
...
aN-2
aN-1
Merger
N/4
¥
aN/2
aN/2+1
e0
¥
aN/2-1
...
...
...
aN/2-2
Merger
N/4
¥
a1
¥
a0
eN-1
Switching Technology / 2003
6 - 15
Odd-even sorting network example
• Number of sorting stages is 0.5log2N(log2N + 1)
• Number of sorting elements is 0.25N[log2N(log2N - 1) + 4] - 1
2x2
SORTER
4x4
SORTER
8x8
SORTER
¥ ¥
¥
¥ ¥
¥
¥
¥
¥ ¥
¥
¥ ¥
¥ ¥
¥
¥
¥
¥
¥ ¥
© P. Raatikainen
2x2 UP SORTER
2x2 DOWN SORTER
Switching Technology / 2003
6 - 16
8](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-136-2048.jpg)
![Design optimization example (cont.)
• As an example, let’s assume that price of each component is a function of
time and is given by P(t)=Ce-t/T+ D ,
where C, D and T are component specific constants
=> Pa(t)=Cae-t/Ta+ Da , Pb(t)=Cbe-t/Tb+ Db and Pc(t)=Cce-t/Tc+ Dc
• Number of alternative crossbar components needed to build an NxN switch
=> Ka = ceil[N/Na]2, Kb = ceil[N/Nb]2 , Kc = ceil[N/Nc]2
• Alternative component costs as a function of time t
=> Pa(t)=Cae-(t- ta)/Ta+ Ca
=> Pb(t)=Cbe-(t- tb)/Tb+ Cb
=> Pc(t)=Cce-(t- tc)/Tc+ Cc
• These functions can be used to draw price development curves to make
comparisons
© P. Raatikainen
Switching Technology / 2003
6 - 51
Design optimization example (cont.)
Numerical example:
• Let N = 64, Na = 16, Nb = 32, Nc = 64, Ta = Tb = Tc = 3 time units (years),
Ca = 20,Cb = 50, Cc = 100 and Da = 10, Db = 20, Dc = 40 price units (euros)
• Product development period is assumed to be 1 time unit (year) and
tb = ta +1.5, tc = ta +3, tm = ta +4 => tpd = ta + 3
• Choosing that tpd = to = 0 => ta = t + 3, tb = t +1.5, tc = t, tm = t -1 (t ≥ tpd = 0 )
• Number of components needed Ka = 16, Kb = 4, Kc = 1
• Switch fabric component cost functions
=> Pa(t)=16[20e-(t+3)/3 + 10]
=> Pb(t)=4[50e-(t+1.5)/3 + 20]
=> Pc(t)=100e-(t)/3 + 40
© P. Raatikainen
Switching Technology / 2003
6 - 52
26](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-154-2048.jpg)
![Combinatorial reliability
• A serial system S functions if and only if all
its parts Si (1≤i≤n) function
S
n
=> Rs = Π Ri and Fs = (1- Rs)
S1
i=1
S2
Sn
• Failures in sub-systems are supposed to be
independent
S1
• A parallel (replicated) system fails if all its subsystems fail
n
=> Fs = Π (1-Ri)
i=1
S2
n
and Rs = 1- Fs = 1- Π (1-Ri)
i=1
Sn
• Reliability of a duplicated system (Ri = R) is
Rs = 1- (1-R)2
© P. Raatikainen
S
Switching Technology / 2003
7 - 29
Combinatorial reliability example 1
• Calculate reliability Rs and failure probability Fs of system S
given that failures in sub-systems Si are independent and for
some time interval it holds that
R1 = 0.90, R2 = 0.95 and R3 = R4 = 0.80
=> Rs = Π Ri = R1 x R2 x R3-4
=> R3-4 = 1- Π (1-Ri) = 1- (1- R3)(1- R4)
=> Rs = R1 x R2 x [1- (1- R3)(1- R4)]
S
S1
S3-4
S3
S2
S4
=> Fs = 1- Rs = 1 - R1 x R2 x [1- (1- R3)(1- R4)]
=> Rs = 0.82 and Fs = 0.18
© P. Raatikainen
Switching Technology / 2003
7 - 30
15](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-170-2048.jpg)
![Combinatorial reliability (cont.)
• If failures in sub-systems Si of an m/n system
are independent and Ri = R for all i∈[1,n]
then the system is a Bernoulli system and
binomial distribution applies
n
=> Rs =
Σ ( k )Rk(1-R)n-k
k=m
n
• For a system of m/n = 2/3
3
3!
−−−−
=> R2/3 = Σ k!(3-k)! Rk(1-R)3-k = 3R2 - 2R3
k=2
If for example R
S1
S2
S
m/n
Sn
= 0.9 => R2/3 = 0.972
© P. Raatikainen
Switching Technology / 2003
7 - 33
Computing MTTF
• MTTF =
∞
∫ R(t)dt - valid for any reliability distribution
0
• Single component with a constant failure rate (CFR) λ
- R(t) = e-λt
- MTTF = 1/λ
λ
• Serial systems with n CFR components
- Rs(t) = R1(t) x R2(t) x ... x Rn(t) = e- (λ1 + λ2 + ... + λn)t = e- λst
- λs= λ1 + λ2 + ... + λn
• MTTFs = 1/ λs
• 1/MTTFs = 1/MTTF1 + 1/MTTF2 + ... + 1/MTTFn
© P. Raatikainen
Switching Technology / 2003
7 - 34
17](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-172-2048.jpg)
![Telecom exchange reliability from
subscriber’s point of view
n-1/n
Line-card
Subscriber
module
control
Subscriber
call
control
Centralized
functions
Exchange
terminal
CCS7 signaling processors
• (n-1)/n operational processors
for call setup
• chosen processor functions
during a call
Premature release requirement P ≤ 2x10-5 applied
© P. Raatikainen
Switching Technology / 2003
7 - 35
Failure intensity
• Unit of failure intensity λ is defined to be
λ
[λ] = fit = number of faults /109 h
• Failure intensities for replaceable plug-in-units varies in the
range 0.1 - 10 kfit
• Example:
• if failure intensity of a line-card in an exchange is 2 kfit, what
is its MTTF ?
109 h
1 000 000 h
MTTF = 1/λ = = = 58 years
λ 2000
2x24x360
© P. Raatikainen
Switching Technology / 2003
7 - 36
18](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-173-2048.jpg)
![Markov chain modeling (cont.)
• Probabilities (πi) of the states and transition rates (λij) between the
states are tied together with the following formula
πΛ = 0
where
π n]
)
¡
¡
¢
¡
¡
© P. Raatikainen
)
λ13
λ23
− (λ31 + λ32 +
¢
λ12
− (λ21 + λ23 +
λ32
¢
)
¢
¢
− (λ12 + λ13 +
λ21
Λ=
λ31
¢
π = [π 1 π 2
Switching Technology / 2003
7 - 39
Markov chain modeling (cont.)
Example
λ12
λ13
− (λ12 + λ13 )
Λ=
− (λ21 + λ23 )
λ21
λ23
− (λ31 + λ32 )
λ31
λ32
and π = [π 1 π 2
£
πΛ = 0
πn]
− (λ12 + λ13 )π 1 + λ12π 2 + λ13π 3 = 0
λ21π 1 − (λ21 + λ23 )π 2 + λ23π 3 = 0
λ π + λ π − (λ + λ )π = 0
32 2
31
32
3
31 1
© P. Raatikainen
Switching Technology / 2003
λ12
S1
λ31
S2
λ21
λ13
λ32
λ23
S3
7 - 40
20](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-175-2048.jpg)
![Markov chain modeling (cont.)
Chapman-Kolmogorov equations:
∀i , j ∈ S
pij ( t + s ) = ∑ pik ( t ) pkj ( s )
∀s , t ≥ 0
k∈S
Since p(t) is a continuous function
d
pij ( ∆t ) = pij (0 ) + pij ( 0) ∆t + o( ∆t 2 )
dt
d
λij ( t ) = pij (0 )
We have defined =>
dt
≠
For i≠j:
pij ( ∆t ) = pij (0 ) + λij ∆t + o( ∆t 2 ) ≈ λij ∆t
(for small ∆t)
For i=j:
pii ( ∆t ) = pii (0 ) + λii ∆t + o( ∆t 2 ) ≈ 1 + λii ∆t
(for small ∆t)
© P. Raatikainen
Switching Technology / 2003
7 - 49
Markov chain modeling (cont.)
From Chapman-Kolmogorov equations:
pij ( t + ∆t ) = ∑ pik ( t ) pkj ( ∆t ) = pij ( t ) p jj ( ∆t ) + ∑ pik ( t ) pkj ( ∆t )
k≠ j
k
[
]
[
= pij ( t ) 1 + λ jj ∆t + o( ∆t ) + ∑ pik ( t ) λkj ∆t + o( ∆t 2 )
2
k≠ j
]
pij ( t + ∆t ) = pij ( t ) + ∑ pik ( t )λkj ∆t + ∑ pik ( t ) o( ∆t 2 )
k
k
pij ( t + ∆t ) − pij ( t )
∆t
o( ∆ t 2 )
= ∑ pik ( t )λkj + ∑ pik ( t )
k
k
∆t
Taking the limit as ∆t → 0
© P. Raatikainen
d
pij ( t ) = ∑ pik ( t )λkj
dt
k
Switching Technology / 2003
∀i , j
7 - 50
25](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-180-2048.jpg)
![Markov chain modeling (cont.)
An alternative derivation of the steady-state conditions begins with
the differential equation describing the process:
d
pij ( t ) = ∑ pik ( t )λkj
dt
k
∀i , j
Suppose that we take the limit of each side as t → ∞
d
pij (t ) = lim ∑ pik (t )λkj
t →∞
dt
k
=>
lim
=>
d
lim pij (t ) = ∑ lim pik (t )λkj
t →∞
dt t →∞
k
=>
∑π
t →∞
k
λkj = 0
i.e. πΛ=0
k
© P. Raatikainen
Switching Technology / 2003
7 - 55
Markov chain modeling (cont.)
Example
λ12
λ13
− (λ12 + λ13 )
Λ=
− (λ21 + λ23 )
λ21
λ23
− (λ31 + λ32 )
λ31
λ32
and π = [π 1 π 2
πΛ = 0
πn]
λ12
S1
λ31
S2
λ21
λ13
λ32
λ23
S3
− (λ12 + λ13 )π 1 + λ21π 2 + λ31π 3 = 0
λ12π 1 − (λ21 + λ23 )π 2 + λ32π 3 = 0
λ π + λ π − (λ + λ )π = 0
23 2
31
32
3
13 1
© P. Raatikainen
Switching Technology / 2003
7 - 56
28](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-183-2048.jpg)
![MTIE limits for PRC, SSU and SEC
Clock
source
Time-slot
interval [ns]
Time-slot
interval [ns]
PRC
25 ns
0.3t ns
300 ns
0.01t ns
0.1 < t < 83 s
83 < t < 1000 s
1000 < t < 30 000 s
t > 30 000 s
SSU
25 ns
10t ns
2000 ns
433t0.2 + 0.01t ns
0.1 < t < 2.5 s
2.5 < t < 200 s
200 < t < 2 000 s
t > 2 000 s
SEC
250 ns
100t ns
2000 ns
433t0.2 + 0.01t ns
0.1 < t < 2.5 s
2.5 < t < 20 s
20 < t < 2 000 s
t > 2 000 s
ETS 300 462-3
© P. Raatikainen
Switching Technology / 2003
8 - 25
Occurrence of slips
• Slips occur on connections whose timing differs from the timing signal used by
the exchange
• If both ends of a connection are internally synchronized to a PRC signal,
theoretically slips occur no more frequently than once in 72 days
• In a reference connection a slip occurs theoretically once in 72/12 = 6 days
or if national segments are synchronized once in 720/4 = 18 days
• Slip requirement on an end-to-end connection is looser:
Average frequency of slips
Share of time during one year
≤ 5 slips / 24h
98.90 %
5 slips/ 24 h …. 30 slips/ 1h
<1%
≤ 10 slips / 1h
< 0.1 %
© P. Raatikainen
Switching Technology / 2003
8 - 26
13](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-196-2048.jpg)
![Slip calculation example
Show that two networks with single frame buffers and timed from
separate PRCs would see a maximum slip rate of one slip every
72 days
Solution:
• Timing accuracy of a PRC clock is 10-11
• Let the frequencies of the two ends be f1 and f2
• In the worst case, these frequencies deviate from the reference
clock fo by 10-11x fo and those deviations are to different directions
• Let the frequencies be f1 = (1+ 10-11) fo and f2 = (1- 10-11) fo
• Duration of bits in these networks are T1= 1/ f1 and T2= 1/ f2
© P. Raatikainen
Switching Technology / 2003
8 - 27
Slip calculation example (cont.)
Solution (cont.):
• During one bit interval, the timing difference is T1- T2 and after
some N bits the difference exceeds a frame length of 125 µs and a
slip occurs => NT1- T2 = 125x10-9
-9 /[(1/ f -1/ f ) ]
=> N = 125x10
1
2
• Inserting f1 = (1+ 10-11) fo and f2 = (1- 10-11) fo into the above equation,
we get => N = 125x10-9 fo (1- 10-22)/(2x 10-11)
• Multiplying N by the duration (Tb) of one bit , we get the time (Tslip)
between slips
• In case of E1 links, fo= 2.048x106/s and Tb = 488 ns. Dividing the
obtained Tslip by 60 (s), then by 60 (min) and finally by 24 (h) we get
the average time interval between successive slips to be 72.3 days
© P. Raatikainen
Switching Technology / 2003
8 - 28
14](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-197-2048.jpg)
![PDH bit rates and related bit/octet times
Hierarchy
level
Time-slot
Bit interval
interval [ns]
[ns]
E1/2M
3906
488
E2/8M
947
118
E3/34M
233
29
E4/140M
57.4
7.2
• When time-slots turn into parallel form (8 bits in parallel) memory
speed requirement decreased by a factor of 8
• Present day memory technology enables up to 256 PDH E1 signals
to be written to and read from a SRAM memory on wire speed
© P. Raatikainen
Switching Technology / 2003
8 - 35
Properties of full matrix switches
Pros
• strict-sense non-blocking
• no path search - a connection can always be written into the
control memory if requested output is idle
• multi-cast capability
• constant delay
• multi-slot connections possible
Cons
• switch and control memory both increase in square of the number
of input/outputs
• broadband - required memory speed may not be available
© P. Raatikainen
Switching Technology / 2003
8 - 36
18](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-201-2048.jpg)
![New directions in IP lookup
• More efficient lookup schemes have been developed to improve the
average lookup performance and storage complexity
• Examples of new methods are
• Binary search on trie levels, which decomposes the longest prefix
operation into W exact matching operations, each performed on prefixes
of equal length
• Multiway or K-way range search, which applies a binary search to best
matching prefixes by using two routing entries per prefix and with some
precomputation
• Ternary CAM uses a special CAM (Content Addressable Memory),
which performs parallel comparisons internally. TCAM stores each W-bit
field as a [val, mask] pair and when a bit string is presented to the input,
TCAM outputs the location (or address) where a match is found.
© P. Raatikainen
Switching Technology / 2005
L10 - 65
New directions in IP lookup (cont.)
• Conventional routers offer the best-effort service by processing each
incoming packet in the same way. New applications require different
QoS levels and to meet these requirements new mechanisms, such
as admission control, resource reservation and per-flow queuing,
need to be implemented in routers.
• Routers are required to distinguish and classify incoming traffic into
different flows
• Flows are specified by rules and each rule consists of operations for
comparing packet fields with certain values
• Packet fields to be inspected are collected from different protocols
=> packet classification
© P. Raatikainen
Switching Technology / 2005
L10 - 66](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-272-2048.jpg)
![Optical spectrum
• Since wavelength λ and frequency f are related by f λ = c, where c is the
velocity of light in the medium, we have the relation
∆ f ≈ − c ∆λ
2
λ
• Thus, 10 GHz ≈ 0.08 nm and 100 GHz ≈ 0.8 nm in the range of 1,550 nm,
where most modern lightwave networks operate
• The 10-GHz channel spacing is sufficient to accommodate λ-channels
carrying aggregate digital bit rates on the order of 1 Gbps
- modulation efficiency of 0.1 bps/Hz typical for optical systems
• The 10-GHz channel spacing is suitable for optical receivers, but much too
dense to permit independent wavelength routing at the network nodes
- for this, 100-GHz channel spacing is needed.
• In a waveband routing network, several λ-channels (with 10-GHz channel
spacing) comprise an independently routed waveband (with 100-GHz
spacing between wavebands).
P. Raatikainen
Switching Technology / 2003
11 - 13
Wavelength partitioning of the optical
spectrum
Unusable spectrum
λ1
λ2
λm
...
λ
f/λ [GHz/nm]
10 GHz
0.08 nm
λ-channel spacing for separability at receivers
λ1
λ2
λm
...
f/λ
λ
100 GHz/0.8 nm
λ-channel spacing for separability at network nodes
P. Raatikainen
Switching Technology / 2003
11 - 14
7](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-280-2048.jpg)
![Directional Coupler (1)
• Directional coupler (= 2x2 switch) is an optical four-port
– ports 1 and 2 designated as input ports
– ports 1’ and 2’ designated as output ports
• Optical power
– enters a coupler through fibers attached to input ports,
– divided and combined linearly
– leaves via fibers attached to output ports
• Power relations for input signal powers
powers P1′ and P2′ are given by
P1 and P2 and output
P ′ = a11 P + a12 P2
1
1
P2′ = a21 P + a22 P2
1
1
• Denote the power transfer matrix by A
P. Raatikainen
= [aij]
2
a11
a21
a12
1′
2′
a22
Switching Technology / 2003
11 - 27
Directional Coupler (2)
• Ideally, the power transfer matrix A is of the form
1 − α
A=
α
α
,
1−α
0 ≤α ≤1
• If parameter α is fixed, the device is static, e.g. with α = 1/2 and
signals present at both inputs, the device acts as a 2x2 star coupler
• If α can be varied through some external control, the device is
dynamic or controllable, e.g. add-drop switch
• If only input port 1 is used (i.e., P2 = 0),
1
the device acts as a 1x2 divider
• If only output port 1’ is used (and port 2’ is
2
terminated), the device acts as a 2x1 combiner
P. Raatikainen
Switching Technology / 2003
1−α
α
α
1−α
1′
2′
11 - 28
14](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-287-2048.jpg)
![Permutation switch
P. Raatikainen
1′
2′
3′
4′
output ports
1′ 2′ 3′ 4′
input ports
1
• Dynamic NxN permutation switch
(e.g. crossbar switch)
2
– unicast optical connections
3
between input and output ports
4
– N! connection states (if
nonblocking)
– each connection state can carry N
simultaneous unicast optical
connections
– representation of a connection state
by a NxN connection matrix
1
1
2 1
3
1
4
1
Switching Technology / 2003
11 - 33
Generalized switch
• Dynamic RxN generalized switch (e.g.
crossbar switch)
1/N
1/N
1/N
1/N
1
– any input/output pattern possible
2
– 2NR connection states
3
– each connection state can carry (at most)
R simultaneous multicast optical
4
connections
– a connection state represented by a RxN
connection matrix
1 ,
aij = NR
0,
P. Raatikainen
if switch (i,j ) is on
otherwise
Switching Technology / 2003
2′
3′
4′
output ports
1′ 2′ 3′ 4′
input ports
• Input/output power relation P’ = AP with
NxR power transfer matrix A = [aij], where
1/R1/R
1/R
1/R
1′
1
1 1
2 1
1
3
1
4 1 1 1
11 - 34
17](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-290-2048.jpg)
![Linear Divider-Combiner (LDC)
1′
1
δ11
• Linear Divider-Combiner (LDC) is
δ δ21
δ41 31
a generalized switch that
2
– controls power-dividing and
power-combining ratios
3
σ41
– less inherent loss than in crossbar
σ σ42
σ4443
4
• Power-dividing and power-combining ratios
– δij = fraction of power from input port j directed to output port i’
– σij = fraction of power from input port j combined onto output port i
• In an ideal case of lossless couplers, we have constraints
2′
3′
4′
∑ δ ij = 1 and ∑ σ ij = 1
i
j
• The resulting power transfer matrix A = [aij] is such that
aij = δ ijσ ij
P. Raatikainen
Switching Technology / 2003
11 - 35
LDC and generalized switch realizations
1
rx1
combiner
directional couplers
11
12
1r
...
22
2r
...
21
2
1xn
splitter
n
...
δ - σ linear divider-combiner
1
2
n1
r
n2
nr
Generalized optical switch
P. Raatikainen
Switching Technology / 2003
11 - 36
18](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-291-2048.jpg)
![Connections in various layers
• Logical connection sublayer
– Logical connection (LC) is a unidirectional connection between
external ports on a pair of source and destination network
access stations (NAS)
• Optical connection sublayer
– Optical connection (OC) defines a relation between one
transmitter and one or more receivers, all operating in the same
wavelength
• Optical path sublayer
– Optical path (OP) routes the aggregate power on one waveband
on a fiber, which could originate from several transmitters within
the waveband
P. Raatikainen
Switching Technology / 2003
11 - 55
Notation for connections in various
layers
• Logical connection sublayer
– [a, b] = point-to-point logical connection from an external port on station a
to one on station b
– [a, {b, c, …}] = multi-cast logical connection from a to set {b, c, …}
• station a sends the same information to all receiving stations
• Optical connection sublayer
– (a, b) = point-to-point optical connection from station a to station b
– (a, b)k = point-to-point optical connection from a to b using wavelength λk
– (a,{b,c,…}) = multi-cast optical connection from a to set {b,c,…}
• Optical path sublayer
– 〈a, b〉 = point-to-point optical path from station a to station b
– 〈a, b〉k = point-to-point optical path from a to b using waveband wk
– 〈a, {b, c, …}〉 = multi-cast optical path from a to set {b,c,…}
P. Raatikainen
Switching Technology / 2003
11 - 56
28](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-301-2048.jpg)
![Example of a logical connection between
two NASs
Logical connection [A,B]
NAS
NAS
TP
RP
Transmission channel
Electrical
Optical connection (A,B)λ1
OT
Optical
λ-channel
λ1 ... λm
WMUX
Electrical
OR
λm ... λ1
Optical
WDMUX
Optical path <A,B>w1
w1
ONN
w2
P. Raatikainen
ONN
ONN
Switching Technology / 2003
11 - 57
Contents
• The Big Picture
• Network Resources
• Network Connections
– Connectivity
– Connections in various layers
– Example: realizing full connectivity between
five end systems
P. Raatikainen
Switching Technology / 2003
11 - 58
29](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-302-2048.jpg)
![Static networks
• Static network, also called broadcast-and-select network, is a
purely optical shared medium network
• passive splitting and combining nodes are interconnected by fibers to
provide static connectivity among some or all OTs and ORs
• OTs broadcast and ORs select
• Broadcast star network is an example of such a static network
• star coupler combines all signals and broadcasts them to all ORs
- static optical multi-cast paths from any station to the set of all stations
- no wavelength selectivity at the network node
• optical connection is created by tuning the source OT and/or destination
OR to the same wavelength
• two OTs must operate at different wavelengths (to avoid interference)
- this is called the distinct channel assignment (DCA) constraint
• however, two ORs can be tuned to the same wavelength
- by this way, optical multi-cast connections are created
P. Raatikainen
Switching Technology / 2003
12 - 3
Realization of logical connectivity
• Methods to realize full point-to-point logical connectivity in a
broadcast star with N nodes:
• WDM/WDMA
- a whole λ-channel allocated for each LC
- N(N-1) wavelengths needed (one for each LC)
- N-1 transceivers needed in each NAS
• TDM/TDMA
- 1/[N(N-1)] of a λ-channel allocated for each LC
- 1 wavelength needed
- 1 transceiver needed in each NAS
• TDM/T-WDMA
- 1/(N-1) of a λ-channel allocated for each LC
- N wavelengths needed (one for each OT)
- 1 transceiver needed in each NAS, e.g. fixed OT and tunable OR
(FT-TR), or tunable OT and fixed OR (TT-FR)
P. Raatikainen
Switching Technology / 2003
12 - 4](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-307-2048.jpg)
![Broadcast star using WDM/WDMA
LCs
[1,2]
[1,3]
[2,1]
[2,3]
[3,1]
[3,2]
LCs
NAS 1
TP
TP
TP
λ1
OT λ
2
OT
λ3
OT λ
4
OT
λ5
OT λ
6
OT
λ1,2
λ1-6
λ3,4
λ1-6
λ1-6
λ5,6
λ3
λ5 OR
OR
λ1
λ6 OR
OR
λ2
λ4 OR
OR
RP
[2,1]
[3,1]
RP
[1,2]
[3,2]
RP
[1,3]
[2,3]
star coupler
P. Raatikainen
Switching Technology / 2003
12 - 5
Broadcast star using TDM/TDMA
LCs
NAS 1
[1,2]
[1,3]
TP
OT
[2,1]
[2,3]
TP
OT
[3,1]
[3,2]
TP
OT
λ1
λ1
λ1
LCs
λ1
λ1
OR
RP
[2,1]
[3,1]
OR
RP
[1,2]
[3,2]
OR
RP
[1,3]
[2,3]
λ1
star coupler
P. Raatikainen
Switching Technology / 2003
12 - 6](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-308-2048.jpg)
![Effect of propagation delay on
TDM/TDMA
OT1
[1,2]1
[1,2]2
[1,3]1
[1,2]2
From 1
[2,3]2
From 2
From 1
F1
From 2
From 1
F1
From 2
F1
From 2
F2
From 1
P. Raatikainen
From 2
F2
From 1
OR2
OR3
[1,3]1
[2,3]1
OT2
Coupler
[1,2]1
From 1
A TDM/TDMA schedule
From 2
F2
Switching Technology / 2003
12 - 7
Broadcast star using TDM/T-WDMA in
FT-TR mode
LCs
fixed
[1,2]
[1,3]
TP
OT
[2,1]
[2,3]
TP
OT
[3,1]
[3,2]
TP
OT
NAS 1
λ1
λ2
λ3
tunable
λ1-3
λ1-3
λ1-3
LCs
λ2
λ3 OR
RP
[2,1]
[3,1]
λ1
λ3 OR
RP
[1,2]
[3,2]
λ1
λ2 OR
RP
[1,3]
[2,3]
star coupler
P. Raatikainen
Switching Technology / 2003
12 - 8](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-309-2048.jpg)
![Broadcast star using TDM/T-WDMA in
TT-FR mode
LCs
[1,2]
[1,3]
[2,1]
[2,3]
[3,1]
[3,2]
tunable
TP
λ2
OT λ3
TP
λ1
OT λ3
TP
λ1
OT λ2
NAS 1
fixed
λ1
λ2,3
λ1,3
λ1,2
λ1-3
λ1-3
λ1-3
λ2
λ3
LCs
OR
RP
[2,1]
[3,1]
OR
RP
[1,2]
[3,2]
OR
RP
[1,3]
[2,3]
star coupler
P. Raatikainen
Switching Technology / 2003
12 - 9
Channel allocation schedules for circuit
switching
WDM/WDMA
λ1
λ2
λ3
λ4
[1,2] [1,2] [1,2] [1,2]
[1,3] [1,3] [1,3] [1,3]
[2,1] [2,1] [2,1] [2,1]
TDM/T-WDMA with FT-TR
λ1 [1,2] [1,3] [1,2] [1,3]
λ2 [2,3] [2,1] [2,3] [2,1]
λ3 [3,1] [3,2] [3,1] [3,2]
TDM/T-WDMA with TT-FR
λ1 [2,1] [3,1] [2,1] [3,1]
λ2 [3,2] [1,2] [3,2] [1,2]
λ3 [1,3] [2,3] [1,3] [2,3]
[2,3] [2,3] [2,3] [2,3]
λ5 [3,1] [3,1] [3,1] [3,1]
λ6 [3,2] [3,2] [3,2] [3,2]
frame
TDM/TDMA
frame
frame
Channel allocation schedule (CAS) should be
- realizable = only one LC per each OT and time-slot
- collision-free = only one LC per each λ and time-slot
- conflict-free = only one LC per each OR and time-slot
λ1 [1,2] [1,3] [2,1] [2,3] [3,1] [3,2] [1,2] [1,3] [2,1] [2,3] [3,1] [3,2]
frame
P. Raatikainen
Switching Technology / 2003
12 - 10](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-310-2048.jpg)
![Static wavelength routed star
• Full point-to-point logical/optical connectivity in a static
wavelength routed star with N nodes can be realized by
– WDM/WDMA
• a whole λ-channel allocated for each LC
• N-1 wavelengths needed
- spectrum reuse factor is N
(= N(N-1) optical connections / N-1 wavelengths)
• N-1 transceivers needed in each NAS
P. Raatikainen
Switching Technology / 2003
12 - 15
Static wavelength routed star using
WDM/WDMA
LCs
NAS 1
[1,2]
[1,3]
TP
[2,1]
[2,3]
TP
[3,1]
[3,2]
TP
λ1
OT λ
2
OT
λ2
OT λ
1
OT
λ1
OT λ
2
OT
λ1,2
λ1,2
λ1,2
LC’
λ1,2
λ1,2
λ1,2
λ2
λ1 OR
OR
λ1
λ2 OR
OR
λ2
λ1 OR
OR
RP
[2,1]
[3,1]
RP
[1,2]
[3,2]
RP
[1,3]
[2,3]
wavelength router
P. Raatikainen
Switching Technology / 2003
12 - 16](https://image.slidesharecdn.com/optix-core-good-140111131404-phpapp02/75/Optical-Switching-Comprehensive-Article-313-2048.jpg)
Uploaded byMapYourTech
Optical Switching Comprehensive Article
This document outlines an optics switching technology course, including: - The course covers switching technology, including understanding switching systems, fabrics, implementations, and optical switching. - The schedule lists 13 lectures and 7 exercises over 14 weeks, covering topics such as switch fabrics, PDH, ATM, and optical networks. - Readings are provided to supplement the lecture materials, and requirements include exercises, a grading system, and a final examination.
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Optical Switching Comprehensive Article
- 1. Optics Switching Technology © P.Raatikainen Switching Technology / 2005 L1 - 1 General • Lecturer:Pertti Raatikainen, research professor /VTT email: pertti.raatikainen@vtt.fi • Exercises: Kari Seppänen, snr. research scientist /VTT email: kari.seppänen@vtt.fi • Information: http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2005 L1 - 2
- 2. Goals of thecourse • Understand what switching is about • Understand the basic structure and functions of a switching system • Understand the role of a switching system in a transport network • Understand how a switching system works • Understand technology related to switching • Understand how conventional circuit switching is related to packet switching © P. Raatikainen Switching Technology / 2005 L1 - 3 Course outline • Introduction to switching – switching in general – switching modes – transport and switching • Switch fabrics – basics of fabric architectures – fabric structures – path search, self-routing and sorting © P. Raatikainen Switching Technology / 2005 L1 - 4
- 3. Course outline • Switchimplementations – PDH switches – ATM switches – routers • Optical switching – basics of WDM technology – components for optical switching – optical switching concepts © P. Raatikainen Switching Technology / 2005 L1 - 5 Course requirements • Preliminary information – S-38.188 Tietoliikenneverkot or S-72.423 Telecommunication Systems (or a corresponding course) • 13 lectures (á 3 hours) and 7 exercises (á 2 hours) • Calculus exercises • Grating – Calculus 0 to 6 bonus points – valid in exams in 2005 – Examination, max 30 points © P. Raatikainen Switching Technology / 2005 L1 - 6
- 4. Course material • Lecturenotes • Understanding Telecommunications 1, Ericsson & Telia, Studentlitteratur, 2001, ISBN 91-44-00212-2, Chapters 2-4. • J. Hui: Switching and traffic theory for integrated broadband networks, Kluwer Academic Publ., 1990, ISBN 0-7923-9061-X, Chapters 1 - 6. • H. J. Chao, C. H. Lam and E. Oki: Broadband Packet Switching technologies – A Practical Guide to ATM Switches and IP routers, John Wiley & Sons, 2001, ISBN 0-471-00454-5. • T.E. Stern and K. Bala: Multiwavelength Optical Networks: A Layered Approach, Addison-Wesley, 1999, ISBN 0-201-30967-X. © P. Raatikainen Switching Technology / 2005 L1 - 7 Additional reading • A. Pattavina: Switching Theory - Architecture and Performance in Broadband ATM Networks, John Wiley & Sons (Chichester), 1998, IBSN 0-471-96338-0, Chapters 2 - 4. • R. Ramaswami and K. Sivarajan, Optical Networks, A Practical Perspective, Morgan Kaufman Publ., 2nd Ed., 2002, ISBN 1-55860-6556. © P. Raatikainen Switching Technology / 2005 L1 - 8
- 5. Schedule Day L/E Topic 18.1. L Introduction toswitching 25.1. L Transmission techniques and multiplexing 27.1. E Exercise 1 1.2. L Basic concepts of switch fabrics 8.2. L Multistage fabric architectures 1 10.2. E Exercise 2 15.2. L Multistage fabric architectures 2 22.2. L Self- routing and sorting networ ks 24.2. E Exercise 3 1.3. L Switch fabric implementations 8.3. L PDH switches 10.3. E Exercise 4 15.3. L ATM switches 17.3. E Exercise 5 22.3. L Routers 5.4. L Introduction to optical networks 7.4. E Exercise 6 12.4. L Optical network architectures 19.4. L Optical switches 21.4. E Exercise 7 © P. Raatikainen Switching Technology / 2005 L1 - 9 Introduction to switching Switching Technology S38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2005 L1 - 10
- 6. Introduction to switching •Switching in general • Switching modes • Transport and switching © P. Raatikainen Switching Technology / 2005 L1 - 11 Switching in general ITU-T specification for switching: “The establishing, on-demand, of an individual connection from a desired inlet to a desired outlet within a set of inlets and outlets for as long as is required for the transfer of information.” inlet/outlet = a line or a channel © P. Raatikainen Switching Technology / 2005 L1 - 12
- 7. Switching in general(cont.) • Switching implies directing of information flows in communications networks based on known rules • Switching takes place in specialized network nodes • Data switched on bit, octet, frame or packet level • Size of a switched data unit is variable or fixed © P. Raatikainen Switching Technology / 2005 L1 - 13 Why switching ? • Switches allow reduction in overall network cost by reducing number and/or cost of transmission links required to enable a given user population to communicate • Limited number of physical connections implies need for sharing of transport resources, which means – better utilization of transport capacity – use of switching • Switching systems are central components in communications networks © P. Raatikainen Switching Technology / 2005 L1 - 14
- 8. Full connectivity betweenhosts Full mesh © P. Raatikainen Number of links to/from a host = n-1 Total number of links = n(n-1)/2 Switching Technology / 2005 L1 - 15 Centralized switching Number of links to/from a host = 1 Total number of links = n © P. Raatikainen Switching Technology / 2005 L1 - 16
- 9. Switching network toconnect hosts Number of links to/from a host = 1 Total number of links depends on used network topology © P. Raatikainen Switching Technology / 2005 L1 - 17 Hierarchy of switching networks Local switching network To higher level of hierarchy Long distance switching network © P. Raatikainen Switching Technology / 2005 L1 - 18
- 10. Sharing of linkcapacity Space Division Multiplexing (SDM) 1 1 2 CH n 3 ... ... Physical link CH 2 ... 3 2 CH 1 Physical link n n Space to be divided: - physical cable or twisted pair - frequency - light wave © P. Raatikainen Switching Technology / 2005 L1 - 19 Sharing of link capacity (cont.) Time Division Multiplexing (TDM) Synchronous transfer mode (STM) 1 ... 2 1 n n-1 1 … 3 2 2 1 ... ... 2 n n Asynchronous transfer mode (ATM) 1 ... 1 1 1 idle idle n 2 2 ... n n Overhead © P. Raatikainen 2 1 ... 2 k Payload Switching Technology / 2005 L1 - 20
- 11. Main building blocksof a switch Switch control Input Interface Input Card #1 Interface Input Card #1 interface #1 • • • • • input signal reception error checking and recovery incoming frame disassembly buffering routing/switching decision Switch fabric • switching of data units from input interfaces to destined output interfaces • limited buffering Output Interface Output Card #1 Interface Output Card #1 interface #1 • buffering, prioritizing and scheduling • outgoing frame assembly • output signal generation and transmission • processing of signaling/connection control information • configuration and control of input/output interfaces and switch fabric © P. Raatikainen Switching Technology / 2005 L1 - 21 Heterogeneity by switching • Switching systems allow heterogeneity among terminals – terminals of different processing and transmission speeds supported – terminals may implement different sets of functionality • and heterogeneity among transmission links by providing a variety of interface types – data rates can vary – different link layer framing applied – optical and electrical interfaces – variable line coding © P. Raatikainen Switching Technology / 2005 L1 - 22
- 12. Heterogeneity by switching(cont.) … Analog interface … Subscriber mux ISDN (2B+D) or E1 E1 or E2 E1, E2 or E3 … Remote subscriber switch © P. Raatikainen Switching Technology / 2005 L1 - 23 Basic types of witching networks • Statically switched networks – connections established for longer periods of time (typically for months or years) – management system used for connection manipulation • Dynamically switched networks – connections established for short periods of time (typically from seconds to tens of minutes) – active signaling needed to manipulate connections • Routing networks – no connections established - no signaling – each data unit routed individually through a network – routing decision made dynamically or statically © P. Raatikainen Switching Technology / 2005 L1 - 24
- 13. Development of switchingtechnologies Broadband, optical Broadband, electronic SPC, digital switching SPC, analog switching Crossbar switch Step-by-step Manual 1950 SPC - stored program control 1960 1970 1980 1990 2000 2010 2020 Source: Understanding Telecommunications 1, Ericsson & Telia, Studentlitteratur, 2001. © P. Raatikainen Switching Technology / 2005 L1 - 25 Development of switching tech. (cont.) • Manual systems – in the infancy of telephony, exchanges were built up with manually operated switching equipment (the first one in 1878 in New Haven, USA) • Electromechanical systems – manual exchanges were replaced by automated electromechanical switching systems – a patent for automated telephone exchange in 1889 (Almon B. Strowger) – step-by-step selector controlled directly by dial of a telephone set – developed later in the direction of register-controlled system in which number information is first received and analyzed in a register – the register is used to select alternative switching paths (e.g. 500 line selector in 1923 and crossbar system in 1937) – more efficient routing of traffic through transmission network – increased traffic capacity at lower cost © P. Raatikainen Switching Technology / 2005 L1 - 26
- 14. Development of switchingtech. (cont.) • Computer-controlled systems – FDM was developed round 1910, but implemented in 1950’s (ca. 1000 channels transferred in a coaxial cable) – PCM based digital multiplexing introduced in 1970’s – transmission quality improved – costs reduced further when digital group switches were combined with digital transmission systems – computer control became necessary - the first computer controlled exchange put into service in 1960 (in USA) – strong growth of data traffic resulted in development of separate data networks and switches – advent of packet switching (sorting, routing and buffering) – N-ISDN network combined telephone exchange and packet data switches – ATM based cell switching formed basis for B-ISDN – next step is to use optical switching with electronic switch control – all optical switching can be seen in the horizon © P. Raatikainen Switching Technology / 2005 L1 - 27 Roadmap of Finnish networking technologies Circuit switching Packet sw UMTS GSM NMT-900 NMT-450 WWW Arpanet ---> Internet technology Data networks ISDN Digitalization of Exchanges Digital transmission Automation of long distance telephony 1955 -60 -65 © P. Raatikainen -70 -75 -80 -85 -90 Switching Technology / 2005 -95 2000 L1 - 28
- 15. Challenges of modernswitching • Support of different traffic profiles • constant and variable bit rates, bursty traffic, etc. • Simultaneous switching of highly different data rates • from kbits/s rates to Gbits/s rates • Support of varying delay requirements • constant and variable delays • Scalability • number of input/output links, link bit rates, etc. • Reliability • Cost • Throughput © P. Raatikainen Switching Technology / 2005 L1 - 29 Switching modes Switching Technology S38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2005 L1 - 30
- 16. Narrowband network evolution •Early telephone systems used analog technology - frequency division multiplexing (FDM) and space division switching (SDS) • When digital technology evolved time division multiplexing (TDM) and time division switching (TDS) became possible • Development of electronic components enabled integration of TDM and TDS => Integrated Digital Network (IDN) • Different and segregated communications networks were developed – circuit switching for voice-only services – packet switching for (low-speed) data services – dedicated networks, e.g. for video and specialized data services © P. Raatikainen Switching Technology / 2005 L1 - 31 Segregated transport UNI UNI Voice Voice Data Packet switching network Data Data Video © P. Raatikainen Circuit switching network Dedicated network Data Video Switching Technology / 2005 L1 - 32
- 17. Narrowband network evolution(cont.) • Service integration became apparent to better utilize communications resources => IDN developed to ISDN (Integrated Services Digital Network) • ISDN offered – a unique user-network interface to support basic set of narrowband services – integrated transport and full digital access – inter-node signaling (based on packet switching) – packet and circuit switched end-to-end digital connections – three types of channels (B=64 kbit/s, D=16 kbit/s and H=nx64 kbit/s) • Three types of long-distance interconnections – circuit switched, packet switched and signaling connections • Specialized services (such as video) continued to be supported by separate dedicated networks © P. Raatikainen Switching Technology / 2005 L1 - 33 Integrated transport Signaling network UNI Voice Data ISDN switch Circuit switching network UNI ISDN switch Voice Data Packet switching network Data Video © P. Raatikainen Dedicated network Switching Technology / 2005 Data Video L1 - 34
- 18. Broadband network evolution •Progress in optical technologies enabled huge transport capacities => integration of transmission of all the different networks (NB and BB) became possible • Switching nodes of different networks co-located to configure multifunctional switches – each type of traffic handled by its own switching module • Multifunctional switches interconnected by broadband integrated transmission (BIT) systems terminated onto network-node interfaces (NNI) • BIT accomplished with partially integrated access and segregated switching © P. Raatikainen Switching Technology / 2005 L1 - 35 Narrowband-integrated access and broadband-integrated transmission Signaling switch UNI © P. Raatikainen Circuit switch Packet switch Ad-hoc switch Data Video Circuit switch Packet switch ISDN switch Voice Data Signaling switch Ad-hoc switch Multifunctional switch NNI NNI Multifunctional switch Switching Technology / 2005 ISDN switch Voice Data Data Video UNI L1 - 36
- 19. Broadband network evolution(cont.) • N-ISDN had some limitations: – low bit rate channels – no support for variable bit rates – no support for large bandwidth services • Connection oriented packet switching scheme, i.e., ATM (Asynchronous Transfer Mode), was developed to overcome limitations of N-ISDN => B-ISDN concept => integrated broadband transport and switching (no more need for specialized switching modules or dedicated networks) © P. Raatikainen Switching Technology / 2005 L1 - 37 Broadband integrated transport Voice Data Video B-ISDN switch UNI © P. Raatikainen Voice Data Video B-ISDN switch NNI NNI Switching Technology / 2005 UNI L1 - 38
- 20. OSI definitions forrouting and switching Routing on L3 L4 L4 L3 L3 L3 L3 L3 L3 L2 L2 L2 L2 L2 L2 Switching on L2 L4 L4 L3 L3 L3 L3 L3 L3 L2 L2 L2 L2 L2 L2 © P. Raatikainen Switching Technology / 2005 L1 - 39 Switching modes • Circuit switching • Cell and frame switching • Packet switching – Routing – Layer 3 - 7 switching – Label switching © P. Raatikainen Switching Technology / 2005 L1 - 40
- 21. Circuit switching • End-to-endcircuit established for a connection • Signaling used to set-up, maintain and release circuits • Circuit offers constant bit rate and constant transport delay • Equal quality offered to all connections • Transport capacity of a circuit cannot be shared • Applied in conventional telecommunications networks (e.g. PDH/PCM and N-ISDN) Layer 1 Limited error detection Layer 1 Network edge Limited error detection Layer 1 Switching node © P. Raatikainen Layer 1 Network edge Switching Technology / 2005 L1 - 41 Cell switching • Virtual circuit (VC) established for a connection • Data transported in fixed length frames (cells), which carry information needed for routing cells along established VCs • Forwarding tables in network nodes Layer 2 (H) Layer 2 (L) Layer 1 Network edge © P. Raatikainen Error recovery & flow control Error & congestion control Limited error detection Layer 2 (L) Layer 2 (L) Layer 1 Layer 1 Switching node Switching Technology / 2005 Error & congestion control Limited error detection Layer 2 (H) Layer 2 (L) Layer 1 Network edge L1 - 42
- 22. Cell switching (cont.) •Signaling used to set-up, maintain and release VCs as well as update forwarding tables • VCs offer constant or variable bit rates and transport delay • Transport capacity of links shared by a number of connections (statistical multiplexing) • Different quality classes supported • Applied, e.g. in ATM networks © P. Raatikainen Switching Technology / 2005 L1 - 43 Frame switching • Virtual circuits (VC) established usually for virtual LAN connections • Data transported in variable length frames (e.g. Ethernet frames), which carry information needed for routing frames along established VCs • Forwarding tables in network nodes LLC MAC Layer 1 Network edge © P. Raatikainen Error recovery & flow control Error & congestion control Limited error detection MAC MAC Layer 1 Layer 1 Switching node Switching Technology / 2005 Error & congestion control Limited error detection LLC MAC Layer 1 Network edge L1 - 44
- 23. Frame switching (cont.) •VCs based, e.g., on 12-bit Ethernet VLAN IDs (Q-tag) or 48-bit MAC addresses • Signaling used to set-up, maintain and release VCs as well as update forwarding tables • VCs offer constant or variable bit rates and transport delay • Transport capacity of links shared by a number of connections (statistical multiplexing) • Different quality classes supported • Applied, e.g. in offering virtual LAN services for business customers © P. Raatikainen Switching Technology / 2005 L1 - 45 Packet switching • No special transport path established for a connection • Variable length data packets carry information used by network nodes in making forwarding decisions • No signaling needed for connection setup Routing & mux Layer 3 Layer 2 Layer 1 Network edge © P. Raatikainen Error recovery & flow control Routing & mux Layer 3 Layer 3 Layer 2 Layer 2 Layer 1 Layer 1 Switching node Switching Technology / 2005 Error recovery & flow control Layer 3 Layer 2 Layer 1 Network edge L1 - 46
- 24. Packet switching (cont.) •Forwarding tables in network nodes are updated by routing protocols • No guarantees for bit rate or transport delay • Best effort service for all connections in conventional packet switched networks • Transport capacity of links shared effectively • Applied in IP (Internet Protocol) based networks © P. Raatikainen Switching Technology / 2005 L1 - 47 Layer 3 - 7 switching • L3-switching evolved from the need to speed up (IP based) packet routing • L3-switching separates routing and forwarding • A communication path is established based on the first packet associated with a flow of data and succeeding packets are switched along the path (i.e. software based routing combined with hardware based one) • Notice: In wire-speed routing traditional routing is implemented in hardware to eliminate performance bottlenecks associated with software based routing (i.e., conventional routing reaches/surpasses L3-switching speeds) © P. Raatikainen Switching Technology / 2005 L1 - 48
- 25. Layer 3 -7 switching (cont.) Layer 7 Layer 7 Layer 4 Layer 3 Layer 2 ... ... Routing info • In L4 - L7 switching, forwarding decisions are based not only on MAC address of L2 and destination/source address of L3, but also on application port number of L4 (TCP/UDP) and on information of layers above L4 Flow control Routing Routing Layer 1 Network edge Layer 3 Layer 3 Layer 2 Layer 2 Layer 1 Error recovery & flow control Layer 1 Error recovery & flow control Layer 3 Layer 2 Layer 1 Switching node © P. Raatikainen Layer 4 Network edge Switching Technology / 2005 L1 - 49 Label switching • Evolved from the need to speed up connectionless packet switching and utilize L2-switching in packet forwarding • A label switched path (LSP) established for a connection • Forwarding tables in network nodes Flow control Layer 3 Layer 2 Layer 1 Network edge © P. Raatikainen Error recovery & flow control Layer 2 Layer 2 Layer 1 Layer 1 Switching node Switching Technology / 2005 Error recovery & flow control Layer 3 Layer 2 Layer 1 Network edge L1 - 50
- 26. Label switching (cont.) •Signaling used to set-up, maintain and release LSPs • A label is inserted in front of a L3 packet (behind L2 frame header) • Packets forwarded along established LSPs by using labels in L2 frames • Quality of service supported • Applied, e.g. in ATM, Ethernet and PPP • Generalized label switching scheme (GMPLS) extends MPLS to be applied also in optical networks, i.e., enables light waves to be used as LSPs © P. Raatikainen Switching Technology / 2005 L1 - 51 Latest directions in switching • The latest switching schemes developed to utilize Ethernet based transport • Scalability of the basic Ethernet concept has been the major problem, i.e., 12-bit limitation of VLAN ID • Modifications to the basic Ethernet frame structure have been proposed to extend Ethernet’s addressing capability, e.g., Q-in-Q, Mac-in-Mac, Virtual MAN and Ethernet-over-MPLS • Standardization bodies favor concepts (such as Q-in-Q and VMAN) that are backward compatible with the legacy Ethernet frame • Signaling solutions still need further development © P. Raatikainen Switching Technology / 2005 L1 - 52
- 27. Transmission techniques and multiplexinghierarchies Switching Technology S38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2005 L2 - 1 Transmission techniques and multiplexing hierarchies • Transmission of data signals • Timing and synchronization • Transmission techniques and multiplexing – – – – – – PDH ATM IP/Ethernet SDH/SONET OTN GFP © P. Raatikainen Switching Technology / 2005 L2 - 2
- 28. Transmission of datasignals • Encapsulation of user data into layered protocol structure • Physical and link layers implement functionality that have relevance to switching – – – – – multiplexing of transport signals (channels/connections) medium access and flow control error indication and recovery bit, octet and frame level timing/synchronization line coding (for spectrum manipulation and timing extraction) © P. Raatikainen Switching Technology / 2005 L2 - 3 Encapsulation of user data User data TLH NLH LLH PLH © P. Raatikainen Transport layer payload • • • • error coding/indication octet & frame synchronization addressing medium access & flow control Network layer payload Link layer payload Physical layer Switching Technology / 2005 • line coding • bit level timing • physical signal generation/ recovery L2 - 4
- 29. Synchronization of transmitteddata • Successful transmission of data requires bit, octet, frame and packet level synchronism • Synchronous systems (e.g. PDH and SDH) carry additional information (embedded into transmitted line signal) for accurate recovery of clock signals • Asynchronous systems (e.g. Ethernet) carry additional bit patterns to synchronize receiver logic © P. Raatikainen Switching Technology / 2005 L2 - 5 Timing accuracy • Inaccuracy of frequency classified in telecom networks to – jitter (short term changes in frequency > 10 Hz) – wander (< 10 Hz fluctuation) – long term frequency shift (drift or skew) • To maintain required timing accuracy, network nodes are connected to a hierarchical synchronization network – Universal Time Coordinated (UTC): error in the order of 10-13 – Error of Primary Reference Clock (PRC) of the telecom network in the order of 10-11 © P. Raatikainen Switching Technology / 2005 L2 - 6
- 30. Timing accuracy (cont.) •Inaccuracy of clock frequency causes – degraded quality of received signal – bit errors in regeneration – slips: in PDH networks a frame is duplicated or lost due to timing difference between the sender and receiver • Based on applied synchronization method, networks are divided into – fully synchronous networks (e.g. SDH) – plesiochronous networks (e.g. PDH), sub-networks have nominally the same clock frequency but are not synchronized to each other – mixed networks © P. Raatikainen Switching Technology / 2005 L2 - 7 Methods for bit level timing • To obtain bit level synchronism receiver clocks must be synchronized to incoming signal • Incoming signal must include transitions to keep receiver’s clock recovery circuitry in synchronism • Methods to introduce line signal transitions – Line coding – Block coding – Scrambling © P. Raatikainen Switching Technology / 2005 L2 - 8
- 31. Line coding 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 +V Uncoded +V ADI +V ADI RZ +V AMIRZ -V ADI - Alternate Digit Inversion ADI RZ - Alternate Digit Inversion Return to Zero AMI RZ - Alternate Mark Inversion Return to Zero © P. Raatikainen Switching Technology / 2005 L2 - 9 Line coding (cont.) • ADI, ADI RZ and codes alike introduce DC balance shift => clock recovery becomes difficult • AMI and AMI RZ introduces DC balance, but lacks effective ability to introduce signal transitions • HDB3 (High Density Bipolar 3) code, used in PDH systems, guarantees a signal transition at least every fourth bit • 0000 coded by 000V when there is an odd number of pulses since the last violation (V) pulse • 0000 coded by B00V when there is an even number of pulses since the last violation pulse 1 +V HDB3 -V © P. Raatikainen 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 V B Switching Technology / 2005 V L2 - 10
- 32. Line coding (cont.) •When bit rates increase (> 100 Mbit/s) jitter requirements become tighter and signal transitions should occur more frequently than in HDB3 coding • CMI (Coded Mark Inversion) coding was introduced for electronic differential links and for optical links • CMI doubles bit rate on transmission link => higher bit rate implies larger bandwidth and shortened transmission distance 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 +V CMI -V © P. Raatikainen Switching Technology / 2005 L2 - 11 Block coding • • • • • • Entire blocks of n bits are replaced by other blocks of m bits (m > n) nBmB block codes are usually applied on optical links by using on-off keying Block coding adds variety of “1”s and “0”s to obtain better clock synchronism and reduced jitter Redundancy in block codes (in the form of extra combinations) enables error recovery to a certain extent When m>n the coded line signal requires larger bandwidth than the original signal Examples: 4B5B (FDDI), 5B6B (E3 optical links) and 8B10B (GbE) © P. Raatikainen Switching Technology / 2005 L2 - 12
- 33. Coding examples 4B5B coding Input word 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output word 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 ©P. Raatikainen 5B6B coding Other output words 00000 11111 00100 11000 10001 01101 00111 11001 00001 00010 00011 00101 00110 01000 01100 10000 Quiet line symbol Idle symbol Halt line symbol Start symbol Start symbol End symbol Reset symbol Set Symbol Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Switching Technology / 2005 Input word Output word 00000 00001 00010 00011 ... 11100 11101 11110 11111 101011 101010 101001 111000 ... 010011 010111 011011 011100 L2 - 13 Scrambling • Data signal is changed bit by bit according to a separate repetitive sequence (to avoid long sequences of “1”s or “0”s) • Steps of the sequence give information on how to handle bits in the signal being coded • A scrambler consists of a feedback shift register described by a polynomial (xN + … + xm + … + xk + … + x + 1) • Polynomial specifies from where in the shift register feedback is taken • Output bit rate is the same as the input bit rate • Scrambling is not as effective as line coding © P. Raatikainen Switching Technology / 2005 L2 - 14
- 34. Scrambler example SDH/STM-1 usesx7+x6+1 polynomial Scrambler x Preset 0 D x 1 D Di + x 2 D x 3 D x 4 D x 5 D x x 6 D 7 D Si + Xi = Si⊕Di Xi Descrambler Xi + x0 Preset x1 x2 x3 x4 x5 x6 x7 D D D D D D D D Si + Ri = Si⊕Xi = Si⊕(Si⊕Di) = Di Ri =Di © P. Raatikainen Switching Technology / 2005 L2 - 15 Methods for octet and frame level timing • Frame alignment bit pattern • Start of frame signal • Use of frame check sequence © P. Raatikainen Switching Technology / 2005 L2 - 16
- 35. Frame alignment sequence •Data frames carry special frame alignment bit patterns to obtain octet and frame level synchronism • Data bits scrambled to avoid misalignment • Used in networks that utilize synchronous transmission, e.g. in PDH, SDH and OTN • Examples – PDH E1 frames carry bit sequence 0011011 in every other frame (even frames) – SDH and OTN frames carry a six octet alignment sequence (hexadecimal form: F6 F6 F6 28 28 28) in every frame © P. Raatikainen Switching Technology / 2005 L2 - 17 Start of frame signal • Data frames carry special bit patterns to synchronize receiver logic • False synchronism avoided for example by inserting additional bits into data streams • Used in synchronous and asynchronous networks, e.g., Ethernet and HDLC • Examples – Ethernet frames are preceded by a 7-octet preamble field (10101010) followed by a start-of-frame delimiter octet (10101011) – HDLC frames are preceded by a flag byte (0111 1110) © P. Raatikainen Switching Technology / 2005 L2 - 18
- 36. Frame check sequence •Data frames carry no special bit patterns for synchronization • Synchronization is based on the use of error indication and correction fields – CRC (Cyclic Redundancy Check) calculation • Used in bit synchronous networks such as ATM and GFP (Generic Framing Procedures) • Example – ATM cells streams can be synchronized to HEC (Header Error Control) field, which is calculated across ATM cell header © P. Raatikainen Switching Technology / 2005 L2 - 19 Transmission techniques • PDH (Plesiochronous Digital Hierarchy) • ATM (Asynchronous Transfer Mode) • IP/Ethernet • SDH (Synchronous Digital Hierarchy) • OTN (Optical Transport network) • GFP (Generic Framing Procedure) © P. Raatikainen Switching Technology / 2005 L2 - 20
- 37. Plesiochronous Digital Hierarchy(PDH) • Transmission technology of the digitized telecom network • Basic channel capacity 64 kbit/s • Voice information PCM coded • 8 bits per sample • A or µ law • sample rate 8 kHz (125 µs) • Channel associated signaling (SS7) • Higher order frames obtained by multiplexing four lower order frames bit by bit and adding some synchr. and management info • The most common switching and transmission format in the telecommunication network is PCM 30 (E1) © P. Raatikainen 139.264 Mbit/s E4 1920 channels x 4 34.368 Mbit/s E3 480 channels x 4 8.448 Mbit/s E2 120 channels x 4 2.048 Mbit/s E1 ... 64 kbit/s E0 30 channels x 32 1 channel Switching Technology / 2005 L2 - 21 PDH E1-frame structure (even frames) Multi- frame F0 F1 ... F14 Voice channels 1 - 15 T0 T1 T2 ... T0 Frame alignment time-slot C 0 0 1 1 0 1 Frame alignment signal (FAS) Error indicator bit (CRC-4) © P. Raatikainen Voice channels 16 - 30 ... T15 T16 T17 T28 T29 T30 T31 Voice channel 28 Signaling time-slot 1 F15 0 0 0 Multi-frame alignment bit sequence in F0 0 1 A 1 Multi-frame alarm Switching Technology / 2005 1 B1 Polarity B2 B3 B4 B5 B6 B7 B8 Voice sample amplitude L2 - 22
- 38. PDH E1-frame structure(odd frames) Multi- frame F0 F1 ... F14 Voice channels 1 - 15 T0 T1 T2 ... T0 Frame alignment time-slot C 1 A D Error indicator bit (CRC-4) © P. Raatikainen D D D F15 Voice channels 16 - 30 ... T15 T16 T17 T28 T29 T30 T31 Signaling time-slot D Data bits for management Far end alarm indication a b c Channel 1 signaling bits d a b c c Channel 16 signaling bits Switching Technology / 2005 Nowadays, time slot 1 used for signaling and time slot 16 for voice L2 - 23 PDH-multiplexing • Tributaries have the same nominal bit rate, but with a specified, permitted deviation (100 bit/s for 2.048 Mbit/s) • Plesiochronous = tributaries have almost the same bit rate • Justification and control bits are used in multiplexed flows • First order (E1) is octet-interleaved, but higher orders (E2, …) are bit-interleaved © P. Raatikainen Switching Technology / 2005 L2 - 24
- 39. PDH network elements •concentrator – n channels are multiplexed to a higher capacity link that carries m channels (n > m) • multiplexer – n channels are multiplexed to a higher capacity link that carries n channels • cross-connect – static multiplexing/switching of user channels • switch – switches incoming TDM/SDM channels to outgoing ones © P. Raatikainen Switching Technology / 2005 L2 - 25 Example PDH network elements ... n input channels Concentrator n>m Cross-connect DXC m output channels Switch Multiplexer n=m © P. Raatikainen m output channels 3 2 1 4 3 2 1 4 ... n input channels 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 Switching Technology / 2005 L2 - 26
- 40. Synchronous digital hierarchy 40Gbit/s STM-256 x 4 Major ITU-T SDH standards: - G.707 - G.783 10 Gbit/s STM-64 x 4 2.48 Gbit/s STM-16 x 4 Notice that each frame transmitted in 125 µs ! 622 Mbit/s STM-4 x 4 STM-1 © P. Raatikainen 155 Mbit/s Switching Technology / 2005 L2 - 27 SDH reference model DXC STM-n MPX R STM-n Regeneration section Multiplexing section STM-n Regeneration section R STM-n Tributaries Tributaries MPX Regeneration section Multiplexing section Path layer connection - DXC - MPX -R © P. Raatikainen Digital gross-connect Multiplexer Repeater Switching Technology / 2005 L2 - 28
- 41. SDH-multiplexing • Multiplexing hierarchy forplesiochronous and synchronous tributaries (e.g. E1 and E3) • Octet-interleaving, no justification bits - tributaries visible and available in the multiplexed SDH flow • SDH hierarchy divided into two groups: – multiplexing level (virtual containers, VCs) – line signal level (synchronous transport level, STM) • Tributaries from E1 (2.048 Mbit/s) to E4 (139.264 Mbit/s) are synchronized (using justification bits if needed) and packed in containers of standardized size • Control and supervisory information (POH, path overhead) added to containers => virtual container (VC) © P. Raatikainen Switching Technology / 2005 L2 - 29 SDH-multiplexing (cont.) • • • • Different sized VCs for different tributaries (e.g. VC-12/E1, VC-3/E3, VC-4/E4) Smaller VCs can be packed into a larger VC (+ new POH) Section overhead (SOH) added to larger VC => transport module Transport module corresponds to line signal (bit flow transferred on the medium) – bit rate is 155.52 Mbit/s or its multiples – transport modules called STM-N (N = 1, 4, 16, 64, ...) – bit rate of STM-N is Nx155.52 Mbit/s – duration of a module is 125 µs (= duration of a PDH frame) © P. Raatikainen Switching Technology / 2005 L2 - 30
- 42. SDH network elements •regenerator (intermediate repeater, IR) – regenerates line signal and may send or receive data via communication channels in RSOH header fields • multiplexer – terminal multiplexer multiplexes/demultiplexes PDH and SDH tributaries to/from a common STM-n – add-drop multiplexer adds or drops tributaries to/from a common STMn • digital cross-connect – used for rearrangement of connections to meet variations of capacity or for protection switching – connections set up and released by operator © P. Raatikainen Switching Technology / 2005 L2 - 31 Example SDH network elements Cross-connect STM-n STM-n STM-n DXC STM-n STM-n Add-drop multiplexer STM-n ADM Terminal multiplexer STM-n ADM 2 - 140 Mbit/s © P. Raatikainen STM-n STM-n 2 - 140 Mbit/s Switching Technology / 2005 L2 - 32
- 43. Generation of STM-1frame Justification PDH/E1 VC-12 + POH + POH © P. Raatikainen STM-1 VC-4 MUX + SOH Switching Technology / 2005 L2 - 33 STM-n frame Three main fields: – Regeneration and multiplexer section overhead (RSOH and MSOH) – Payload and path overhead (POH) – AU (administrative) pointer specifies where payload (VC-4 or VC-3) starts nx9 octets 3 AU-4 PTR 5 © P. Raatikainen RSOH 1 nx261 octets MSOH P O H Switching Technology / 2005 L2 - 34
- 44. Synchronization of payload •Position of each octet in a STM frame (or VC frame) has a number • AU pointer contains position number of the octet in which VC starts • Lower order VC included as part of a higher order VC (e.g. VC-12 as part of VC-4) VC-4 no. 0 RSOH STM-1 no. k AU-4 PTR MSOH VC-4 no. 1 RSOH STM-1 no. k+1 AU-4 PTR MSOH © P. Raatikainen VC-4 no. 2 Switching Technology / 2005 L2 - 35 ATM concept in summary • cell – 53 octets • routing/switching – based on VPI and VCI • adaptation – processing of user data into ATM cells • error control – cell header checking and discarding • flow control – no flow control – input rate control • congestion control – cell discarded (two priorities) © P. Raatikainen Switching Technology / 2005 L2 - 36
- 45. ATM protocol referencemodel AAL Convergence sublayer (CS) Segmentation and reassembly (SAR) Generic flow control ATM VPI/VCI translation Multiplexing and demultiplexing of cells Cell rate decoupling TC HEC header sequence generation/verification Cell delineation Transmission frame adaptation Phys PM Transmission frame generation/recovery © P. Raatikainen Timing Physical medium Switching Technology / 2005 L2 - 37 Reference interfaces NNI UNI EX ATM network TE NNI UNI EX TE © P. Raatikainen - Network-to-Network Interface User Network Interface Exchange Equipment Terminal Equipment Switching Technology / 2005 L2 - 38
- 46. ATM cell structure 5octets 48 octets ATM ATM header header Cell payload Cell payload ATM header for UNI GFC GFC VPI VPI VCI VCI VCI VCI HEC HEC VPI VPI VCI VCI PTI PTI CPL CPL ATM header for NNI VPI VPI VCI VCI VPI VPI VCI VCI HEC HEC © P. Raatikainen UNI NNI VPI VCI GFC PTI CPL HEC - User Network Interface - Network-to-Network Interface - Virtual Path Identifier - Virtual Channel Identifier - Generic Flow Control - Payload Type Identifier - Cell Loss Priority - Header Error Control VCI VCI PTI PTI CPL CPL HEC = 8 x (header octets 1 to 4) / (x8 + x2 + x + 1) Switching Technology / 2005 L2 - 39 ATM connection types VCI 1 VCI 2 VPI 1 VPI 1 VCI 1 VCI 2 Physical channel VCI 1 VCI 2 VPI 2 VPI 2 VCI k VPI k © P. Raatikainen VCI 1 VCI 2 - Virtual Channel Identifier k - Virtual Path Identifier k Switching Technology / 2005 L2 - 40
- 47. Physical layers forATM • SDH (Synchronous Digital Hierarchy) – STM-1 155 Mbit/s – STM-4 622 Mbit/s – STM-16 2.4 Gbit/s • PDH (Plesiochronous Digital Hierarchy) – E1 – E3 – E4 2 Mbit/s 34 Mbit/s 140 Mbit/s • TAXI 100 Mbit/s and IBM 25 Mbit/s • Cell based interface – uses standard bit rates and physical level interfaces (e.g. E1, STM-1 or STM-4) – HEC used for framing © P. Raatikainen Switching Technology / 2005 L2 - 41 Transport of data in ATM cells Network layer IP packet Pad 0 - 47 octets (1+1+ 2) octets ATM layer Physical layer © P. Raatikainen 4 octets ≤ 65 535 ATM adaptation layer (AAL) AAL 5 payload 5 H P UU/ CPI/ LEN CRC 48 Cell payload P UU CPI LEN - H Cell payload H Cell payload H Cell payload Padding octets AAL layer user-to-user indicator Common part indicator Length indicator Switching Technology / 2005 L2 - 42
- 48. ATM cell encapsulation/ SDH 9 octets 3 1 STM-1 frame 261 octets VC-4 frame SOH AU-4 PTR J1 ... B3 5 ... C2 G1 SOH F2 H4 ... ... ... Z3 Z4 ... Z5 ATM cell VC-4 POH © P. Raatikainen Switching Technology / 2005 L2 - 43 ATM cell encapsulation / PDH (E1) 32 octets TS0 Header TS16 TS0 TS16 TS0 Header TS16 TS0 TS0 Header TS16 TS16 Head. ... TS0 • frame alignment • F3 OAM functions • loss of frame alignment • performance monitoring • transmission of FERF and LOC • performance reporting © P. Raatikainen Switching Technology / 2005 TS16 • reserved for signaling L2 - 44
- 49. Cell based interface Framestructure for cell base interfaces: 1 27 P L IDLE or PL-OAM H ATM layer 2 H ATM layer 26 ... H ATM layer 27 P L IDLE or PL-OAM • PL cells processed on physical layer (not on ATM layer) • IDLE cell for cell rate adaptation • PL-OAM cells carry physical level OAM information (regenerator (F1) and transmission path (F3) level messages) • PL cell identified by a pre-defined header • 00000000 00000000 0000000 00000001 (IDLE cell) • 00000000 00000000 0000000 00001001 (phys. layer OAM) • xxxx0000 00000000 0000000 0000xxxx (reserved for phys. layer) H = ATM cell Header, PL = Physical Layer, OAM = Operation Administration and Maintenance © P. Raatikainen Switching Technology / 2005 L2 - 45 ATM network elements • Gross-connect – switching of virtual paths (VPs) – VP paths are statically connected • Switch – switching of virtual channel (VCs) – VC paths are dynamically or statically connected • DSLAM (Digital Subscriber Line Access Multiplexer) – concentrates a larger number of sub-scriber lines to a common higher capacity link – aggregated capacity of subscriber lines surpasses that of the common link © P. Raatikainen Switching Technology / 2005 L2 - 46
- 50. Ethernet • Originally alink layer protocol for LANs (10 and 100 MbE) • Upgrade of link speeds => optical versions 1GbE and 10 GbE => suggested for long haul transmission • No connections - each data terminal (DTE) sends data when ready - MAC is based on CSMA/CD • Synchronization – line coding, preamble pattern and start-of-frame delimiter – Manchester code for 10 MbE, 8B6T for 100 MbE, 8B10B for GbE © P. Raatikainen Switching Technology / 2005 L2 - 47 Ethernet frame 64 - 1518 octets Preamble S F D DA SA 7 1 6 6 T/L Payload CRC 2 46 - 1500 4 Preamble - AA AA AA AA AA AA AA (Hex) SFD - Start of Frame Delimiter AB (Hex) DA - Destination Address SA - Source Address T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator CRC - Cyclic Redundance Check Inter-frame gap 12 octets (9,6 µs /10 MbE) © P. Raatikainen Switching Technology / 2005 L2 - 48
- 51. 1GbE frame 512 -1518 octets Preamble 7 S F D DA SA 1 6 6 L 2 Payload 46 - 1500 CRC Extension 4 Preamble - AA AA AA AA AA AA AA (Hex) SFD - Start of Frame Delimiter AB (Hex) DA - Destination Address SA - Source Address T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator CRC - Cyclic Redundancy Check Inter-frame gap 12 octets (96 ns /1 GbE) Extension - for padding short frames to be 512 octets long © P. Raatikainen Switching Technology / 2005 L2 - 49 Ethernet network elements • Repeater – interconnects LAN segments on physical layer – regenerates all signals received from one segment and forwards them onto the next • Bridge – interconnects LAN segments on link layer (MAC) – all received frames are buffered and error free ones are forwarded to another segment (if they are addressed to it) • Hub and switch – hub connects DTEs with two twisted pair links in a star topology and repeats received signal from any input to all output links – switch is an intelligent hub, which learns MAC addresses of DTEs and is capable of directing received frames only to addressed ports © P. Raatikainen Switching Technology / 2005 L2 - 50
- 52. Optical transport network •Optical Transport Network (OTN), being developed by ITU-T (G.709), specifies interfaces for optical networks • Goal to gather for the transmission needs of today’s wide range of digital services and to assist network evolution to higher bandwidths and improved network performance • OTN builds on SDH and introduces some refinements: – management of optical channels in optical domain – FEC to improve error performance and allow longer link spans – provides means to manage optical channels end-to-end in optical domain (i.e. no O/E/O conversions) – interconnections scale from a single wavelength to multiple ones © P. Raatikainen Switching Technology / 2005 L2 - 51 OTN reference model OMPX OA OTS Optical channels Optical channels OMPX OA OTS OTS OMS OCh - OCh - OA - OMS - OMPX - OTS © P. Raatikainen Optical Channel Optical Amplifier Optical Multiplexing Section Optical Multiplexer Optical Transport Section Switching Technology / 2005 L2 - 52
- 53. OTN layers andOCh sub-layers SONET/ SDH ATM Ethernet IP OPU Optical channel payload unit ODU Optical channel data unit Optical channel OTU Optical channel transport unit Optical multiplexing section (OMSn) Optical transport section (OTSn) © P. Raatikainen Switching Technology / 2005 L2 - 53 OTN frame structure • Three main fields – Optical channel overhead – Payload – Forward error indication field GbE IP FR SONET/SDH ATM GbE IP ATM/FR SONET/SDH DWDM Och Payload FEC Client Digital wrapper © P. Raatikainen Switching Technology / 2005 L2 - 54
- 54. OTN frame structure(cont.) 4080 bytes 4 rows 1 16 17 ................................... Och overhead 1 1 ..... ..... 7 8 ..... 14 4 ... 4080 FEC 15 ... 16 • Frame size remains the same (4x4080) regardless of line rate => frame rate increases as line rate increases • Three line rates defined: • OTU1 2.666 Gbit/s • OTU2 10.709 Gbit/s • OTU3 43.014 Gbit/s OTU overhead OPU overh. ODU overhead 3 3825 Payload Frame alignmt. 2 3824 OTU - Optical transport unit ODU - Optical data unit OPU - Optical payload unit FEC - Forward error correction © P. Raatikainen Switching Technology / 2005 L2 - 55 Generation of OTN frame and signal OTN frame generation Client signal OPU ODU + OPU-OH OTU + OTU-OH + FEC OTN signal generation Client signal © P. Raatikainen … Client signal OCh OMUX OMS OTS OCh Switching Technology / 2005 L2 - 56
- 55. OTN network elements •optical amplifier – amplifies optical line signal • optical multiplexer – multiplexes optical wavelengths to OMS signal – add-drop multiplexer adds or drops wavelengths to/from a common OMS • optical cross-connect – used to direct optical wavelengths (channels) from an OMS to another – connections set up and released by operator • optical switches ? – when technology becomes available optical switches will be used for switching of data packets in the optical domain © P. Raatikainen Switching Technology / 2005 L2 - 57 Generic Framing Procedure (GFP) • Recently standardized traffic adaptation mechanism especially for transporting block-coded and packet-oriented data • Standardized by ITU-T (G.7041) and ANSI (T1.105.02) (the only standard supported by both organizations) • Developed to overcome data transport inefficiencies of existing ATM, POS, etc. technologies • Operates over byte-synchronous communications channels (e.g. SDH/SONET and OTN) • Supports both fixed and variable length data frames • Generalizes error-control-based frame delineation scheme (successfully employed in ATM) – relies on payload length and error control check for frame boundary delineation © P. Raatikainen Switching Technology / 2005 L2 - 58
- 56. GFP (cont.) • Twoframe types: client and control frames – client frames include client data frames and client management frames – control frames used for OAM purposes • Multiple transport modes (coexistent in the same channel) possible – Frame-mapped GFP for packet data, e.g. PPP, IP, MPLS and Ethernet) – Transparent-mapped GFP for delay sensitive traffic (storage area networks), e.g. Fiber Channel, FICON and ESCON © P. Raatikainen Switching Technology / 2005 L2 - 59 GFP frame types GFP frames Client frames Client data frames © P. Raatikainen Control frames Client management frames Idle frames Switching Technology / 2005 OA&M frames L2 - 60
- 57. GFP client dataframe • Composed of a frame header and payload • Core header intended for data link management – payload length indicator (PLI, 2 octets), HEC (CRC-16, 2 octets) • Payload field divided into payload header, payload and optional FCS (CRC-32) sub-fields • Payload header includes: – payload type (2 octets) and type HEC (2 octets) sub-fields – optional 0 - 60 octets of extension header • Payload: – variable length (0 - 65 535 octets, including payload header and FCS) for frame mapping mode (GFP-F) - frame multiplexing – fixed size Nx[536, 520] for transparent mapping mode (GFP-T) - no frame multiplexing © P. Raatikainen Switching Technology / 2005 L2 - 61 GFP frame structure Payload length indicator Core header Core HEC PFI EXI UPI Type HEC CID Payload header Payload area PTI Payload type 0 – 60 bytes extension header (optional) Spare Extension HEC MSB Extension HEC LSB Payload [N x 536, 520 bytes or variable length packet] Payload FCS CID - Channel identifier FCS - Frame Check Sequence EXI - Extension Header Identifier HEC - Header Error Check PFI - Payload FCS Indicator PTI - Payload Type Indicator UPI - User payload Identifier Source: IEEE Communications Magazine, May 2002 © P. Raatikainen Switching Technology / 2005 L2 - 62
- 58. GFP client-dependent Frame mapped Other client signals ESCON FICON Fiber Channel RPR MAPOS IP/PPP Ethernet GFP relationship toclient signals and transport paths Transparent mapped GFP client-independent SDH/SONET path ESCON FICON IP/PPP MAPOS RPR - OTN ODUk path Enterprise System CONnection Fiber CONnection IP over Point-to-Point Protocol Multiple Access Protocol over SONET/SDH Resilient Packet Ring Source: IEEE Communications Magazine, May 2002 © P. Raatikainen Switching Technology / 2005 L2 - 63 Adapting traffic via GFP-F and GFP-T GFP-F frame PLI cHEC 2 bytes 2 bytes Payload header Client PDU (PPP, IP, Ethernet, RPR, etc.) 4 bytes FCS (optional) 4 bytes GFP-T frame PLI cHEC 2 bytes 2 bytes FCS cHEC PDU PLI Payload header 4 bytes 8x64B/65B superblock #1 #2 ... #N-1 #N FCS (optional) 4 bytes - Frame Check Sequence - Core Header Error Control - Packet Data Unit - Payload Length Indicator © P. Raatikainen Switching Technology / 2005 L2 - 64
- 59. GFP-T frame mapping 64B/65Bcode block 8B 8B 8B 8B 8B 8B 8B 8B 8 x 64B/65B code blocks Superblock (8 x 64B/65B code blocks + CRC-16) CRC-16 GFP-T frame with five superblocks Core header and payload header © P. Raatikainen FCS (optional) Switching Technology / 2005 L2 - 65
- 60. Switch Fabrics Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2003 3-1 Switch fabrics • • • • • • Basic concepts Time and space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search © P. Raatikainen Switching Technology / 2003 3-2 1
- 61. Switch fabrics • • • • • Multi-point switching Self-routingnetworks Sorting networks Fabric implementation technologies Fault tolerance and reliability © P. Raatikainen Switching Technology / 2003 3-3 Basic concepts • • • • • • Accessibility Blocking Complexity Scalability Reliability Throughput © P. Raatikainen Switching Technology / 2003 3-4 2
- 62. Accessibility • A networkhas full accessibility when each inlet can be connected to each outlet (in case there are no other I/O connections in the network) • A network has a limited accessibility when the above given property does not exist • Interconnection networks applied in today’s switch fabrics usually have full accessibility © P. Raatikainen Switching Technology / 2003 3-5 Blocking • Blocking is defined as failure to satisfy a connection requirement and it depends strongly on the combinatorial properties of the switching networks Network class Network state Strict-sense non-blocking Non-blocking Network type Without blocking states Wide-sense non-blocking Rearrangeably non-blocking Blocking © P. Raatikainen With blocking state Others Switching Technology / 2003 3-6 3
- 63. Blocking (cont.) • • • • • Non-blocking -a path between an arbitrary idle inlet and arbitrary idle outlet can always be established independent of network state at set-up time Blocking - a path between an arbitrary idle inlet and arbitrary idle outlet cannot be established owing to internal congestion due to the already established connections Strict-sense non-blocking - a path can always be set up between any idle inlet and any idle outlet without disturbing paths already set up Wide-sense non-blocking - a path can be set up between any idle inlet and any idle outlet without disturbing existing connections, provided that certain rules are followed. These rules prevent network from entering a state for which new connections cannot be made Rearrangeably non-blocking - when establishing a path between an idle inlet and an idle outlet, paths of existing connections may have to be changed (rearranged) to set up that connection © P. Raatikainen Switching Technology / 2003 3-7 Complexity • Complexity of an interconnection network is expressed by cost index • Traditional definition of cost index gives the number of crosspoints in a network – used to be a reasonable measure of space division switching systems • Nowadays cost index alone does not characterize cost of an interconnection network for broadband applications – VLSIs and their integration degree has changed the way how cost of a switch fabric is formed (number of ICs, power consumption) – management and control of a switching system has a significant contribution to cost © P. Raatikainen Switching Technology / 2003 3-8 4
- 64. Scalability • Due toconstant increase of transport links and data rates on links, scalability of a switching system has become a key parameter in choosing a switch fabric architecture • Scalability describes ability of a system to evolve with increasing requirements • Issues that are usually matter of scalability – – – – – – number of switching nodes number of interconnection links between nodes bandwidth of interconnection links and inlets/outlets throughput of switch fabric buffering requirements number of inlets/outlets supported by switch fabric © P. Raatikainen Switching Technology / 2003 3-9 Reliability • Reliability and fault tolerance are system measures that have an impact on all functions of a switching system • Reliability defines probability that a system does not fail within a given time interval provided that it functions correctly at the start of the interval • Availability defines probability that a system will function at a given time instant • Fault tolerance is the capability of a system to continue its intended function in spite of having a fault(s) • Reliability measures: – MTTF (Mean Time To Failure) – MTTR (Mean Time To Repair) – MTB (Mean Time Between Failures) © P. Raatikainen Switching Technology / 2003 3 - 10 5
- 65. Throughput • Throughput givesforwarding/switching speed/efficiency of a switch fabric • It is measured in bits/s, octets/s, cells/s, packet/s, etc. • Quite often throughput is given in the range (0 ... 1.0], i.e. the obtained forwarding speed is normalized to the theoretical maximum throughput © P. Raatikainen Switching Technology / 2003 3 - 11 Switch fabrics • • • • • • Basic concepts Time and space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search © P. Raatikainen Switching Technology / 2003 3 - 12 6
- 66. Switching mechanisms • Aswitched connection requires a mechanism that attaches the right information streams to each other • Switching takes place in the switching fabric, the structure of which depends on network’s mode of operation, available technology and required capacity • Communicating terminals may use different physical links and different time-slots, so there is an obvious need to switch both in time and in space domain • Time and space switching are basic functions of a switch fabric © P. Raatikainen Switching Technology / 2003 3 - 13 Space division switching • A space switch directs traffic from input links to output links • An input may set up one connection (1, 3, 6 and 7), multiple connections (4) or no connection (2, 5 and 8) INPUTS OUTPUTS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 m INPUT LINKS © P. Raatikainen INTERCONNECTION NETWORK n OUTPUT LINKS Switching Technology / 2003 3 - 14 7
- 67. Crossbar switch matrix mINPUT LINKS • Crossbar matrix introduces the basic structure of a space switch • Information flows are controlled (switched) by opening and closing cross-points • m inputs and n outputs => mn cross-points (connection points) • Only one input can be connected to an output at a time, but an input can be connected to multiple outputs (multi-cast) at a time 1 2 3 4 5 6 7 8 MULTI-CAST A CLOSED CROSS-POINT 1 2 3 4 5 6 n OUTPUT LINKS © P. Raatikainen Switching Technology / 2003 3 - 15 An example space switch • m x1 -multiplexer used to implement a space switch • Every input is fed to every output mux and mux control signals are used to select which input signal is connected through each mux mux/connection control 1 2 m mx1 1 © P. Raatikainen mx1 2 Switching Technology / 2003 mx1 m 3 - 16 8
- 68. Time division multiplexing •Time-slot interchanger is a device, which buffers m incoming timeslots, e.g. 30 time-slots of an E1 frame, arranges new transmit order and transmits n time-slots • Time-slots are stored in buffer memory usually in the order they arrive or in the order they leave the switch - additional control logic is needed to decide respective output order or the memory slot where an input slot is stored TIME-SLOT INTERCHANGER Time-slot 1 INPUT CHANNELS 6 5 4 3 2 1 OUTPUT CHANNELS Time-slot 2 5 Time-slot 3 1 3 2 6 4 Time-slot 4 Time-slot 5 Time-slot 6 © P. Raatikainen BUFFER SPACE FOR TIME-SLOTS Switching Technology / 2003 3 - 17 Time-slot interchange BUFFER FOR m INPUT/OUTPUT SLOTS (3) 8 (2) 7 6 5 (4) (1,6) (5) 4 3 2 1 1 2 3 4 5 6 6 5 4 3 2 1 n OUTPUT LINKS m INPUT LINKS DESTINATION OUTPUT # 7 8 © P. Raatikainen Switching Technology / 2003 3 - 18 9
- 69. Time switch implementationexample 1 • Incoming time-slots are written cyclically into switch memory • Output logic reads cyclically control memory, which contains a pointer for each output time-slot • Pointer indicates which input time-slot to insert into each output time-slot … 3 2 1 Cyclic read Switch memory 1 2 3 Control memory 1 2 3 write address (3) . . . k . . . Outgoing frame buffer n … j … 2 1 Cyclic write . . . read address (k) m j (k) . . . n read/write address (j) Incoming frame buffer m Time-slot counter & R/W control © P. Raatikainen Switching Technology / 2003 3 - 19 Time switch implementation example 2 • Incoming time-slots are written into switch memory by using write-addresses read from control memory • A write address points to an output slot to which the input slot is addressed • Output time-slots are read cyclically from switch memory … 3 2 read address (3) Cyclic read 1 Control memory 1 2 3 (k) write address (k) Switch memory 1 2 3 . . . . . . k m n . . . Outgoing frame buffer n … j … 2 1 Cyclic write read/write address (2) Incoming frame buffer m Time-slot counter & R/W control © P. Raatikainen Switching Technology / 2003 3 - 20 10
- 70. Properties of timeswitches • Input and output frame buffers are read and written at wire-speed, i.e. m R/Ws for input and n R/Ws for output • Interchange buffer (switch memory) serves all inputs and outputs and thus it is read and written at the aggregate speed of all inputs and outputs => speed of an interchange buffer is a critical parameter in time switches and limits performance of a switch • Utilizing parallel to serial conversion memory speed requirement can be cut • Speed requirement of control memory is half of that of switch memory (in fact a little moor than that to allow new control data to be updated) © P. Raatikainen Switching Technology / 2003 3 - 21 Time-Space analogy • A time switch can be logically converted into a space switch by setting time-slot buffers into vertical position => time-slots can be considered to correspond to input/output links of a space switch • But is this logical conversion fair ? 1 … 3 2 © P. Raatikainen 1 n … 3 2 1 Switching Technology / 2003 2 3 … m 3 m Time switch 1 2 … Space switch m 3 - 22 11
- 71. Space-Space analogy • Aspace switch carrying time multiplexed input and output signals can be logically converted into a pure space switch (without cyclic control) by distributing each time-slot into its own space switch 1 1 … 1 1 2 1 2 … … m n n 1 2 … m 2 … 2 2 m 1 2 … Inputs and outputs are time multiplexed signals (K time-slots) n … © P. Raatikainen m 1 2 … K … To switch a time-slot, it is enough to control one of the K boxes 1 2 n Switching Technology / 2003 3 - 23 1 1 2 1 2 m … 2 … K multiplexed input signals on each link An example conversion m n mxn 1 2 KxK nxm 1 1 1 m 1 2 2 2 2 m … … K n K m © P. Raatikainen 1 2 m … 1 2 1 2 m 1 2 m Switching Technology / 2003 3 - 24 12
- 72. Properties of spaceand time switches Space switches Time switches • number of cross-points (e.g. AND-gates) - m input x n output = mn - when m=n => n2 • output bit rate determines the speed requirement for the switch components • both input and output lines deploy “bus” structure => fault location difficult © P. Raatikainen • size of switch memory (SM) and control memory (CM) grows linearly as long as memory speed is sufficient, i.e. - SM = 2 x number of time-slots - CM = 2 x number of time-slots • a simple and cost effective structure when memory speed is sufficient • speed of available memory determines the maximum switching capacity Switching Technology / 2003 3 - 25 Switch fabrics • • • • • • Basic concepts Time and space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search © P. Raatikainen Switching Technology / 2003 3 - 26 13
- 73. A switch fabricas a combination of space and time switches • Two stage switches • • • • Time-Time (TT) switch Time-Space (TS) switch Space-Time (SP) switch Space-Apace (SS) switch • TT-switch gives no advantage compared to a single stage T-switch • SS-switch increases blocking probability © P. Raatikainen Switching Technology / 2003 3 - 27 A switch fabric as a combination of space and time switches (cont.) • ST-switch gives high blocking probability (S-switch can develop blocking on an arbitrary bus, e.g. slots from two different buses attempting to flow to a common output) • TS-switch has low blocking probability, because T-switch allows rearrangement of time-slots so that S-switching can be done blocking free TS-switch ST-switch TS n TS n n © P. Raatikainen 1 2 1 2 n n … … TS n … … … … 1 2 TS 1 TS 2 TS 1 TS 1 TS 2 TS 2 … … TS 1 TS 2 TS 1 TS 1 TS 2 TS 2 TS n TS n TS n Switching Technology / 2003 1 2 n 3 - 28 14
- 74. Time multiplexed space(TMS) switch • Space divided inputs and each of them carry a frame of three time-slots • Input frames on each link are synchronized to the crossbar • A switching plane for each time-slot to direct incoming TS3 es slots to destined output ram 4 gf links of the in 2 3 om Inc corresponding 3 2 1 4 1 time-slot Outputs 1 1 e ac Sp 3 4 2 3 4 2 4x4 plane for slot 1 TS2 TS1 1 T i m e 1 2 2 3 4 4x4 plane for slot 2 Output link address 1 2 3 Cross-point closed © P. Raatikainen 4 4x4 plane for slot 3 Switching Technology / 2003 3 - 29 Connection conflicts in a TMS switch • Space divided inputs and each of them carry a frame of three time-slots • Input frames on each link are synchronized to the crossbar • A switching plane for each time-slot to direct incoming TS3 s me slots to destined output 4 fra ing 2 3 links of the om Inc 3 2 1 corresponding 4 1 time-slot Conflict solved by time-slot interchange Outputs 1 e ac Sp 3 4 2 3 4 2 4x4 plane for slot 1 TS2 TS1 1 1 4 T i m e 1 2 2 3 4 4x4 plane for slot 2 1 2 Connection conflict 3 4 4x4 plane for slot 3 Cross-point closed © P. Raatikainen Switching Technology / 2003 3 - 30 15
- 75. TS switch interconnectingTDM links 1 OUTPUTS OF 4x4 TMS SL O T 2 PL AN E FO R SL OT SPACE FO R 1 TIME PL AN E 2 3 FO R SL O T 3 • Time division switching applied prior to space switching • Incoming time-slots can always be rearranged such that output requests become conflict free for each slot of a frame, provided that the number of requests for each output is no more than the number of slots in a frame © P. Raatikainen PL AN E 3x3 TSI Switching Technology / 2003 3 - 31 SS equivalent of a TS-switch 3x3 S-SWITCH PLANES 4x4 S-SWITCH PLANES 4 PLANES 4 O UT P UT S 3 INPUTS 3 PLANES © P. Raatikainen Switching Technology / 2003 3 - 32 16
- 76. Connections through SS-switch Exampleconnections: - (1, 3, 1) => (2, 1, 2) - (1, 4, 2) => (2, 3, 4) Coordinate (X, Y, Z) stage plane input/output port 3x3 S-SWITCH PLANES 4x4 S-SWITCH PLANES (2, 1, 2) 4 PLANES (1, 3, 1) (1, 4, 2) (2, 3, 4) © P. Raatikainen Switching Technology / 2003 3 - 33 Switch fabrics • • • • • • Basic concepts Time and space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search © P. Raatikainen Switching Technology / 2003 3 - 34 17
- 77. Three stage switches •Basic TS-switch sufficient for switching time-slots onto addressed outputs, but slots can appear in any order in the output frame • If a specific input slot is to carry data of a specific output slot then a time-slot interchanger is needed at each output => any time-slot on any input can be connected to any time-slot on any output => blocking probability minimized • Such a 3-stage configuration is named TST-switching (equivalent to 3-stage SSS-switching) TS 1 TS 1 TS 2 TS 2 TS n TS n TS n TS 1 TS 2 … TS 2 … … © P. Raatikainen TS 1 … n … … 1 2 TS 1 TS 1 TS 2 TS 2 … … TST-switch: TS n TS n TS n 1 2 n Switching Technology / 2003 3 - 35 SSS presentation of TST-switch 3x3 T- or S-SWITCH PLANES 4x4 S-SWITCH PLANES 3x3 T- or S-SWITCH PLANES 4 PLANES 4 PLANES INPUTS © P. Raatikainen 3 HORIZONTAL PLANES OUTPUTS Switching Technology / 2003 3 - 36 18
- 78. Three stage switchcombinations • Possible three stage switch combinations: • Time-Time-Time (TTT) ( not significant, no connection from PCM to PCM) • Time-Time-Space (TTS) (=TS) • Time-Space-Time (TST) • Time-Space-Space (TSS) • Space-Time-Time (STT) (=ST) • Space-Time-Space (STS) • Space-Space-Time (SST) (=ST) • Space-Space-Space (SSS) (not significant, high probability of blocking) • Three interesting combinations TST, TSS and STS © P. Raatikainen Switching Technology / 2003 3 - 37 Time-Space-Space switch • Time-Space-Space switch can be applied to increase switching capacity … … n … … 1 2 TS n n TS 1 TS 2 … TS 1 TS 1 TS 2 TS 2 … … n 1 2 TS n TS n … 1 2 TS 1 TS 2 TS 1 TS 1 TS 2 TS 2 1 2 TS n TS n TS n © P. Raatikainen n Switching Technology / 2003 3 - 38 19
- 79. Space-Time-Space switch • Space-Time-Spaceswitch has a high blocking probability (like ST-switch) - not a desired feature in public networks … © P. Raatikainen … n … … 1 2 TS 1 TS 2 TS 1 TS 1 TS 2 TS 2 TS n TS n TS n Switching Technology / 2003 1 2 n 3 - 39 Graph presentation of space switch • A space division switch can be presented by a graph G = (V, E) - V is the set of switching nodes - E is the set of edges in the graph • An edge e ∈E is an ordered pair (u,v) ∈V - more than one edge can exist between u and v - edges can be consider to be bi-directional • V includes two special sets (T and R) of nodes not considered part of switching network - T is a set of transmitting nodes having only outgoing edges (input nodes to switch) - R is a set of receiving node having only incoming edges (output nodes from switch) © P. Raatikainen Switching Technology / 2003 3 - 40 20
- 80. Graph presentation ofspace switch (cont.) • A connection requirement is specified for each t ∈T by subset Rt∈R to which t must be connected - subsets Rt are disjoint for different t - in case of multi-cast Rt contains more than one element for each t • A path is a sequence of edges (t,a), (a,b), (b,c), … ,(f,g), (g,r) ∈E, ∈ t ∈T, r∈R and a,b,c,…,f,g are distinct elements of V - (T+R) • Paths originating from different t may not use the same edge • Paths originating from the same t may use the same edges © P. Raatikainen Switching Technology / 2003 3 - 41 Graph presentation example INPUT NODES t t1 t2 t3 s1 OUTPUT NODES r u1 s2 v2 u2 s4 s5 v3 r1 r2 r3 ... ... s3 v1 v4 u3 t15 v5 r15 V = (t1, t2 ,... t15, s1, s2 ,... s5 , u1, u2 , u3 , v1, v2 ,... v5 , r1, r2 ,... r15) E = {(t1, s1), ...(t15 , s5), (s1, u1), (s1, u2) ,... (s5, u3), (u1, v1 ), (u1, v2 ), ... (u3, v5 ), (v1, r1 ), (v1, r2 ),... (v5, r15)} © P. Raatikainen Switching Technology / 2003 3 - 42 21
- 81. SSS-switch and itsgraph presentation INPUTS t 3x3 S-SWITCH PLANES 5 PLANE S 5x5 S-SWITCH PLANES OUTPUTS r 3x3 S-SWITCH PLANES 5 PLANES INPUTS 3 HORIZONTAL PLANES © P. Raatikainen OUTPUTS Switching Technology / 2003 3 - 43 Graph presentation of connections INPUTS t OUTPUTS r A TREE A PATH © P. Raatikainen Switching Technology / 2003 3 - 44 22
- 82. Switch Fabrics Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2003 4-1 Switch fabrics • • • • • • Basic concepts Time and space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search © P. Raatikainen Switching Technology / 2003 4-2 1
- 83. Cost criteria forswitch fabrics • • • • • • • Number of cross-points Fan-out Logical depth Blocking probability Complexity of switch control Total number of connection states Path search © P. Raatikainen Switching Technology / 2003 4-3 Cross-points • Number of cross-points gives the number of on-off gates (usually “and-gates”) in space switching equivalent of a fabric • minimization of cross-point count is essential when cross-point technology is expensive (e.g. electro-mechanical and optical cross-points) • Very Large Scale Integration (VLSI) technology implements cross-point complexity in Integrated Circuits (ICs) => more relevant to minimize number of ICs than number of cross-points • Due to increasing switching speeds, large fabric constructions and increased integration density of ICs, power consumption has become a crucial design criteria - higher speed => more power - large fabrics => long buses, fan-out problem and more driving power - increased integration degree of ICs => heating problem © P. Raatikainen Switching Technology / 2003 4-4 2
- 84. Fan-out and logicaldepth • VLSI chips can hide cross-point complexity, but introduce pin count and fan-out problem • • • • • length of interconnections between ICs can be long lowering switching speed and increasing power consumption parallel processing of switched signals may be limited by the number of available pins of ICs fan-out gives the driving capacity of a switching gate, i.e. number of inputs (gates/cross-points) that can be connected to an output long buses connecting cross-points may lower the number of gates that can be connected to a bus Logical depth gives the number of cross-points a signal traverses on its way through a switch • large logical depth causes excessive delay and signal deterioration © P. Raatikainen Switching Technology / 2003 4-5 Blocking probability • • • Blocking probability of a multi-stage switching network difficult to determine Lee’s approximation gives a coarse measure of blocking Assume uniformly distributed load • • Probability that an input is engaged is a = λS where - λ = input rate on an input link - S = average holding time of a link © P. Raatikainen n 1 2 nxk Switching Technology / 2003 kxn 1 n ... • equal load in each input load distributed uniformly among intermediate stages (and their outputs) and among outputs 1 of the switch k 4-6 3
- 85. Blocking probability (cont.) • • • Underthe assumption of uniformly distributed load, probability that a path between any two switching blocks ≥ is engaged is p = an/k (k≥n) Probability that a certain path from an input block to an output block is engaged is 1 - (1-p)2 where the last term is the probability that both (input and output) links are disengaged Probability that all k paths between an input switching block and an output switching block are engaged is B = [1 - (1- an/k )2 ]k which is known as Lee’s approximation © P. Raatikainen Switching Technology / 2003 4-7 Control complexity • Give a graph G , a control algorithm is needed to find and set up paths in G to fulfill connection requirements • Control complexity is defined by the hardware (computation and memory) requirements and the run time of the algorithm • Amount of computation depends on blocking category and degree of blocking tolerated • In general, computation complexity grows exponentially as a function of the number of terminal • There are interconnection networks that have a regular structure for which control complexity is substantially reduced • There are also structures that can be distributed over a large number of control units © P. Raatikainen Switching Technology / 2003 4-8 4
- 86. Management complexity • • Network managementinvolves adaptation and maintenance of a switching network after the switching system has been put in place Network management deals with • failure events and growth in connectivity demand • changes of traffic patterns from day to day • overload situations • diagnosis of hardware failures in switching system, control system as well as in access and trunk network - in case of failure, traffic is rerouted through redundant built-in hardware or via other switching facilities - diagnosis and failure maintenance constitute a significant part of software of a switching system • In order for switching cost to grow linearly in respect to total traffic, switching functions (such as control, maintenance, call processing and interconnection network) should be as modular as possible © P. Raatikainen Switching Technology / 2003 4-9 Example 1 • A switch with • • • • a capacity of N simultaneous calls average occupancy on lines during busy hour is X Erlangs Y % requirement for internal use notice that two (one-way) connections are needed for a call requires a switch fabric with M = 2 x [(100+Y)/100] x(N/X) inputs and outputs. • If N = 20 000, X = 0.72 and Y = 10% => M = 2 x 1.1 x 20 000/0.72 = 61 112 => corresponds to 2038 E1 links 1 2 2 M © P. Raatikainen Switching Technology / 2003 1 M 4 - 10 5
- 87. Amount of trafficin Erlangs Erlang defines the amount of traffic flowing through a communication system - it is given as the aggregate holding time of all channels of a system divided by the observation time period • Example 1: - During an hour period three calls are made (5 min, 15 min and 10 min) using a single telephone channel => the amount of traffic carried by this channel is (30 min/60 min) = 0.5 Erlang • Example 2: - a telephone exchange supports 1000 channels and during a busy hour (10.00 - 11.00) each channel is occupied 45 minutes on the average => the amount of traffic carried through the switch during the busy hour is (1000x45 min / 60 min) = 75 Erlangs • © P. Raatikainen Switching Technology / 2003 4 - 11 Erlang’s first formula Erlang 1st formula An n! E1 (n, A) = A2 An + + 1+ A+ 2! n! Erlang 1st formula applies to systems fulfilling conditions - a failed call is disconnected (loss system) - full accessibility - time between subsequent calls vary randomly - large number of sources E1(5, 2.7) implies that we have a system of 5 inlets and offered load is 2.7 Erlangs - blocking calculated using the formula is 8.5 % Tables and diagrams (based on Erlang’s formula) have been produced to simplify blocking calculations • • • © P. Raatikainen Switching Technology / 2003 4 - 12 6
- 88. Example 2 • An exchangefor 2000 subscribers is to be installed and it is required that the blocking probability should be below 10 %. If E2 links are used to carry the subscriber traffic to telephone network, how many E2 links are needed ? - average call lasts 6 min - a subscriber places one call during a 2-hour busy period (on the average) • Amount of offered traffic is (2000x6 min /2x60 min) = 100 Erl. • Erlang 1st formula gives for 10 % blocking and load of 100 Erl. that n = 97 => required number of E1 links is ceil(97/30) = 4 © P. Raatikainen Switching Technology / 2003 4 - 13 Example 3 • • • Suppose driving current of a switching gate (cross-point) is 100 mA and its maximum input current is 8 mA How many output gates can be connected to a bus, driven by one input gate, if the capacitive load of the bus is negligibly small ? Fan-out = floor[100/8] = 12 c c • How many output gates can be connected to a bus driven by one input gate if load of the bus corresponds to 15 % of the load of a gate input) ? • Fan-out = floor[100/(1.15x8)] = 10 © P. Raatikainen Switching Technology / 2003 c 1 c 2 … M 4 - 14 7
- 89. Switch fabrics • • • • • • Basic concepts Timeand space switching Two stage switches Three stage switches Cost criteria Multi-stage switches and path search © P. Raatikainen Switching Technology / 2003 4 - 15 Multi-stage switching • Large switch fabrics could be constructed by using a single NxN crossbar, interconnecting N inputs to N outputs - such an array would require N2 cross-points - logical depth = 1 - considering the limited driving power of electronic or optical switching gates, large N means problems with signal quality (e.g. delay, deterioration) • • Multi-stage structures can be used to avoid above problems Major design problems with multi-stages - find a non-blocking structure - find non-conflicting paths through the switching network © P. Raatikainen Switching Technology / 2003 4 - 16 8
- 90. Multi-stage switching (cont.) • • • • • • • • Let’stake a network of K stages Stage k (1≤k≤K) has rk switch blocks (SB) Switch block j (1≤j≤ rk) in stage k is denoted by S(j,k) Switch j has mk inputs and nk outputs Input i of S(j,k) is represented by e(i,j,k) Output i of S(j,k) is represented by o(i,j,k) Relation o(i,j,k)= e(i’,j’,k+1) gives interconnection between output i and input i’ of switch blocks j and j’ in consecutive stages k and k+1 Special class of switches: • nk = rk+1 and mk = rk-1 • each SB in each stage connected to each SB in the next stage © P. Raatikainen Switching Technology / 2003 4 - 17 Clos network mk = number of inputs in a SB at stage k nk = number of outputs in a SB at stage k rk = number of SBs at stage k • parameter m1, n3, r1, r2, r3 chosen freely • other parameters determined uniquely by n1 = r2, m2 = r1, n2 = r3, m3 = r2 m2 = r1 = 3 n2 = r3 = 4 m = r = 5 3 2 n1 = r2 = 5 n3 = 2 m1 = 3 r1 = 3 SB = Switch Block © P. Raatikainen r2 = 5 Switching Technology / 2003 r3 = 4 4 - 18 9
- 91. Graph presentation ofa Clos network m2 = r1 = 3 n2 = r3 = 4 m3 = r2 = 5 n1 = r2 = 5 4x4 switch m1 = 3 n3 = 2 1 2 3 4 1 2 3 4 r1 = 3 r2 = 5 r3 = 4 Every SB in stage k is connected to all rk+1 SBs in the following stage k+1 with a single link. © P. Raatikainen Switching Technology / 2003 4 - 19 Path connections in a 3-stage network • • • An input of SB x may be connected to an output of SB y via a middle stage SB a Other inputs of SB x may be connected to other outputs of SB y via other middle stage SBs (b, c, …) Paull’s connection matrix is used 1ST STAGE 2ND STAGE 3RD STAGE to represent paths in three SBs SBs SBs stage switches SB a SB x SB b SB y SB c © P. Raatikainen Switching Technology / 2003 4 - 20 10
- 92. Paull’s matrix • • • Middle stageswitch blocks (a, b, c) connecting 1st stage SB x to 3rd stage SB y are entered into entry (x,y) in r1 x r3 matrix Each entry of the matrix may have 0, 1 or several middle stage SBs A symbol (a,b,..) appears as many times in the matrix as there are connections through it 1 Stage 3 switch blocks . . . . . . y 2 r3 2 . . . x a, b, c . . . Stage 1 switch blocks 1 r1 © P. Raatikainen Switching Technology / 2003 4 - 21 Paull’s matrix (cont.) Conditions for a legitimate point-to-point connection matrix: 1 Each row has at most m1 symbols, since there can be as many paths through a 1st stage SB as there are inputs to it 2 Each column has at most n3 symbols, since there can be as many paths through a 3rd stage SB as there are outputs from it 1 2 . . . 1 2 Rows . . . At most min(m1, r2) symbols in row x y . Columns . . r3 At most min(n3, r2) distinct symbols in row y x . . . r1 © P. Raatikainen Switching Technology / 2003 4 - 22 11
- 93. Paull’s matrix (cont.) Conditionsof a legitimate point-to-point connection matrix (cont.): 3 Symbols in each row must be distinct, since only one edge connects a 1st stage SB to a 2nd stage SB => there can be at most r2 different symbols 4 Symbols in each column must be distinct, since only one edge connects a 2nd stage SB to a 3rd stage SB and an edge does not carry signals from several inputs => there can be at most r2 different symbols In case of multi-casting, conditions 1 and 3 may not be valid, because a path from the 1st stage may be directed via several 2nd stage switch blocks. Conditions 2 and 4 remain valid. © P. Raatikainen Switching Technology / 2003 4 - 23 Strict-sense non-blocking Clos Definitions: • T’ is a subset of set T of transmitting terminals • R’ is a subset of set R of receiving terminals • Each element of T’ is connected by a legitimate multi-cast tree to a non-empty and disjoint subset R’ • Each element of R’ is connected to one element of T’ A network is strict sense non-blocking if any t ∈T- T’ can establish a legitimate multi-cast tree to any subset R - R’ without changes to the previously established paths. A rearrangeable network satisfies the same conditions, but allows changes to be made to the previously established paths. © P. Raatikainen Switching Technology / 2003 4 - 24 12
- 94. Clos theorem Clos theorem: AClos network is strict-sense non-blocking if and only if the number of 2nd stage switch blocks fulfills the condition r2 ≥ m1 + n3 - 1 • A symmetric Clos network with m1 = n3 = n is strict-sense nonblocking if r2 ≥ 2n - 1 © P. Raatikainen Switching Technology / 2003 4 - 25 Proof of Clos theorem Proof 1: • Let’s take some SB x in the 1st stage and some SB y in the 3rd stage, which both have maximum number of connection minus one. => x has m1 -1 and y has n3 -1 connections • One additional connection should be established between x and y • In the worst case, existing connections of x and y occupy distinct 2nd stage SBs => m1 -1 SBs for paths of x has and n3 -1 SBs for paths of y • To have a connection between x and y an additional SB is needed in the 2nd stage => required number of SBs is (m1 -1) + (n3 -1) + 1 = m1 + n3 -1 © P. Raatikainen Switching Technology / 2003 4 - 26 13
- 95. Visualization of proof 1 2 ... m1-1 1 m3 x n1 1 y 1 2 ... n3-1 ©P. Raatikainen Switching Technology / 2003 4 - 27 Paull’s matrix and proof of Clos theorem Proof 2: • A connection from an idle input of a 1st stage SB x to an idle output of a 3rd stage SB y should be established • m1-1 symbols can exist already in row x, because there are m1 inputs to SB x. • n3-1 symbols can exist already in row y, because there are n3 outputs to SB y. • In the worst case, all the (m1-1 + n3-1) symbol are distinct • To have an additional path between x and y, one more SB is needed in the 2nd stage => m1 + n3 -1 SBs are needed © P. Raatikainen Switching Technology / 2003 4 - 28 14
- 96. Procedure for makingconnections • • • • • Keep track of symbols used by row x using an occupancy vector ux (which has r2 entries that represent SBs of the 2nd stage) Enter “1” for a symbol in ux if it has been used in row x, otherwise enter “0” Likewise keep track of symbols used by column y using an occupancy vector uy To set up a connection between SB x and SB y look for a position j in ux and uy which has “0” in both vectors Amount of required computation 0 0 1 ux 0 1 1 is proportional to r2 1 2 3 j r2 common “0” uy © P. Raatikainen 1 1 1 2 0 3 0 j 1 Switching Technology / 2003 0 r2 4 - 29 Rearrangeable networks Slepian-Duguid theorem: A three stage network is rearrangeable if and only if r2 ≥ max(m1, n3) A symmetric Clos network with m1 = n3 = n is rearrangeably nonblocking if r2 ≥ n Paull’s theorem: The number of circuits that need to be rearranged is at most min(r1, r3) -1 © P. Raatikainen Switching Technology / 2003 4 - 30 15
- 97. Connection rearrangement by Paull’smatrix • If there is no common symbol (position j) found in ux and uy, we look for symbols in ux that are not in uy and symbols in uy not found in ux => a new connection can be set up only by rearrangement • Let’s suppose there is symbol a in ux (not in uy) and symbol b in uy (not in ux) and let’s choose either one as a starting point • Let it be a then b is searched from the column in which a resides (in row x) - let it be column j1 in which b is found in row i1 • In row i1 search for a - let this position be column j2 n • This procedure continues until symbol a or b cannot be found in the column or row visited 0 1 1 1 ux 1 1 1 uy © P. Raatikainen 2 a b 1 1 1 2 1 0 a b r2 1 1 r2 Switching Technology / 2003 4 - 31 Connection rearrangement by Paull’s matrix (cont.) • • • At this point connections identified can be rearranged by replacing symbol a (in rows x, i1, i2, ...) by b and symbol b (in columns y, j1, j2, ...) by a a and b still appear at most once in any row or column 2nd stage SB a can be used to connect x and y 1 j1 y j3 j2 1 r3 j1 y j3 j2 r3 1 1 i1 x a a i2 a b i1 a x b b © P. Raatikainen a i2 b a b b r1 b r1 Switching Technology / 2003 4 - 32 16
- 98. Example of connectionrearrangement by Paull’s matrix • • Let’s take a three-stage network 24x25 with r1=4 and r3=5 Rearrangeability condition requires that r2=6 - let these SBs be marked by a, b, c, d, e and f => m1 = 6, n1 = 6, m2 = 4, n2 = 5, m3 = 6, n3 = 5 6x6 1 2 4x5 1 6x5 1(a) 1 2 1 6 5 1 2 2 2(b) 1 2 2 6 5 … … … 4 1 2 6(f) 5 1 2 6 5 © P. Raatikainen Switching Technology / 2003 4 - 33 Example of connection rearrangement by Paull’s matrix (cont.) • • • In the network state shown below, a new connection is to be established between SB1 of stage 1 and SB1 of stage 3 No SBs available in stage 2 to allow a new connection Slepian-Duguid theorem => a three stage network is rearrangeable if and only if r2 ≥ max(m1, n3) - m1 = 6, n3 = 5, r2 = 6 => condition fulfilled SBs c and d are selected to operate rearrangement 1 1 1st stage SBs • f 2 a,b 3rd stage SBs 2 3 4 5 3 4 a d b,e c u1-1 c c d Occupancy vectors of SB1/stage 1 and SB1/stage 3 e,f a b,f 1 b 1 c 0 d 1 e 1 f u3-1 1 a 1 b 0 c 1 d 0 e 0 f d c 1 a © P. Raatikainen Switching Technology / 2003 4 - 34 17
- 99. Example of connectionrearrangement by Paull’s matrix (cont.) • Start rearrangement procedure from symbol c in row 1 and column 5 5 connection rearrangements are needed to set up the required connection - Paull’s theorem !!! 1st stage SBs 1 1 f 2 a,b 3rd stage SBs 2 3 4 5 3 a d c 4 d b,e c c e,f c d a © P. Raatikainen b,f 1 1st stage SBs • 1 c,f 2 a,b 3rd stage SBs 2 3 4 5 3 4 a c b,e d d e,f d d c c a b,f Switching Technology / 2003 4 - 35 Example of connection rearrangement by Paull’s matrix (cont.) • Paull’s theorem states that the number of circuits that need to be rearranged is at most min(r1, r3) -1 = 3 => there must be another solution • Start rearrangement procedure from d in row 4 and column 1 => only one connection rearrangement is needed 1 f 2 a,b 3rd stage SBs 2 3 4 5 3 4 © P. Raatikainen a d c d b,e c c e,f c d a b,f 1 1st stage SBs 1st stage SBs 1 1 c,f 2 a,b 3rd stage SBs 2 3 4 5 3 4 Switching Technology / 2003 a c d c b,e d d e,f d c a b,f 4 - 36 18
- 100. Recursive construction ofswitching networks • To reduce cross-point complexity of three stage switches individual stages can be factored further • Suppose we want to construct an NxN switching network and let N = pxq • A rearrangeably non-blocking Clos network is constructed recursively by connecting a pxp, qxq and pxp rearrangeably nonblocking switch together in respective order => under certain conditions result may be a strict-sense nonblocking network • A strict-sense non-blocking network is constructed recursively by connecting a p(2p - 1), qxq and p(2p - 1) strict-sense non-blocking switch together in respective order => result may be a rearrangeable non-blocking network © P. Raatikainen Switching Technology / 2003 4 - 37 3-dimensional construction of a rearrangeably non-blocking network q PLANES p PLANES pxp q PLANES pxp qxq Number of cross-points for the rearrangable construction is p2q + q2p + p2q = 2 p2q + q2p © P. Raatikainen Switching Technology / 2003 4 - 38 19
- 101. 3-dimensional construction ofa strictsense non-blocking network q PLANES px(2p-1) p PLANES q PLANES (2p-1)xp qxq Number of cross-points for the strictly non-blocking construction is p(2p - 1)q + q2 (2p - 1) + p (2p - 1)q = 2p(2p - 1) q + q2 (2p - 1) © P. Raatikainen Switching Technology / 2003 4 - 39 Recursive factoring of switching networks • N can be factored into p and q in many ways and these can be factored further • Which p to choose and how should the sub-networks be factored further ? • Doubling in the 1st and 3rd stages suggests to start with the smallest factor and recursively factor q = N/p using the next smallest factor => this strategy works well for rearrangeable networks => for strict-sense non-blocking networks width of the network is doubled => not the best strategy for minimizing cross-point count • Ideal solution: low complexity, minimum number of cross-points and easy to construct => quite often conflicting goals © P. Raatikainen Switching Technology / 2003 4 - 40 20
- 102. Recursive factoring ofa rearrangeably non-blocking network N INPUTS N/2 x N/2 SWITCH N/2 x N/2 SWITCH © P. Raatikainen N OUTPUTS • Special case N = 2n, n being a positive integer => a rearrangeable network can be constructed by factoring N into p = 2 and q = N/2 => resulting network is a Benes network => each stage consists of N/2 switch blocks of size 2x2 • Factor q relates to the multiplexing factor (number of time-slots on inputs) => recursion continued until speed of signals low enough for real implementations Switching Technology / 2003 4 - 41 Benes network Inverse baseline network N INPUTS N OUTPUTS Baseline network Number of stages in a Benes network K = 2log2N - 1 © P. Raatikainen Switching Technology / 2003 4 - 42 21
- 103. Benes network (cont.) • Benesnetwork is recursively constructed of 2x2 switch blocks and it is rearrangeably non-blocking (see Clos theorem) • First half of Benes network is called baseline network • Second half of Benes network is a mirror image (inverse) of the first half and is called inverse baseline network • Number of switch stages is K = 2log2N - 1 • Each stage includes N/2 2x2 switching blocks (SBs) and thus number of SBs of a Benes network is Nlog2N - (N/2) = N(log2N - ½) • Each 2x2 SB has 4 cross-points and number of cross-points in a Benes network is 4(N/2)(2log2N-1) = 4Nlog2N - 2N ∼ 4Nlog2N © P. Raatikainen Switching Technology / 2003 4 - 43 16 INPUTS 16 OUTPUTS Illustration of recursively factored Benes network © P. Raatikainen Switching Technology / 2003 4 - 44 22
- 104. Switch Fabrics Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2003 5-1 Recursive factoring of a strict-sense non-blocking network • A strict-sense non-blocking network can be constructed recursively, but the size of network (number of cross-points) crows fast as a function of the number of inputs, namely CNlog2N • Instead of starting with the smaller factor for p let’s use switch blocks of N x N • Let N = 2n and n = 2l then we are factoring square switches with number of inputs and outputs being power of 2 => condition for a strict-sense non-blocking network states that there are r2 ≥ 2x2n/2 - 1 second stage SBs • • Let choose r2 = 2x2n/2 then sizes of the - 1st stage switches are 2n/2 x 2n/2+1 - 3rd stage switches are 2n/2+1 x 2n/2 Each of these can be made of two SBs each of size 2n/2 x 2n/2 © P. Raatikainen Switching Technology / 2003 5-2 1
- 105. Recursive factoring ofa strict-sense non-blocking network (cont.) • 2nd stage switches are of size 2n/2 x 2n/2 • The three stages consist of 6x2n/2 SBs, each of size 2n/2 x 2n/2 • Let F(2n ) be the cross-point complexity of an NxN switch then • F(2n) = 6x2n/2F(2n/2 ) = 6lx2n/2+n/4+…+1F(21) < 6lx2nF(2) = N(log2N)2.58F(2) = 4N(log2N)2.58 • The difference between rearrangeable and strict-sense nonblocking networks lies in the exponent for the log2N term © P. Raatikainen Switching Technology / 2003 5-3 Strict-sense non-blocking network with smaller number of cross-points • Strict-sense non-blocking networks with smaller number of crosspoints than F(2n) = 4N(log2N)2.58 can be constructed • One alternative is to use Cantor network, which is constructed using Benes networks, multiplexers and demultiplexers • i-th input of Cantor network connected to j-th input of j-th Benes network using j-th output of a 1xm demultiplexer • i-th output of j-th Benes network connected to i-th output of Cantor network using j-th input of a mx1 multiplexer • When N is known, number of required Benes planes to have a strict-sense non-blocking Cantor network is m = log2N • Since a Benes network has a cross-point count of 4Nlog2N, number of cross-points of a Cantor network is roughly 4N(log2N)2 (when ignoring cross-points of the multiplexers and demultiplexers © P. Raatikainen Switching Technology / 2003 5-4 2
- 106. Cantor network 1 TOLOG(N) MULTIPLEXERS N INPUTS N OUTPUTS 1 TO LOG(N) DEMULTIPLEXERS © P. Raatikainen Switching Technology / 2003 5-5 Cantor network strict-sense non-blocking Proof: • Markings • m number of parallel Benes networks • k number of stage in a Benes network • A(k) number of reachable 2x2 SBs without rearrangements in stage k (1≤k≤log2N) starting from an input of a Cantor network • Reachable 2x2 SBs in consecutive stages • A(1) = m • A(2) = 2A(1) - 1 • A(3) = 2A(2) - 2 • A(k) = 2A(k-1) - 2k-2 = 22A(k-2) - 2x2k-2 = 2k-1A(1) - (k-1)x2k-2 • A(log2N) = 2log2N-1m - (log2N -1) 2log2N-2 = ½ Nm - ¼ (log N -1)N 2 © P. Raatikainen Switching Technology / 2003 5-6 3
- 107. Cantor network strict-sense non-blocking(cont.) • Cantor network is symmetrical at the middle => the same number of center stage nodes are reachable by an output of a Cantor network • Total number of SBs in center stages is Nm/2 (m Benes networks) • If the number of center stage SBs reached by an input and an output exceeds Nm/2 then there must be a SB reachable from both • Hence strict-sense non-blocking is achieved if 2 [1 Nm - 1 (log 2 N - 1)N ] > 2 4 Nm 2 => m > log2N - 1 Notice that a strict-sense non-blocking Cantor network is constructed of log2N rearrangeably non-blocking Benes networks © P. Raatikainen Switching Technology / 2003 5-7 N INPUTS N OUTPUTS Visualization of proof © P. Raatikainen Switching Technology / 2003 5-8 4
- 108. Dimensioning example ofCantor network Number of inputs and outputs of a switching network should be N = 32 x 2048 = 216 ≈ 64 000 • number of multiplexers = • number of demultiplexers = • number of Benes networks m = log2N = => number of outputs in demultiplexers = => number of inputs in Multiplexers = 64 000 64 000 16 16 16 • number of stages in Benes networks = 2log2N - 1 = 2x16-1 = 31 • number of 2x2 SBs in Benes networks = Nlog2N = 216 * 32 ≈ 2N SBs in each Benes network © P. Raatikainen Switching Technology / 2003 5-9 Control algorithms • Control algorithms for networks, which are formed recursively by three stage factorization • Control algorithms can be applied recursively • • • works well for strict-sense non-blocking networks when setting up connections one at a time for rearrangeable networks adding just one connections may cause the connection pattern to change dramatically => adding a connection to a Benes network can be as complicated as reconnecting all input-output pairs Let’s examine control algorithm for a Benes network, formed by factoring recursively • • N = 2m inputs and outputs start with a totally disconnected network and establish requested connection patterns © P. Raatikainen Switching Technology / 2003 5 - 10 5
- 109. Looping algorithm During thefirst factorization of an NxN switch each 2x2 input SB may be connected to a 2x2 output SB either via upper (U) or lower (L) N/2xN/2 switch (see figure) 1) Initialization Start with 2x2 input SB 1 and mark it by S 2) Loop forward Connect an unconnected input of S to desired output by upper switch U. If no connection is required, go to 4. 3) Loop backward Connect the adjacent output of the output just visited to the desired input by the lower switch L. If no connection is required, go to 4. Otherwise, the newly visited input SB becomes S. Go to 2. © P. Raatikainen Switching Technology / 2003 5 - 11 Looping algorithm (cont.) N INPUTS N/2 x N/2 UPPER SWITCH N/2 x N/2 LOWER SWITCH © P. Raatikainen Switching Technology / 2003 N OUTPUTS 4) Start new loop Choose another SB, which has not been visited yet as S. Go to 2. If all connections for the NxN switch are made, the algorithm terminates at level m. 5 - 12 6
- 110. Looping algorithm (cont.) • Loopingalgorithm is applied recursively to establish connections for the upper switch U and lower switch L • Computation of paths is complex and time consuming and it can be shown that the total run time of the algorithm to compute paths for all inputs and outputs is proportional to (log2N )2 Looping algorithm • suits for circuit switching, because connections computed per call • not suitable for packet switching, because connections may have to be recomputed for all N input-output pairs within duration of a packet • dedicating a processor for each input and output SB connection => computations become faster, but exchange of path information between processors gets very complicated => Alternative switching architectures needed for packet switching • © P. Raatikainen Switching Technology / 2003 5 - 13 Switch fabrics • • • • • Multi-point switching Self-routing networks Sorting networks Fabric implementation technologies Fault tolerance and reliability © P. Raatikainen Switching Technology / 2003 5 - 14 7
- 111. Graph presentation ofconnection patterns Point-to-point switching I O Multi-cast switching I One-to-one connections C = {(i,o)| i∈I, o∈O} If (i,o) ∈C and (i,o’)∈C => o=o’ If (i,o) ∈C and (i’,o) ∈C => i=i’ O One-to-many connections C = {(i,ni)| i∈I, ni⊂O} C - a logical mapping from inputs to outputs © P. Raatikainen Switching Technology / 2003 5 - 15 Graph presentation of connection patterns (cont.) I Super-concentrator Concentrator O (compact if B compact) I A A To any member in O O Β To any member in specific B One-to-one connections One-to-one connections C = {(i,o)| i∈A⊂I, o∈O} If (i,o)∈C and (i,o’)∈C => o=o’ If (i,o)∈C and (i’,o) ∈C => i=i’ C = {(i,o)| i∈A⊂I, o∈Β⊂O} If (i,o)∈C and (i,o’)∈C => o=o’ If (i,o)∈C and (i’,o)∈C => i=i’ © P. Raatikainen Switching Technology / 2003 5 - 16 8
- 112. Graph presentation ofconnection patterns (cont.) I Copy O A To any ni members in O One-to-many connections C = {(i,ni)| i∈A⊂I, Σni∈N} Order and identity of outputs ni ignored (output unspecific) © P. Raatikainen Switching Technology / 2003 5 - 17 Combinatorial bound • • • ζ(G) is log2 of the number of distinct and legitimate C realized by G R is number of cross-points in a switch fabric ζ measures combinatorial power of a graph, may bear no direct relationship to control complexity of finding a switch setting to realize a connection pattern • R2 is the number of states in a switch fabric of R cross-points => rough upper bound for the number of Cs in G is ζ≤ R • Better upper bound obtained by removing - all non-legitimate states, e.g., those in which two cross-points are feeding one output - one of states for which another state produces the same C • Such improvements not easily found © P. Raatikainen Switching Technology / 2003 5 - 18 9
- 113. Combinatorial bound (cont.) Letus look at number of different C measured as ζ realized by different connection functions • For each connection function, which defines a set of legitimate C, we may compute the logarithm of the total number of distinct C, marked by ζ • A graph G is rearrangeably non-blocking if all such C can be realized by G => we must have ζ≤ ζ(G) for rearrangeably non-blocking G It follows that by observing the number of distinct C realized by different connection functions, we can find the lower bound of complexity for any rearrangeably non-blocking fabric. © P. Raatikainen Switching Technology / 2003 5 - 19 Lower combinatorial bound for point-to-point connections • NxN switch with full connectivity (any element in I can be connected to any distinct element in O) • Obviously network that can realize all maximal connection patterns can realize less than maximal patterns • Number of C we want to realize equals to N! • Sterling’s approximation: 2π 2π => N! ≈ √ NN+½ e-N = √ exp2(Nlog2N - Nlog2e + ½log2N) => • ζpt-pt = log2N! ≈ Nlog2N - 1.44N + ½log2N = O(NlogN) If 2x2 SBs are used, at least Nlog2N such SBs are needed to realize the N! possible maximal connection patterns => A poit-to-point interconnection network has a complexity of O(NlogN) © P. Raatikainen Switching Technology / 2003 5 - 20 10
- 114. Visualization of point-to-pointmappings Number of connection patterns in point-to-point switching Lc= N! N = 2 => Lc= 2 N = 3 => Lc= 6 Construction of C: Enumerate inputs, mix them in an arbitrary order. © P. Raatikainen Switching Technology / 2003 5 - 21 Lower bound of Benes network 16 INPUTS 16 OUTPUTS • Number of 2x2 SBs in a Benes network: => 2log2N - 1 stages and each stage has N/2 SBs of size 2x2 => total number of 2x2 SBs is Nlog2N - N/2 , which is close to ζpt-pt => total number of cross-points 4(Nlog2N - N/2) ≈ 4Nlog2N © P. Raatikainen Switching Technology / 2003 5 - 22 11
- 115. Lower combinatorial boundfor multi-point connections • Let’s suppose that any input can be connected to any output, i.e., each element in O may choose any one of the N inputs => total number of connection patterns C is NN = exp2(Nlog2N) => ζmcast = Nlog2N => ζmcast - ζpt-pt = 1.44N • A fabric architecture that would implement multi-casting and would be close to the lower bound of complexity is not known yet • It is known that Benes network implements multi-cast if the number of 2x2 SBs is doubled compared to the pt-to-pt case © P. Raatikainen Switching Technology / 2003 5 - 23 Visualization of multi-cast mappings Number of connection patterns in multi-cast switching Lc= NN N = 3 => Lc= 27 etc. … © P. Raatikainen Switching Technology / 2003 5 - 24 12
- 116. Lower combinatorial boundfor concentrator • A concentrator with M inputs and N outputs (M>N) • Connection pattern C defined to be a set of any N of the M inputs • Number of these sets = M N • Sterling’s approximation: ζ concentrator = log 2 ≈ log 2 1,2 M-1+N M-1 1 M! N!(M − N)! 0,8 0,6 M M! M 2 πN(M − N)! N N (M − N) M -N 0,4 0,2 0 ≈ MH(c) 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Entropy function: H(c) = -clog2c - (1-c)log2(1-c) © P. Raatikainen Switching Technology / 2003 5 - 25 Lower combinatorial bound for concentrator (cont.) • For given C => ζconcentrator = O(M) • This lower bound is smaller by a factor of logM than that of point-topoint or multi-point networks • Although concentrators with linear complexity (linear to number of inputs) can be shown to exist, there are no known practical solutions - complicated control algorithms • It can be shown that a strict-sense non-blocking concentrator is as complex as a point-to-point non-blocking concentrator - M logM • => MlogM-fabrics are used for concentration © P. Raatikainen Switching Technology / 2003 5 - 26 13
- 117. Visualization of concentratormappings Number of connection patterns in concentrator Lc= Concentrator MxN = 4x2 => © P. Raatikainen ( M )= N M! N!(N-M)! Lc = 6 Switching Technology / 2003 5 - 27 Lower combinatorial bound for super-concentrator • • • A super-concentrator with M inputs, N outputs and K elements ≤ (K≤ M,N) Connection pattern C defined to be a legitimate set of C = (A, B) by all A and B with K elements M N K K Total number of these sets = K K ζ super −con ≈ M H + N H M N • Super concentrators more complex than concentrators • Compact super-concentrator specifies output set B once the starting position of the compact sequence is specified => there are N possible starting positions and hence K ζ super −con ≈ M H + log 2 N M © P. Raatikainen Switching Technology / 2003 5 - 28 14
- 118. Visualization of super-concentrator mappings Numberof connection patterns in super-concentrator M N M!N! Lc= K K = K!(M-K)!K!(N-K)! ( )( ) Super concentrator M=4, N=3 and K=2 => © P. Raatikainen Lc = 18 Switching Technology / 2003 5 - 29 Lower combinatorial bound for copy network • A copy network with M inputs and N outputs • Connection requests ni over all inputs i is equal to N => Number of connection patterns C equals to => ζcopy ≈ (M - 1+ N )H M −1 M −1 + N Complexity lower bound is liner in M and N © P. Raatikainen Switching Technology / 2003 5 - 30 15
- 119. Visualization of copymappings Number of connection patterns in copy network M-1+N (M-1+N)! = (M-1)!N! Lc= M-1 ( ) Copy MxN = 4x2 => Lc= 10 Lc is the number of ways N objects can be put into M bins. © P. Raatikainen Switching Technology / 2003 5 - 31 Compact super-concentrator example 16 INPUTS 16 OUTPUTS Inverse Banyan network formed by recursive 2-stage factoring using super-concentrators © P. Raatikainen Switching Technology / 2003 5 - 32 16
- 120. Two stage factoring px N/q super concentrators q M/p x q super concentrators ve r tic al pa le s p horizontal pales COMPACT SUPER CONCENTRATOR 2-stage factoring can be used to construct compact superconcentrators © P. Raatikainen Switching Technology / 2003 5 - 33 Distribution network • Mirror image of a compact super-concentrator is called a distribution network • Provided that an input-output connection pattern C = { (i,oi) } satisfies: - Compactness condition - active inputs i for the pair in C are compact in modulo fashion - Monotone condition - outputs oi to be connected to each active input are strictly increasing in i in modulo fashion a 2-stage network can be made a non-blocking one if the connection requests arrive in sorted order - one way to achieve this is to put a sorting network in front of a 2-stage network • All point-to-point connections satisfying the above two conditions can be connected using the distribution network © P. Raatikainen Switching Technology / 2003 5 - 34 17
- 121. Compact and monotoneconnection pattern Compact active inputs A modulo-wise compact set 0 N-1 1 2 N-2 3 N-3 4 Cyclically monotone outputs 0 1 2 3 4 5 0 1 2 3 4 5 © P. Raatikainen ... ... ... ... N-4 N-3 N-2 N-1 N-4 N-3 N-2 N-1 Switching Technology / 2003 5 - 35 Construction of a distribution network COMPACT SUPER CONCENTRATOR © P. Raatikainen MIRROR IMAGE Switching Technology / 2003 DISTRIBUTION NETWORK 5 - 36 18
- 122. Example of adistribution network Distribution network based on inverse Banyan network 0000 0001 0000 0001 0010 0011 0010 0011 0100 0101 0100 0101 0110 0111 0110 0111 1000 1001 1000 1001 1010 1011 1010 1011 1100 1101 1100 1101 1110 1111 1110 1111 © P. Raatikainen Switching Technology / 2003 5 - 37 Construction of copy networks • Distribution network which allows multiple connections between an input and outputs is called a copy distribution network • An input can make extra connections to outputs if the outputs connected remain monotonically increasing with respect to the inputs - Compactness condition - active inputs i for the pair in C are compact in modulo fashion - Monotone condition - each element in Oi is greater than each element in Oi’ if i >i’ in modulo fashion • Inverse of many-to-one concentrator performs the copy functions © P. Raatikainen Switching Technology / 2003 5 - 38 19
- 123. Copy distribution network DISTRIBUTIONNETWORK MONOTONE SET OF Oi MULTI-COPY INPUT © P. Raatikainen Switching Technology / 2003 5 - 39 Compact and monotone connection pattern Many-to-one concentration 0 1 2 3 4 5 0 1 2 3 4 5 One-to-many copying MIRROR IMAGE 0 1 2 3 4 5 0 1 2 3 4 5 ... ... ... ... N-4 N-3 N-2 N-1 N-4 N-3 N-2 N-1 N-4 N-3 N-2 N-1 N-4 N-3 N-2 N-1 Compact outputs Compact active inputs Cyclically monotone output sets Cyclically monotone input sets © P. Raatikainen Switching Technology / 2003 5 - 40 20
- 124. Construction of multi-castnetworks • Multi-cast networks can be constructed, e.g. by concatenating a copy network and a point-to-point network - 3-stage factorization can be applied to get a point-to-point network - resulting network consists of a concentrator, copy distribution network and Benes network => number of stages increases => total number of 2x2 SBs is 2Nlog2N • There are alternative ways to construct multi-cast networks, but they encounter the above mentioned problems - number of stages increases • Difficult to calculate connections through the fabric • Complicated fabric control algorithms • One way to solve the control problem is to use self-routing © P. Raatikainen Switching Technology / 2003 5 - 41 Switch fabrics • • • • • Multi-point switching Self-routing networks Sorting networks Fabric technologies Fault tolerance and reliability © P. Raatikainen Switching Technology / 2003 5 - 42 21
- 125. Self-routing • Self-routing isa popular principle in fast packet switching • Header of each packet contains all information needed to route a packet through a switch fabric • One or more paths may exist from an input to an output • Interconnection network has the unique path property - if the sequence of nodes connecting an input to an output is unique for all input-output pairs • An important class of networks having the unique property is the generic banyan network - NlogN complexity - only one path connecting each input-output pair © P. Raatikainen Switching Technology / 2003 5 - 43 Examples of unique route network Banyan network Shuffle exchange (Omega) network © P. Raatikainen Baseline network Flip network (inverse shuffle exchange) Switching Technology / 2003 5 - 44 22
- 126. Self-routing principle • S1,S2 , … SK is a sequence of switch blocks, which have n1, n2, … nK outputs respectively • Route of a packet uses the bk-th output of switch block k => route given by the sequence b1 b2 … bk … bK • At switch block k, packet routed to output bk and address bk is removed from the self-routing header Self-routing address bK ... b1 1 2 Self-routing address bK ... b2 Self-routing address bK 1 2 1 2 ... ... ... b1 b2 bK © P. Raatikainen ... ... ... n1 n2 Switch block S1 nK Switch block S2 Switch block SK Switching Technology / 2003 5 - 45 Self-routing principle (cont.) • In a self-routing shuffle exchange (NxN) network - N = 2K inputs and outputs interconnected by K stages of 2K-1 nodes - nodes numbered in each stage from 0 to 2K-1-1 (binary K-1 format) - links (= edges) in each stage numbered from 0 to 2K-1 (binary K format) - outgoing links numbered by appending “0” (up going links) or “1” (down going links) to the node’s number 00 010 011 01 100 101 10 110 111 00 11 Edge 011 © P. Raatikainen 00 000 001 01 01 010 011 10 10 100 101 11 UP =0 1 N= W DO 000 001 11 110 111 Edge 110 Switching Technology / 2003 5 - 46 23
- 127. Self-routing in ashuffle exchange network • Self-routing shuffle exchange scheme - a packet at input a1a2 … aK is destined to output b1b2 … bK - b1b2 … bK is used as the self-routing address (up link chosen if bk=0 and down link if bk=1) - packet visits first node a2…aK => travels along edge a2…aKb1 => visits node a3…aKb1 =>… = finally after visiting node b1…bn-1 arrives at output edge b1…bn > 000 001 00 00 00 000 001 010 011 01 01 01 010 011 100 101 10 10 10 110 111 11 11 Source 0 1 100 101 110 111 001 Edge 1 © P. Raatikainen 011 11 Edge 2 110 Edge 3 0 Destination 1 0 1 Edge 1 Edge 2 Edge 3 Edge 4 Edge 4 Switching Technology / 2003 5 - 47 Monotone and compact addresses • Top-down numbering of nodes and links can be used also for other self-routing networks having the unique property • If self-routing addresses of packets at the inputs satisfy conditions: • addresses are strictly monotone in the sense that destination addresses are strictly increasing in top-down manner at the inputs • packets are compact in the sense that there is no idle input between any two inputs with packets => self-routing paths used by these packets do not share any link within the shuffle exchange network => no need for buffering at inputs of the internal nodes © P. Raatikainen Switching Technology / 2003 5 - 48 24
- 128. Limitations of banyannetworks • Banyan network can realize exp2(½Nlog2N) = (NN)½ input-output permutations (connection patterns) • Full connectivity requires N! connection patterns => Banyan network is a blocking one • Combinatorial power of banyan network can be increased significantly by implementing - multiple links between nodes - duplicated switch - appended switch with random routing (shuffle) - buffering at intermediate nodes (=> undesirable random delay) © P. Raatikainen Switching Technology / 2003 5 - 49 25
- 129. Switch Fabrics Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2003 6-1 Switch fabrics • • • • • Multi-point switching Self-routing networks Sorting networks Fabric implementation technologies Fault tolerance and reliability © P. Raatikainen Switching Technology / 2003 6-2 1
- 130. Sorting networks • Typesof blocking • Internal blocking • Output blocking • Head of line blocking • Sorting to remove internal blocking • Resolving output conflicts • Easing of HOL blocking © P. Raatikainen Switching Technology / 2003 6-3 Internal blocking • Internal blocking occurs at the internal links of a switch fabric • In a switch fabric, which implements synchronous slot timing, internal blocking implies that some input (i) to output (j) connection cannot be established (even if both are idle ones) • Internally non-blocking switch makes all requested connections (i, ji), provided that there are no multiple request to the same output (ji ≠ ji’ if i ≠ i’, 1≤i,j≤N) Input Dest. Output i 1 2 3 4 ji 1 4 3 j 1 2 3 4 Connection pattern = {(2, 1), (3, 4), (4, 3)} © P. Raatikainen Switching Technology / 2003 6-4 2
- 131. Output blocking • Internallynon-blocking switch can block at an output of a switch fabric due to conflicting requests, i.e., ji = ji’ for some i ≠ i’ • When output conflict occurs, switch should connect one of the conflicting inputs to requested output => output conflict resolution • Major distinction between a circuit and packet switching node • a packet switching node must solve output conflicts per time-slot (timeslots are not assigned beforehand) Input Dest. Output • a circuit switching node solves i ji j possible output conflicts and 3 1 1 assigns a time-slot for entire 1 2 2 duration of a connection 4 3 3 beforehand 3 4 4 Conflicting output request © P. Raatikainen Switching Technology / 2003 6-5 Head of line (HOL) blocking • Packets not forwarded due to output conflict are buffered => more delay experienced • Buffered packets normally served in a FCFS (First Come First Served) manner => HOL blocking introduced at the input queues • Packet facing HOL blocking may prevent the next packet in Input Dest. i ji the queue to be delivered to 2 3 1 a non-contended output 4 1 2 => throughput of a switch 3 4 3 reduced 4 1 2 3 1 3 Packet blocked by HOL queuing © P. Raatikainen Output j Switching Technology / 2003 4 Conflicting output request 6-6 3
- 132. Sorting to removeinternal blocking • If connection requests at the inputs of a banyan network are compact and in strictly increasing order => input-output paths are link-disjoint => banyan internally non-blocking • A method for building an internally non-blocking network is to apply a sorting network in front of a banyan network to generate a strict increasing order of destination addresses for the banyan network • A sorting network connects an input i, which has a connection request to output ji, to an output of a sorting network according to the position of ji in the sorted list of destination requests (see figure) • Sorting networks can be formed by interconnecting nodes of smaller sorting networks (such as 2x2) • Self-routing should be applied in the sorting network © P. Raatikainen Switching Technology / 2003 6-7 Internally non-blocking and self-routing switch Input Dest. i ji 1 2 3 4 Compact and monotone output addresses 1 1 4 2 3 3 4 Sorting network (Batcher) © P. Raatikainen 1 3 4 Output j Routing network (Banyan) Switching Technology / 2003 6-8 4
- 133. Sorting to removeinternal blocking • A permuted list (a1, a2 , …, aN) can be restored to its original order by sorting • A switching network for a maximal connection pattern can be obtained from a sorting network by treating 2x2 sorting elements as 2x2 switching elements • Asymptotic lower bound for 2x2 sorting elements to build a NxN sorting network is Nlog2N (as for a respective switching network) - no sorting network found so far to obtain this bound • Sequential merge-sorting process can be used to obtain Nlog2N bound for the number of binary sorts © P. Raatikainen Switching Technology / 2003 6-9 Merge-sorting algorithm Merge-sorting algorithm • Input : unsorted list AN = (a1, a2 , …, aN) • Sort procedure: Sort (AN) = Merge {Sort(a1, …, a½N), Sort (a½N+1 , …, aN)} • Merge procedure: Merge {(a1, …, am), (a’1, …, a’m’)} = {a1, (Merge ((a2, …, am), (a’1, …, a’m’))} if a1≤ a’1 = {a’1, (Merge ((a1, …, am), (a’2, …, a’m’))} if a1> a’1 • Procedure Merge, called by procedure Sort, takes two sorted lists and merges them by comparing the smallest elements in each of the two sorted lists © P. Raatikainen Switching Technology / 2003 6 - 10 5
- 134. Merge-sorting algorithm (cont.) •Merging of two sorted lists (N/2 numbers in each) requires N binary sorts • Total complexity of sorting N numbers is given by C(N) = 2C(N/2) = N + 2(N/2 + 2C(N/4)) = … = Nlog2N • Due to sequential nature of procedure Merge the sorting takes at least O(N) time 1 4 6 10 11 15 17 20 © P. Raatikainen Compare numbers at the top of lists then merge 2 5 7 9 12 14 16 24 Switching Technology / 2003 6 - 11 Odd-even merging Recursive construction of an odd-even merger ... ¥ ¥ ... ... ... e0 e1 e2 e3 e4 eN/2-5 eN/2-4 eN/2-3 eN/2-2 eN/2-1 cN/2-2 cN/2-1 Odd merger N/2 dN/2-3 ... bN/2-4 bN/2-3 bN/2-2 bN/2-1 ... ... ... d0 d1 ... b0 b1 © P. Raatikainen ¥ ¥ ... aN/2-2 aN/2-1 Even merger N/2 c0 c1 c2 ... a0 a1 a2 a3 ... - number of sorting stages is log2N - number of sorting elements is 0.5N [log2N-1]+1 dN/2-2 dN/2-1 Switching Technology / 2003 6 - 12 6
- 135. Bitonic list • Bitoniclist AN = (a1, a2 , …, aN) is a list for which it holds that a1 ≤ a2 ≤ … ≤ ak-1 ≤ ak and ak ≥ ak+1 ≥ … ≥ aN-1 ≥ aN (1≤ k ≤ N) • Unique cross-over property - when comparing a monotonically increasing list with a monotonically decreasing list, there is at most one position where the two lists cross-over in their values (see figures) Bitonic list 1 4 6 10 11 15 17 20 Cross-over © P. Raatikainen < > Circular bitonic list 24 16 14 12 9 7 5 2 17 20 24 16 14 12 9 7 > < 5 2 1 4 6 10 11 15 Cross-over Switching Technology / 2003 6 - 13 Bitonic merging Recursive construction of a bitonic merger - number of sorting stages is log2N - number of sorting elements is 0.5N log2N dN/2-3 dN/2-2 dN/2-1 ... Bitonic merger N/2 Switching Technology / 2003 ... eN/2 eN/2+1 ... ... ¥ ¥ ... © P. Raatikainen d0 d1 eN/2-2 eN/2-1 ... ... cN/2-2 cN/2-1 aN/2 aN/2+1 aN-2 aN-1 Bitonic merger N/2 e0 e1 ... ... c0 c1 c2 ... ... aN/2-2 aN/2-1 ¥ ¥ a0 a1 eN-2 eN-1 6 - 14 7
- 136. Sorting by merging Recursiveconstruction of a sorting by merging network - number of sorting stages is 0.5Nlog2N(log2N + 1) ¥ ¥ Merger N/2 ¥ ¥ ¥ © P. Raatikainen Merger N ... Merger N/4 ... Merger N/2 ¥ Merger N/4 ... ... aN-2 aN-1 Merger N/4 ¥ aN/2 aN/2+1 e0 ¥ aN/2-1 ... ... ... aN/2-2 Merger N/4 ¥ a1 ¥ a0 eN-1 Switching Technology / 2003 6 - 15 Odd-even sorting network example • Number of sorting stages is 0.5log2N(log2N + 1) • Number of sorting elements is 0.25N[log2N(log2N - 1) + 4] - 1 2x2 SORTER 4x4 SORTER 8x8 SORTER ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ © P. Raatikainen 2x2 UP SORTER 2x2 DOWN SORTER Switching Technology / 2003 6 - 16 8
- 137. Bitonic sorting networkexample • Number of sorting stages is 0.5log2N(log2N + 1) • Number of sorting elements is 0.25Nlog2N(log2N + 1) ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ © P. Raatikainen ¥ ¥ ¥ ¥ 2x2 UP SORTER ¥ ¥ ¥ ¥ 8x8 SORTER ¥ 4x4 SORTER ¥ 2x2 SORTER 2x2 DOWN SORTER Switching Technology / 2003 6 - 17 Batcher-Banyan self-routing network ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ 8x8 ROUTER ¥ ¥ ¥ 8x8 BITONIC SORTER ¥ 4x4 BITONIC SORTER ¥ 2x2 BITONIC SORTER © P. Raatikainen 2x2 UP SORTER ROUTING NETWORK ¥ ¥ SORTING NETWORK 2x2 DOWN SORTER Switching Technology / 2003 6 - 18 9
- 138. Resolving output blocking •Packet switches do not maintain a scheduler for dedicating time-slots for packets (at the inputs) => output conflicts possible => output conflict resolution needed on slot by slot basis • Output conflicts solved by • polling (e.g. round robin, token circulation) - do not scale for large numbers of inputs - outputs just served have an unfair advantage in getting a new time-slot • sorting networks (making a banyan network internally non-blocking) • An example of sorting networks is sort-purge-concentrate network • when sorting self-routing addresses, duplicated output requests appear adjacent to each other in the sorted order (see figure) - either one has to be purged (deleted) - successful delivery is acknowledged and purged packets are re-sent © P. Raatikainen Switching Technology / 2003 6 - 19 Sort-purge-concatenate network • A sorting network can easily handle packet priority by - adding a priority field in the self-routing address - higher priority packets are placed in a favorable position before purging - support of priority is an essential feature when integrating circuit and packet switching in a sort-banyan network Input i 1 2 3 4 Dest. ji Sorted destination addresses Compact and sorted output addresses 3 1 1 1 3 3 4 3 4 3 4 Sorting network © P. Raatikainen Output j 1 2 3 4 Purge network Concentration network Switching Technology / 2003 Routing network (Banyan) 6 - 20 10
- 139. Resolving HOL blocking •HOL blocking solved by • allowing packets behind a HOL packet to contend for outputs • allow multiple delivery of conflicting HOL packets to an output buffer - multiple rounds of arbitration for sort-banyan network - multiple planes of sort-banyan networks • a good solution is to implement multiple input buffers (one for each output if possible) and if the packet in turn cannot be transmitted due to HOL, transmit an other packet from another buffer © P. Raatikainen Switching Technology / 2003 6 - 21 Construction of a multipoint packet switch In a self-routing multipoint switch - incoming packets destined to multiple outputs - packets carry all destination addresses in their headers COPY NETWORK COMPACT SUPER CONCENTRATOR © P. Raatikainen COPY DISTRIBUTION NETWORK Switching Technology / 2003 ROUTING NETWORK BANYAN SWITCH 6 - 22 11
- 140. Batcher-Banyan example ¥ ¥ ¥ ¥ ¥ 4 6 7 - 1 1 1 - 2 3 - 1 3 2 3 2 4 - 2 3 6 6 - 4 7 - 4 - - 7 6 6 - 4 7 7 ¥ - 3 ¥ 7 1 ¥ 6 2 ¥ 1 1 8x8 ROUTER ¥ 1 2 4 ¥ 2 6 2 ¥ 1 7 ¥ 7 7 4 3 ¥ - - ¥ 2 6 3 ¥ 3 3 ¥ 6 4 ¥ - 8x8 BITONIC SORTER ¥ 4 ¥ 110/ ***(-) 111/001 (1) ¥ 100/111 (7) 101/010 (2) 4x4 BITONIC SORTER ¥ 010/ *** (-) 011/011 (3) ¥ 000/110 (6) 001/100 (4) 2x2 BITONIC SORTER ¥ Source/dest. © P. Raatikainen 2x2 UP SORTER ROUTING NETWORK ¥ ¥ SORTING NETWORK 2x2 DOWN SORTER Switching Technology / 2003 6 - 23 Switch fabrics • • • • • Multipoint switching Self-routing networks Sorting networks Fabric implementation technologies Fault tolerance and reliability © P. Raatikainen Switching Technology / 2003 6 - 24 12
- 141. Fabric implementation technologies •Time division fabrics • Shared media • Shared memory • Space division fabrics • Crossbar • Multi-stage constructions • Buffering techniques © P. Raatikainen Switching Technology / 2003 6 - 25 Time division fabrics • Shared media • Bus architectures • Ring architectures Shared memory © P. Raatikainen Switching Technology / 2003 • 6 - 26 13
- 142. Shared bus Bus architecture •Switching in time domain, but time and space switching implementations enabled • Easy to implement and low cost (cost index = N) • One time-slot carried through the bus at a time => limited throughput (multi-casting possible) => low number of line interfaces => limited scalability Line Interface #1 Line Interface #2 Line Interface #3 ... Line Interface #n Bus control © P. Raatikainen Switching Technology / 2003 6 - 27 Shared bus (cont.) Bus architecture • Internally non-blocking implementations require high capacity switching bus => throughput ≥ aggregate capacity of line interfaces • Inherently a single stage switch, but TST-switching possible if linecards support time-slot interchange • Multiple-bus structures can be used to improve reliability and increase throughput Bus 1 Line Interface #1 Line Interface #2 Line Interface #3 ... Line Interface #n Bus control Bus 2 © P. Raatikainen Switching Technology / 2003 6 - 28 14
- 143. Ring architectures Ring architecture •Rings coarsely divided into source and destination release rings – in source release (SR) rings only one switching operation in progress at a time => limited throughput (like a shared bus) – destination release (DR) rings allow spatial reuse, i.e., multiple time-slots can be carried through the ring simultaneously => improved throughput • Switching in time domain, but time and space switching implementations enabled • Usually easy to implement and low cost (cost index = N) • Scales better than a shared bus © P. Raatikainen Switching Technology / 2003 6 - 29 Ring architectures (cont.) Ring architecture • Internally non-blocking implementations require that throughput of a ring bus ≥ aggregate capacity of line interfaces • Throughput can be improved by implementing parallel ring buses - control usually distributed => MAC implementations may be difficult • Multi-casting relatively easy to implement • Inherently a single stage switch, but TSTswitching possible if line-cards support timeslot interchange • Multiple rings can be used to implement switching networks © P. Raatikainen Switching Technology / 2003 6 - 30 15
- 144. Ring architectures (cont.) Dualring architecture • Multiple rings used to improve throughput, decrease internal blocking, improve scalability and increase reliability © P. Raatikainen Switching Technology / 2003 6 - 31 Shared memory Shared memory architecture • Switching in time domain, but time and space switching implementations enabled • Inherently a single stage switch, but allows TST-switching if linecards support time-slot interchange • Easy to implement and low cost (cost index = N) Line Interface #1 Line Interface #2 Line Interface #3 ... Line Interface #n CPU Buffer memory Bus © P. Raatikainen Switching Technology / 2003 6 - 32 16
- 145. Shared memory (cont.) Sharedmemory architecture • Every time-slot carried twice through the bus => low throughput => low number of line interfaces => limited scalability • Internally non-blocking if throughput of a switching bus and speed of shared memory ≥ aggregate capacity of line interfaces • Performance can be improved by dual bus architecture or replacing the bus with a space switch (such as crossbar) © P. Raatikainen Switching Technology / 2003 6 - 33 Shared memory (cont.) Shared memory architecture • • Dual-bus architecture improves throughput, decreases internal blocking, improves scalability and increases reliability Memory speed requirement equal to that of single bus solutions Bus 1 Line Interface #1 Line Interface #2 Line Interface #3 ... Line Interface #n CPU Buffer memory Bus 2 © P. Raatikainen Switching Technology / 2003 6 - 34 17
- 146. Dimensioning example A sharedmemory architecture, which uses a shared bus to connect line interfaces to the memory, is used to implement a switching equipment. The bus is 32 bits wide and bus clock is 150 MHz. Three clock cycles are needed to transfer a 32 bit word through the bus and 20 % of the bus capacity is used for other than switching purposes. How many E1 interfaces can be supported by the switch ? What is the required memory speed ? Solution: If the bus transfers an eight bit time-slot (of a 64 kbit/s PDH channel) across the bus at a time, a single bus solution can transfer 0.8x(150/3) Mbytes/s = 40 Mbytes/s © P. Raatikainen Switching Technology / 2003 6 - 35 Dimensioning example (cont.) Solution (cont.): In a single bus solution, half of the bus capacity (20 Mbytes/s) is used for storing time-slots to memory and another half for reading time-slots from memory => memory speed requirement is 1/(20 Mbytes/s) = 50 ns => during a 125 µs period (= duration of an E1 frame) the bus switches 125x20 bytes = 2500 time-slots and the number of supported E1 links is 2500/32 ≈ 78 Throughput of the switching system can be increased by adding a 32 bit receive-register to the shared switch memory block, which enables to transfer 4 time-slots (in parallel) through the bus at a time. By doing so, the throughput of the bus gets four fold and the number of supported E1 links increases to 312. Time-slots are still written one by one to the switch memory, and thus the memory speed requirement is 12.5 ns. © P. Raatikainen Switching Technology / 2003 6 - 36 18
- 147. Space division fabrics • • ©P. Raatikainen Crossbar Multi-stage constructions Switching Technology / 2003 6 - 37 Crossbar Crossbar architecture • Inherently a space division switch • Allows to build TST-switches if interfaces implement time-slot interchange functionality • Hard to implement large switches due to complicated control schemes => high cost (cost index = N2) • Commercial high-speed NxN crossbar components enable modular and relatively inexpensive fabric constructions, but still control of the switch is a problem © P. Raatikainen Switching Technology / 2003 6 - 38 19
- 148. Crossbar (cont.) Crossbar architecture •Inherently a strict-sense non-blocking fabric architecture • Possible to carry N time-slots through the switch at a time => high throughput => possible to implement a large number of line interfaces => scales well within the limits of available modular components => scaling up means increase of cross-point count from NxN to to (N+k)x (N+k) Switch control • Multi-casting easy to implement © P. Raatikainen Switching Technology / 2003 6 - 39 Crossbar (cont.) Example implementation of a crossbar 1 Inputs c AND c AND ... c AND ... c ... c AND 2 ... c AND c AND ... ... ... m c AND c 1 C - connection control © P. Raatikainen AND 2 ... AND n Outputs Switching Technology / 2003 6 - 40 20
- 149. Crossbar (cont.) An 8x8switch constructed of four 4x4 crossbar blocks Notice that doubling of input/output count increases the number of crossbar components from one to four. © P. Raatikainen Switching Technology / 2003 6 - 41 Multi-stage building blocks • Multi-stage switches usually constructed of 2x2 switching blocks • Implemented usually in FPGAs (Field Programmable Gate Arrays) and/or ASICs (Application Specific Integrated Circuit) • FPGA for experimental use and low volume production • ASICs for high volume production • Batcher-banyan network most popular • Used to implement space division In1 switching In2 • Allows to build TST-switches if In3 In4 interfaces implement time-slot In5 interchange functionality X X Out1 Out2 In1 In2 Out1 In1 X Out1 Out2 X Out3 Out4 In6 Out2 In2 X Out5 Out6 In7 In8 © P. Raatikainen X Out2 Switch network In2 composed of Out1 2x2 blocks In1 X Out1 Out2 In1 In2 X Out7 Out8 Switching Technology / 2003 6 - 42 21
- 150. Multi-stage building blocks(cont.) • Hard to implement large circuit switches due to complicated control schemes (especially rearrangeable fabrics) => high cost (cost index ∼ CNlog2N) • Suitable for packet switching when self-routing functionality included • Fixed duration time-slot implementations favored to obtain strictsense non-blocking fabrics • Possible to carry N time-slots through the switch at a time => relatively high throughput => scalable only if larger networks can be factored using smaller NxN components => scaling up means increase of cross-point count from ∼ CNlog2N to ∼ C(N+k)log2(N+k) In1 In2 © P. Raatikainen X Out1 Out2 Switching Technology / 2003 6 - 43 Problems with multi-stages • Path search required • Fast connection establishment implies need for fast control system => part of switching capacity is lost if control system is not fast enough • Multi-cast is not self evident, because multi-cast complicates path search and control scheme and increases blocking probability • Multi-slot connections (i.e. several slots used for a particular connection) complicate matters - especially if path delay is not constant, e.g., slots belonging to the same connection may arrive to outputs in different order than they were at the inputs - blocking increases © P. Raatikainen Switching Technology / 2003 6 - 44 22
- 151. Trends in fabrictechnologies • Memory technology getting faster and faster • Current SRAM (Static Random Access Memory) technology allows easy implementations of large PDH switches, e.g. full matrix for 8000 E1 (2M) PDH circuits - bigger fabrics hardly needed in narrow band networks => in narrow band networks the trend over the last 10 years has been to build full matrix fabrics based on shared memory • However, when striving for broadband communications, memory based switch fabrics do not scale to bandwidth needed => multi-stage and crossbar switches have their change © P. Raatikainen Switching Technology / 2003 6 - 45 Trends in fabric technologies (cont.) • Multistage fabrics were “reinvented” at the advent of ATM - ATM suits perfectly for fixed length time-slot switching - self-routing and sorting applies for ATM cell routing - blocking and buffering causes headache => in spite of huge research effort, there have been very few commercial multi-stage fabrics available (mostly proprietary ASICs) • Development of IC technologies, increased packing density (number of gates/chip) and increased speed, have enabled crossbar fabrics suitable for high-speed switching applications (N = 2 … 64 and line rate 2.5 … 40 Gbit/s) - examples: Cx27399/Mindspeed, ETT1/Sierra, CE200/Internet Machines and PI140xx/Agere • Packet switching and advent of optical networking favors multistages and crossbars => packet switching introduces a new problem - buffering © P. Raatikainen Switching Technology / 2003 6 - 46 23
- 152. Technological tradeoffs inswitch fabric design • When trying to simplify path search and to speed up connection establishment => bus speed increases (inside fabric) => faster memory required => power consumption increases => integration level of a cross-point product needs to be increased => faster memory required, etc. Memory speed Bus speed => crossbar fabrics (for small switches) => multistage fabrics (for large switches) - real switching capacity may be less than theoretical - minimization of cross-point count often pointless Level of crosspoint integration • If fast memory not available, use Complexity of path search © P. Raatikainen Switching Technology / 2003 6 - 47 Electronic design problems • Signal skew - caused by long signal lines with varying capacitive load inside switch fabric and/or on circuit boards • Mismatching line termination - caused by long signal lines combined with varying (high) bit rates • Varying delay on bus lines - caused by differently routed bus lines (nonuniform capacitive load) • Crosstalk - caused by electro-magnetic coupling of signals from adjacent signal lines • Power feeding and voltage-swing - incorrectly dimensioned power source/lines cause non-uniform voltage and lack of adequate filtering causes fluctuation of voltage • Mismatching timing signals - different line lengths from a centralized timing source cause phase shift and distributed timing may suffer from lack of adequate synchronization © P. Raatikainen Switching Technology / 2003 6 - 48 24
- 153. Some design limitations •Speed of available components vs. required wire speed and slot time interval • Component packing density and power consumption vs. heating problem • Maximum practical fan-out vs. required size of fabric • Required bus length inside switch fabric - long buses decrease internal speed of fabric - diagnostics get difficult • IPR policy - whether company wants to use special components or more general all-purpose components © P. Raatikainen Switching Technology / 2003 6 - 49 Design optimization example • An NxN switch fabric is to be designed and there are three alternative crossbar components a, b and c available - a is an NaxNa fabric component - b is an NbxNb fabric component - c is an NcxNc fabric component and Na<Nb<Nc≤N • Component a has entered the market at time ta, b at time tb and c at time tc • Product development starts at tpd and the switch product should come in the market at tm. Components are expected to be available when the product development starts => ta < tb < tc ≤ tpd < tm • Price of a component develops with time and is generally given by P(t)=Cf(t) + D, where Cf(t) is a time dependent and D a constant part of component’s price • Question: Which one of the three components to choose for constructing an NxN switch fabric ? © P. Raatikainen Switching Technology / 2003 6 - 50 25
- 154. Design optimization example(cont.) • As an example, let’s assume that price of each component is a function of time and is given by P(t)=Ce-t/T+ D , where C, D and T are component specific constants => Pa(t)=Cae-t/Ta+ Da , Pb(t)=Cbe-t/Tb+ Db and Pc(t)=Cce-t/Tc+ Dc • Number of alternative crossbar components needed to build an NxN switch => Ka = ceil[N/Na]2, Kb = ceil[N/Nb]2 , Kc = ceil[N/Nc]2 • Alternative component costs as a function of time t => Pa(t)=Cae-(t- ta)/Ta+ Ca => Pb(t)=Cbe-(t- tb)/Tb+ Cb => Pc(t)=Cce-(t- tc)/Tc+ Cc • These functions can be used to draw price development curves to make comparisons © P. Raatikainen Switching Technology / 2003 6 - 51 Design optimization example (cont.) Numerical example: • Let N = 64, Na = 16, Nb = 32, Nc = 64, Ta = Tb = Tc = 3 time units (years), Ca = 20,Cb = 50, Cc = 100 and Da = 10, Db = 20, Dc = 40 price units (euros) • Product development period is assumed to be 1 time unit (year) and tb = ta +1.5, tc = ta +3, tm = ta +4 => tpd = ta + 3 • Choosing that tpd = to = 0 => ta = t + 3, tb = t +1.5, tc = t, tm = t -1 (t ≥ tpd = 0 ) • Number of components needed Ka = 16, Kb = 4, Kc = 1 • Switch fabric component cost functions => Pa(t)=16[20e-(t+3)/3 + 10] => Pb(t)=4[50e-(t+1.5)/3 + 20] => Pc(t)=100e-(t)/3 + 40 © P. Raatikainen Switching Technology / 2003 6 - 52 26
- 155. Design optimization example(cont.) Numerical example (cont.) : Component cost 160 300 120 250 Cost 100 Cost Switch fabric cost 350 140 80 60 200 150 100 40 50 20 0 0 0 1 2 3 4 5 6 0 1 2 Pa(t) Pb(t) 3 4 5 6 Time Time Pc(t) Ta(t) Tb(t) Tc(t) • Although the price of component c is manifold compared to the price of component a or b, c turn out to be the cheapest alternative • Another reason to choose c is that it probably stays longest in the market giving more time for the switch product © P. Raatikainen Switching Technology / 2003 6 - 53 27
- 156. Switch Fabrics Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2003 7-1 Switch fabrics • • • • • Multipoint switching Self-routing networks Sorting networks Fabric implementation technologies Fault tolerance and reliability © P. Raatikainen Switching Technology / 2003 7-2 1
- 157. Fabric implementation technologies •Time division fabrics • Shared media • Shared memory • Space division fabrics • Crossbar • Multi-stage constructions • Buffering techniques © P. Raatikainen Switching Technology / 2003 7-3 Buffering alternatives • • • • Input buffering Output buffering Central buffering Combinations – input-output buffering – central-output buffering © P. Raatikainen Switching Technology / 2003 7-4 2
- 158. Input buffering Buffer memoriesat the input interfaces INPUT BUFFERING © P. Raatikainen SWITCH FABRIC Switching Technology / 2003 7-5 Input buffering (cont.) • Pros • required memory access speed - in FIFO and dual-port RAM solutions equal to incoming line rate - in one-port RAM solutions twice the incoming line rate • Speed of switch fabric - multi-stages and crossbars operate at input wire speed - shared media fabrics operate at the aggregate speed of inputs • low cost solution (due to low memory speed) • Cons • FIFO type of buffering => HOL problem • buffer size may be large (due to HOL) • HOL avoided by having a buffer for each output at each input © P. Raatikainen Switching Technology / 2003 7-6 3
- 159. Output buffering Buffer memoriesat the output interfaces SWITCH FABRIC © P. Raatikainen OUTPUT BUFFERING Switching Technology / 2003 7-7 Output buffering (cont.) • Pros • better throughput/delay performance than in input buffered systems • no HOL problem • Cons • access speed of buffer memory - in FIFO and dual-port RAM solutions N times the incoming line rate - in one-port RAM solutions N+1 times the incoming line rate • high cost due to high memory speed requirement • switch fabric operates at the aggregate speed of inputs (N x wire speed) © P. Raatikainen Switching Technology / 2003 7-8 4
- 160. Central buffering Buffer memorylocated between two switch fabrics - shared by all inputs/outputs - virtual buffer for each input or output SWITCH FABRIC 1 © P. Raatikainen CENTRAL BUFFERING SWITCH FABRIC 2 Switching Technology / 2003 7-9 Central buffering (cont.) • Pros • smaller buffer size requirement and lower average delay than in input or output buffering • HOL problem can be avoided • Cons • speed of buffer memory - in dual-port RAM solutions larger than N times the incoming line rate - in one-port RAM solutions larger than 2xN times the incoming line rate • speed of switch fabric N x wire speed • complicated buffer control • high cost due to high memory speed requirement and control complexity © P. Raatikainen Switching Technology / 2003 7 - 10 5
- 161. Input-output buffering Input-output bufferingcommon in QoS aware switches/routers - inputs implement output specific buffers to avoid HOL - outputs implement dedicated buffers for different traffic classes - combined buffering distributes buffering complexity between inputs and outputs INPUT BUFFERING © P. Raatikainen OUTPUT BUFFERING SWITCH FABRIC Switching Technology / 2003 7 - 11 Input-central buffering Input-central buffering used in QoS aware switches/routers - inputs implement output specific buffers to avoid HOL - central buffer implements dedicated buffers for different traffic classes for each output INPUT BUFFERING © P. Raatikainen SWITCH FABRIC 1 CENTRAL BUFFERING Switching Technology / 2003 SWITCH FABRIC 2 7 - 12 6
- 162. Summary of bufferingtechniques Buffering principle Memory space Input buffering high Output buffering medium Central buffering low © P. Raatikainen Memory speed Memory control slow simple fast fast (due to HOL) longest extra logic needed simple medium supported complicated shortest supported but complex (~input rate) (~N x input rate) (~N x input rate) Queueing Multi-casting delay capabilities Switching Technology / 2003 7 - 13 Priorities and buffering • Separate buffer for each traffic class • A scheduler needed to control transmission data • highest priority served first • longest queue served first • minimization of lost packets/cells • Priority given to high quality traffic • low delay and delay variation traffic • low loss rate traffic • best customer traffic • Scheduling principles • • • • • round robin weighted round robin fair queuing weighted fair queuing etc. © P. Raatikainen Switching Technology / 2003 OUTPUT/CENTRAL BUFFERING CLASS 1 CLASS 2 CLASS 3 CLASS 4 7 - 14 7
- 163. Basic memory typesfor buffering • FIFO (First-In-First-Out) • RAM (Random Access Memory) • Dual-port RAM © P. Raatikainen Switching Technology / 2003 7 - 15 Basic memory types for buffering (cont.) FIFO RAM Read/Write DUAL-PORT RAM Write © P. Raatikainen Read Switching Technology / 2003 7 - 16 8
- 164. Switch fabrics • • • • • Multipoint switching Self-routingnetworks Sorting networks Fabric implementation technologies Fault tolerance and reliability © P. Raatikainen Switching Technology / 2003 7 - 17 Fault tolerance and reliability • Definitions • Fault tolerance of switching systems • Modeling of tolerance and reliability © P. Raatikainen Switching Technology / 2003 7 - 18 9
- 165. Definitions • • • Failure, malfunction -is deviation from the intended/specified performance of a system Fault - is such a state of a device or a program which can lead to a failure Error - is an incorrect response of a program or module. An error is a indication that the module in question may be faulty, the module has received wrong input or it has been misused. An error can lead to a failure if the system is not tolerant to this sort of an error. A fault can exist without any error taking place. © P. Raatikainen Switching Technology / 2003 7 - 19 Fault tolerance • • • Fault tolerance is the ability of a system to continue its intended performance in spite of a fault or faults A switching system is an example of a fault tolerant system Fault tolerance always requires redundancy of some sort © P. Raatikainen Switching Technology / 2003 7 - 20 10
- 166. Categorization of faults •Duration based • permanent or stuck-at (stuck at zero or stuck at one) • intermittent - fault requires repair actions, but its impact is not always observable • transient - fault can be observed for a short period of time and disappears without repair • Observable or latent (hidden) • Based on the scope of the impact (serious - less serious) © P. Raatikainen Switching Technology / 2003 7 - 21 Graceful degradation • Capability of a system to continue its functions under one or more faults, but on a reduced level of performance • For example • in some RAID (Redundant Array Inexpensive Disks) configurations, write speed drops in case of a disk fault, but continues on a lower level of performance even while the fault has not been repaired © P. Raatikainen Switching Technology / 2003 7 - 22 11
- 167. Reliability and availability •Reliability R(t) - probability that a system does not fail within time t under the condition that it was functioning correctly at t = 0 • for all known man-made systems R(t) → 0 when t → ∞ • Availability A(t) - probability that a system will function correctly at time t • for a system that can be repaired A(t) approaches some value asymptotically during the useful lifetime of the system © P. Raatikainen Switching Technology / 2003 7 - 23 Repairable system • Maintainability M(t) - probability that a system is returned to its correct functioning state during time t under the condition that it was faulty at time t = 0 © P. Raatikainen Switching Technology / 2003 7 - 24 12
- 168. MTTF, MTTR andMTBF • MTTF (Mean-Time-To-Failure) - expected value of the time duration from the present to the next failure • MTTR (Mean-Time-To-Repair) - expected value of the time duration from a fault until the system has been restored into a correct functioning state • MTBF (Mean-Time-Between-Failures) - expected value of the time duration from occurrence of a fault until the next occurrence of a fault • MTBF = MTTR + MTTR © P. Raatikainen Switching Technology / 2003 7 - 25 High availability of a switching system • High availability of a switching system is obtained by maintenance software Supervision Alarm system Recovery Diagnostics Detection of errors and faults Fault analysis and pinpointing Recovery - elimination of faults Fault location • In a unit under normal working load • HW implementation => fast • SW implementation => detection delay • Often a rule based system Maintenance software is one of the most important software sub-systems in a switching system in parallel with call/connection control and charging © P. Raatikainen Utilizes • In a unit temporarily • redundancy without normal • switch-overs load - active <=> standby • restarts - a single program - a preprocessor - a single main processor - whole system - fall back to previous SW package Switching Technology / 2003 7 - 26 13
- 169. Main types ofredundancy • Hardware redundancy • duplication (1+1) - need for “self-checking”-recovery blocks that detect their own faults • n+r -principle (n active units and r standby units) • Software redundancy • required always in telecom systems • Information redundancy • parity bits, block codes, etc. • Time redundancy • delayed re-execution of transactions © P. Raatikainen Switching Technology / 2003 7 - 27 Modeling of reliability • Combinatorial models • Markov analysis • Other modeling techniques (not covered here) - Fault tree analysis - Reliability block diagrams - Monte Carlo simulation © P. Raatikainen Switching Technology / 2003 7 - 28 14
- 170. Combinatorial reliability • Aserial system S functions if and only if all its parts Si (1≤i≤n) function S n => Rs = Π Ri and Fs = (1- Rs) S1 i=1 S2 Sn • Failures in sub-systems are supposed to be independent S1 • A parallel (replicated) system fails if all its subsystems fail n => Fs = Π (1-Ri) i=1 S2 n and Rs = 1- Fs = 1- Π (1-Ri) i=1 Sn • Reliability of a duplicated system (Ri = R) is Rs = 1- (1-R)2 © P. Raatikainen S Switching Technology / 2003 7 - 29 Combinatorial reliability example 1 • Calculate reliability Rs and failure probability Fs of system S given that failures in sub-systems Si are independent and for some time interval it holds that R1 = 0.90, R2 = 0.95 and R3 = R4 = 0.80 => Rs = Π Ri = R1 x R2 x R3-4 => R3-4 = 1- Π (1-Ri) = 1- (1- R3)(1- R4) => Rs = R1 x R2 x [1- (1- R3)(1- R4)] S S1 S3-4 S3 S2 S4 => Fs = 1- Rs = 1 - R1 x R2 x [1- (1- R3)(1- R4)] => Rs = 0.82 and Fs = 0.18 © P. Raatikainen Switching Technology / 2003 7 - 30 15
- 171. Combinatorial reliability (cont.) •A load sharing system functions if m of the total of n sub-systems function • If failures in sub-systems Si are independent then probability that the system fails is P(fails) = P(k<m) < S S1 and probability that it functions is P(functioning) = P(k≥m) = 1- P(k<m) ≥ < S2 m/n where k is the number of functioning sub-systems n m-1 i=m Sn i=0 P(k≥m) = Σ P(k=i) and P(k<m) = Σ P(k=i) ≥ = < = © P. Raatikainen Switching Technology / 2003 7 - 31 Combinatorial reliability example 2 • As an example, suppose we have a system having m=2 and n=4 and each of the four sub-systems have a different R, i.e. R1, R2, R3 and R4, and failures in sub-systems Si are independent • Probability that the system fails is 1 P(fails) = P(k<2) = Σ P(k=i) = P(k=0) + P(k=1) i=0 • P(k=0) and P(k=1) can be derived to be P(k=0) = (1- R1)(1- R2)(1- R3)(1- R4) P(k=1) = R1(1- R2)(1- R3)(1- R4) + (1- R1)R2(1- R3)(1- R4) + (1- R1)(1- R2) R3(1- R4) + (1- R1) (1- R2)(1- R3) R4 S1 S2 S 2/4 S3 S4 • If R1=0.9 ,R2,=0.95 ,R3 =0.85 and R4 =0.8 then Rs = 0.994 and Fs = 0.0058 © P. Raatikainen Switching Technology / 2003 7 - 32 16
- 172. Combinatorial reliability (cont.) •If failures in sub-systems Si of an m/n system are independent and Ri = R for all i∈[1,n] then the system is a Bernoulli system and binomial distribution applies n => Rs = Σ ( k )Rk(1-R)n-k k=m n • For a system of m/n = 2/3 3 3! −−−− => R2/3 = Σ k!(3-k)! Rk(1-R)3-k = 3R2 - 2R3 k=2 If for example R S1 S2 S m/n Sn = 0.9 => R2/3 = 0.972 © P. Raatikainen Switching Technology / 2003 7 - 33 Computing MTTF • MTTF = ∞ ∫ R(t)dt - valid for any reliability distribution 0 • Single component with a constant failure rate (CFR) λ - R(t) = e-λt - MTTF = 1/λ λ • Serial systems with n CFR components - Rs(t) = R1(t) x R2(t) x ... x Rn(t) = e- (λ1 + λ2 + ... + λn)t = e- λst - λs= λ1 + λ2 + ... + λn • MTTFs = 1/ λs • 1/MTTFs = 1/MTTF1 + 1/MTTF2 + ... + 1/MTTFn © P. Raatikainen Switching Technology / 2003 7 - 34 17
- 173. Telecom exchange reliabilityfrom subscriber’s point of view n-1/n Line-card Subscriber module control Subscriber call control Centralized functions Exchange terminal CCS7 signaling processors • (n-1)/n operational processors for call setup • chosen processor functions during a call Premature release requirement P ≤ 2x10-5 applied © P. Raatikainen Switching Technology / 2003 7 - 35 Failure intensity • Unit of failure intensity λ is defined to be λ [λ] = fit = number of faults /109 h • Failure intensities for replaceable plug-in-units varies in the range 0.1 - 10 kfit • Example: • if failure intensity of a line-card in an exchange is 2 kfit, what is its MTTF ? 109 h 1 000 000 h MTTF = 1/λ = = = 58 years λ 2000 2x24x360 © P. Raatikainen Switching Technology / 2003 7 - 36 18
- 174. Reliability modeling usingMarkov chains Markov chains • A system is modeled as a set of states of transitions • Each state corresponds to fulfillment of a set of conditions and each transition corresponds to an event in a system that changes from one state to another State 1 State 2 • By using this method it is possible to find reliability behavior of a complex system having a number of states and non-independent failure modes © P. Raatikainen Switching Technology / 2003 7 - 37 Markov chain modeling • A set of states of transitions leads to a group of linear differential equations • For a given modeling goal it is essential to choose a minimal set of states for equations to be easily solved • By setting the derivatives of the probabilities to zero an asymptotic state is obtained if such exists λ P0 P1 µ λ = failure intensity µ = repair intensity (repair time is exponentially distributed) Pi = probability of state i, e.g. P0 = R(t) and P1 = F(t), © P. Raatikainen Switching Technology / 2003 7 - 38 19
- 175. Markov chain modeling(cont.) • Probabilities (πi) of the states and transition rates (λij) between the states are tied together with the following formula πΛ = 0 where π n] ) ¡ ¡ ¢ ¡ ¡ © P. Raatikainen ) λ13 λ23 − (λ31 + λ32 + ¢ λ12 − (λ21 + λ23 + λ32 ¢ ) ¢ ¢ − (λ12 + λ13 + λ21 Λ= λ31 ¢ π = [π 1 π 2 Switching Technology / 2003 7 - 39 Markov chain modeling (cont.) Example λ12 λ13 − (λ12 + λ13 ) Λ= − (λ21 + λ23 ) λ21 λ23 − (λ31 + λ32 ) λ31 λ32 and π = [π 1 π 2 £ πΛ = 0 πn] − (λ12 + λ13 )π 1 + λ12π 2 + λ13π 3 = 0 λ21π 1 − (λ21 + λ23 )π 2 + λ23π 3 = 0 λ π + λ π − (λ + λ )π = 0 32 2 31 32 3 31 1 © P. Raatikainen Switching Technology / 2003 λ12 S1 λ31 S2 λ21 λ13 λ32 λ23 S3 7 - 40 20
- 176. Birth-death process Birth-death processis a special case of continuous-time Markov chain, which models the size of population that increases by 1 (birth) or decreases by one (death). S0 λ1 S1 S2 µ1 Balance equations: λ2 λ3 ... S3 µ2 µ3 - State S0 λ0π 0 = λ1π 1 => - State S1 (λ + µ 1 )π 1 = λ 0 π 0 + λ 2π 2 => λ0 π µ1 0 λλ π2 = 1 0 π0 µ 2 µ1 π1 = => + µ k − 1 )π k − 1 = λ k − 2π k − 2 + λ k π k µ4 (λ - State Sk 1 k −1 πk = λ k −1 λ1 λ 0 π0 µk µ2µ1 λ0 © P. Raatikainen Switching Technology / 2003 7 - 41 Birth-death process (cont.) λ1 λ 0 π 0 = ρ k −1 µ 2 µ1 ¡ λ π k = k−1 µk ρ 1 ρ 1π 0 where ρ k = λ k (k=1, 2, 3, …) µ k +1 ¡ ∞ Substituting these expressions for πk into ∑0 π k = 1 k= yields ∞ λ λ k − 1 λ 1λ 0 λ1 λ0 π 0 = 1 => π 0 1 + ∑ k −1 =1 µ 2 µ1 µ 2 µ1 k =1 µ k k =1 µ k ∞ ¢ π0 + ∑ ¢ ¢ ¢ 1 ∞ λ λk λλ 1 0 k −1 => π = 1 + k∑1 µ µ µ = 0 2 1 k £ £ λ λλ => π k = µk −1 µ 1µ 0 π 0 (k=1, 2, 3, …) k 2 1 Sk Sk+1 µk+1 ¤ ¤ © P. Raatikainen Switching Technology / 2003 7 - 42 21
- 177. Example of birth-deathprocess A switching system has two control computer, one on-line and one standby. The time interval between computer failures is exponentially distributed with mean tf . In case of a failure, the standby computer replaces the failed one. A single repair facility exist and repair times are exponentially distributed with mean tr . What fraction of time the system is out of use, i.e., both computers having failed? The problem can be solved by using a three state birth-death model. λ0 S0 S1 µ1 © P. Raatikainen 1/tr λ1 S2 => S0 S1 1/tf µ2 1/tr S2 1/tf Switching Technology / 2003 7 - 43 Example of birth-death process (cont.) S0 - both computer operable S1 - one computer failed S2 - both computer failed 1 1 1 tr tr = 1+ + 1 1 π0 tf tf 2 => π0 = t r2 t r2 + t r t f + t 2 f (probability that both computers have failed) If tr/tf = 10 , i.e. the average repair time is 10 % of the average time between failures, then π0 =0.009009 and both computer will be out of service 0.9 % of the time. © P. Raatikainen Switching Technology / 2003 7 - 44 22
- 178. Additional reading ofMarkov chain modeling Switching Technology S38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2003 7 - 45 Markov chain modeling A continuous-time Markov Chain is a stochastic process {X(t): t ≥0} • X(t) can have values is S={0,1,2,3,...} • Each time the process enters a state i, the amount of time it spends in that state before making a transition to another state has an λ exponential distribution with mean 1/λi • When leaving state i, the process moves to a state j with probability pij where pii=0 • The next state to be visited after i is independent of the length of time spend in state i λ0 S0 S1 µ1 © P. Raatikainen λ1 λ2 S2 µ2 λ3 ... S3 µ3 Switching Technology / 2003 µ4 7 - 46 23
- 179. Markov chain modeling(cont.) Transition probabilities pij ( t ) = P {X ( t + s ) = j X ( s ) = i} Continuous at t=0, with i= j i≠ j 1 if lim pij ( t ) = t →0 0 if Transition matrix is a function of time ¡ ¡ © P. Raatikainen p12 ( t ) ¢ p11 ( t ) P ( t ) = p21 ( t ) Switching Technology / 2003 7 - 47 Markov chain modeling (cont.) Transition intensity: λ j (t ) = − λij ( t ) = d p jj (0 ) dt (rate at which the process leaves state j when it is in state j) d pij ( 0 ) = λi pij dt (transition rate into state j when the process in is state i) The process, starting in state i, spends an amount of time in that state having exponential distribution with rate λi . It then moves to state j with probability n pij = λij λi n ∀i , j © P. Raatikainen n λij ∑p =∑λ ij j =1 j =1 i ∑λ ij = j =1 λi =1 Switching Technology / 2003 ⇒ n λi = ∑ λij j =1 7 - 48 24
- 180. Markov chain modeling(cont.) Chapman-Kolmogorov equations: ∀i , j ∈ S pij ( t + s ) = ∑ pik ( t ) pkj ( s ) ∀s , t ≥ 0 k∈S Since p(t) is a continuous function d pij ( ∆t ) = pij (0 ) + pij ( 0) ∆t + o( ∆t 2 ) dt d λij ( t ) = pij (0 ) We have defined => dt ≠ For i≠j: pij ( ∆t ) = pij (0 ) + λij ∆t + o( ∆t 2 ) ≈ λij ∆t (for small ∆t) For i=j: pii ( ∆t ) = pii (0 ) + λii ∆t + o( ∆t 2 ) ≈ 1 + λii ∆t (for small ∆t) © P. Raatikainen Switching Technology / 2003 7 - 49 Markov chain modeling (cont.) From Chapman-Kolmogorov equations: pij ( t + ∆t ) = ∑ pik ( t ) pkj ( ∆t ) = pij ( t ) p jj ( ∆t ) + ∑ pik ( t ) pkj ( ∆t ) k≠ j k [ ] [ = pij ( t ) 1 + λ jj ∆t + o( ∆t ) + ∑ pik ( t ) λkj ∆t + o( ∆t 2 ) 2 k≠ j ] pij ( t + ∆t ) = pij ( t ) + ∑ pik ( t )λkj ∆t + ∑ pik ( t ) o( ∆t 2 ) k k pij ( t + ∆t ) − pij ( t ) ∆t o( ∆ t 2 ) = ∑ pik ( t )λkj + ∑ pik ( t ) k k ∆t Taking the limit as ∆t → 0 © P. Raatikainen d pij ( t ) = ∑ pik ( t )λkj dt k Switching Technology / 2003 ∀i , j 7 - 50 25
- 181. Markov chain modeling(cont.) The process is described by the system of differential equations: d pij ( t ) = ∑ pik ( t )λkj dt k ∀i , j which can be given in the form d P ( t ) = P ( t )Λ dt ∑ p (t ) = 1 ∀i , j ij d ∑ pij ( t ) = 0 dt j d d ∑ pij ( t ) = dt (1) = 0 dt j ∑λ ij =0 ∀i , t j The sum of of each row of Λ is zero ! j © P. Raatikainen Switching Technology / 2003 7 - 51 Markov chain modeling (cont.) Example λ12 S1 λ31 S2 λ21 λ13 λ32 λ23 S3 λ12 λ13 − (λ12 + λ13 ) Λ= λ21 − (λ21 + λ23 ) λ23 λ31 λ32 − (λ31 + λ32 ) The sum of of each row of Λ must be zero ! © P. Raatikainen Switching Technology / 2003 7 - 52 26
- 182. Markov chain modeling(cont.) Steady state probabilities lim pij ( t ) = π j t →∞ (Independent of initial state i) n Must be non-negative and must satisfy ∑π i =1 i =1 In case of continuous-time Markov chains balance equation used to determine π. For each state i, the rate at which the system leaves the state must equal to the rate at which the system enters the state => λiπ i = λ jiπ j + λkiπ k + λliπ l j k i l © P. Raatikainen Switching Technology / 2003 7 - 53 Markov chain modeling (cont.) Balance equation ∑ λij π i = ∑ λkiπ k k ≠i j ≠i ∀i Steady state distribution is computed by solving this system of equations ∑ λij π i = ∑ λkiπ k j ≠i k ≠i n ∑π i =1 © P. Raatikainen i ∀i =1 Switching Technology / 2003 7 - 54 27
- 183. Markov chain modeling(cont.) An alternative derivation of the steady-state conditions begins with the differential equation describing the process: d pij ( t ) = ∑ pik ( t )λkj dt k ∀i , j Suppose that we take the limit of each side as t → ∞ d pij (t ) = lim ∑ pik (t )λkj t →∞ dt k => lim => d lim pij (t ) = ∑ lim pik (t )λkj t →∞ dt t →∞ k => ∑π t →∞ k λkj = 0 i.e. πΛ=0 k © P. Raatikainen Switching Technology / 2003 7 - 55 Markov chain modeling (cont.) Example λ12 λ13 − (λ12 + λ13 ) Λ= − (λ21 + λ23 ) λ21 λ23 − (λ31 + λ32 ) λ31 λ32 and π = [π 1 π 2 πΛ = 0 πn] λ12 S1 λ31 S2 λ21 λ13 λ32 λ23 S3 − (λ12 + λ13 )π 1 + λ21π 2 + λ31π 3 = 0 λ12π 1 − (λ21 + λ23 )π 2 + λ32π 3 = 0 λ π + λ π − (λ + λ )π = 0 23 2 31 32 3 13 1 © P. Raatikainen Switching Technology / 2003 7 - 56 28
- 184. PDH Switches Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2003 8-1 PDH switches • General structure of telecom exchange • Timing and synchronization • Dimensioning example © P. Raatikainen Switching Technology / 2003 8-2 1
- 185. PDH exchange • Digitaltelephone exchanges are called SPC (Stored Program Control) exchanges • controlled by software, which is stored in a computer or a group of computers (microprocessors) • programs contain the actual intelligence to perform control functions • software divided into well-defined blocks - modularity makes the system less complicated to maintain and expand • Main building blocks • subscriber interfaces and trunk interfaces • switch fabric • switch/call control © P. Raatikainen Switching Technology / 2003 8-3 … SWITCH FABRIC TRUNK INTERFACE … SUBSCRIBER INTERFACE Basic blocks of a PDH exchange LOCAL LOOP SWITCH CONTROL © P. Raatikainen Switching Technology / 2003 8-4 2
- 186. Switch control • Centralized •all control actions needed to set up/tear down a connection are executed in a central processing unit • processing work normally shared by a number of processors • hierarchical or non-hierarchical processor architecture • Distributed • control functions are shared by a number of processing units that are more or less independent of one another • switching device divided into a number of switching parts and each of them has a control processor © P. Raatikainen Switching Technology / 2003 8-5 Switch control (cont.) Control Control processor processor … … Centralized hierarchical processor system … … Centralized non-hierarchical processor system RP Control units usually doubled or tripled … RP Central processor RP - Regional Processor © P. Raatikainen Switching Technology / 2003 8-6 3
- 187. Switch control (cont.) … Switchingpart with control processor Switching part with control processor … … Switching part with control processor Switching part with control processor … Distributed control with independent switching parts © P. Raatikainen Switching Technology / 2003 8-7 Example construction of a PDH exchange SUBSCRIBER INTERFACES SWITCHING & CALL CONTROL ET … … NT … TRUNK INTERFACES SWITCH FABRIC NT ET AUX CONTROL PROCESSOR ADMINISTRATION COMPUTER AUX - Auxiliary equipment AT - Exchange Terminal NT - Network Terminal © P. Raatikainen Switching Technology / 2003 8-8 4
- 188. Example of callcontrol processing SSU SSU SSU RU RU RU M M M CCSU CM LSU M - LSU LSU LSU CM CM CM Common Channel Signaling Unit Central Memory Line Signaling Unit Marker © P. Raatikainen CCSU CCSU CCSU STU STU STU RU SSU STU - Registering Unit - Subscriber Stage Unit - Statistics Unit DX200 / Nokia Switching Technology / 2003 8-9 Hierarchical control software Software systems in the control part: - signaling and call control - charging and statistics - maintenance software Call control programs Control of connections: - calls should not be directed to faulty destinations - faulty connections should be cleared - detected faulty connections must be reported to far-end if possible © P. Raatikainen Administration programs Switching Technology / 2003 Signaling message processing 8 - 10 5
- 189. Switching part • Maintask of switching part is to connect an incoming time-slot to an outgoing one - unit responsible for this function is called a group switch • Control system assigns incoming and outgoing time-slot, which are reserved by signaling, on associated physical links => need for time and space switching Group switch 2 2 A 1 1 B © P. Raatikainen Switching Technology / 2003 8 - 11 Group switch implementations • Group switch can be based on a space or time switch fabric • Memory based time switch fabrics are the most common ones - flexible constructions - due to advances in IC technology suitable also for large switch fabrics … 3 2 write address (3) Cyclic read 1 Switch memory 1 2 3 Control memory 1 2 3 . . . m … j … 2 1 Cyclic write . . . k . . . Outgoing frame buffer n read address (k) j (k) . . . n read/write address (j) Incoming frame buffer m Time-slot counter & R/W control © P. Raatikainen Switching Technology / 2003 8 - 12 6
- 190. Subscriber connections … … Subscriber mux Local exchange Group switch … Subscriber switch … Remote subscriber switch ©P. Raatikainen Switching Technology / 2003 8 - 13 Subscriber and trunk interface • Subscriber interface • on-hook/off-hook detection, reception of dialed digits • check of subscriber line, power supply for subscriber line • physical signal reception/transmission, A/D-conversion • concentration • Trunk interface • timing and synchronization (bit and octet level) to line/clock signal coming from an exchange of higher level of hierarchy • frame alignment/frame generation • multiplexing/demultiplexing © P. Raatikainen Switching Technology / 2003 8 - 14 7
- 191. Example of telephonenetwork hierarchy International transit level National transit level Regional transit level Tandem level Local exchange © P. Raatikainen Switching Technology / 2003 8 - 15 Network synchronization Need for synchronization • Today’s digital telecom networks are combination of PDH and SDH technologies, i.e. TDM and TDMA utilized • These techniques require that time and timing in the network can be controlled, e.g., when traffic is added or dropped from a bit stream in an optical fiber or to/from a radio-transmitted signal • The purpose of network synchronization is to enable the network nodes to operate with the same frequency stability and/or absolute time • Network synchronism is normally obtained by applying the master-slave timing principle © P. Raatikainen Switching Technology / 2003 8 - 16 8
- 192. Network synchronization Methods fornetwork synchronization • Distribute the clock over special synchronization links - offers best integrity, independent of technological development and architecture of the network • Distribute the clock by utilizing traffic links - most frequently used (master-slave network superimposed on the traffic network) • Use an independent clock in each node - expensive method, but standard solution in international exchanges • Use an international navigation system in each node - GPS (Global Positioning System) deployed increasingly - independent of technological development and architecture of network • Combine some of the above methods © P. Raatikainen Switching Technology / 2003 8 - 17 Master-slave synchronization over transport network ∼ International level ∼ High-stability reference clocks Transit level Local exchange level Remote subscriber switch ITU-T Recommendations G.810, G.811, G.812, G.812, G.823 © P. Raatikainen Switching Technology / 2003 8 - 18 9
- 193. SDH synchronization network referencechain • As the number of clocks in tandem increases, synchronization signal is increasingly degraded • To maintain clock quality it is important to specify limit to the number of cascaded clocks and set limit on degradation of the synchronization signal • Reference chain consists of K SSUs each linked with N SECs • Provisionally K and N have been set to be K=10 and N=20 - total number of SECs has been limited to 60 N x SEC N x SEC N x SEC 1st PRC 2nd SSU PRC SEC SSU © P. Raatikainen N x SEC K-th SSU SSU - Primary Reference Clock (accuracy 10-11) - SDH Equipment Clock (accuracy 10-9) - Synchronization Supply Unit (accuracy 10-6) Switching Technology / 2003 8 - 19 PDH synchronization reference connection • End-to-end timing requirements are set for the reference connection • Link timing errors are additive on the end-to-end connection • By synchronizing the national network at both ends, timing errors can be reduced compared to totally plesiochronous (separate clock in each switch) operation • International connections mostly plesiochronous 27 500 km Nation network International network Local LE PC SC TC X X X X LE - Local Exchange PC - Primary Exchange SC - Secondary Exchange © P. Raatikainen ISC X ... ISC X Nation network Local ISC X TC SC PC LE X X X X TC - Tertiary Exchange ISC - International Switching Center X Digital exchange Switching Technology / 2003 Digital link 8 - 20 10
- 194. Types of timingvariation • Frequency offset - steady-state timing difference - causes buffer overflows • Periodic timing differences - jitter (periodic variation > 10 Hz) - wander (periodic variation < 10 Hz) • Random frequency variation cased by - electronic noise in phase-locked loops of timing devices and recovery systems - transients caused by switching from one clock source to another • Timing variation causes - slips (= loss of a frame or duplication of a frame) in PDH systems - pointer adjustments in SDH systems => payload jitter => data errors © P. Raatikainen Switching Technology / 2003 8 - 21 Jitter amplitude Visualization of jitter and wander t © P. Raatikainen Switching Technology / 2003 8 - 22 11
- 195. Timing variation measures •Time interval error (TIE) - difference between the phase of a timing signal and phase of a reference (master clock) timing signal (given in ns) • Maximum time interval error (MTIE) - maximum value of TIE during a measurement period • Maximum relative time interval error (MRTIE) - underlying frequency offset subtracted from MTIE • Time deviation (TDEV) - average standard deviation calculated from TIE for varying window sizes © P. Raatikainen Switching Technology / 2003 8 - 23 Maximum time interval error timing delay compared to ideal signal • the maximum of peak-to-peak difference in timing signal delay during a measurement period as compared to an ideal timing signal MTIE t Measurement period ( S ) © P. Raatikainen Switching Technology / 2003 8 - 24 12
- 196. MTIE limits forPRC, SSU and SEC Clock source Time-slot interval [ns] Time-slot interval [ns] PRC 25 ns 0.3t ns 300 ns 0.01t ns 0.1 < t < 83 s 83 < t < 1000 s 1000 < t < 30 000 s t > 30 000 s SSU 25 ns 10t ns 2000 ns 433t0.2 + 0.01t ns 0.1 < t < 2.5 s 2.5 < t < 200 s 200 < t < 2 000 s t > 2 000 s SEC 250 ns 100t ns 2000 ns 433t0.2 + 0.01t ns 0.1 < t < 2.5 s 2.5 < t < 20 s 20 < t < 2 000 s t > 2 000 s ETS 300 462-3 © P. Raatikainen Switching Technology / 2003 8 - 25 Occurrence of slips • Slips occur on connections whose timing differs from the timing signal used by the exchange • If both ends of a connection are internally synchronized to a PRC signal, theoretically slips occur no more frequently than once in 72 days • In a reference connection a slip occurs theoretically once in 72/12 = 6 days or if national segments are synchronized once in 720/4 = 18 days • Slip requirement on an end-to-end connection is looser: Average frequency of slips Share of time during one year ≤ 5 slips / 24h 98.90 % 5 slips/ 24 h …. 30 slips/ 1h <1% ≤ 10 slips / 1h < 0.1 % © P. Raatikainen Switching Technology / 2003 8 - 26 13
- 197. Slip calculation example Showthat two networks with single frame buffers and timed from separate PRCs would see a maximum slip rate of one slip every 72 days Solution: • Timing accuracy of a PRC clock is 10-11 • Let the frequencies of the two ends be f1 and f2 • In the worst case, these frequencies deviate from the reference clock fo by 10-11x fo and those deviations are to different directions • Let the frequencies be f1 = (1+ 10-11) fo and f2 = (1- 10-11) fo • Duration of bits in these networks are T1= 1/ f1 and T2= 1/ f2 © P. Raatikainen Switching Technology / 2003 8 - 27 Slip calculation example (cont.) Solution (cont.): • During one bit interval, the timing difference is T1- T2 and after some N bits the difference exceeds a frame length of 125 µs and a slip occurs => NT1- T2 = 125x10-9 -9 /[(1/ f -1/ f ) ] => N = 125x10 1 2 • Inserting f1 = (1+ 10-11) fo and f2 = (1- 10-11) fo into the above equation, we get => N = 125x10-9 fo (1- 10-22)/(2x 10-11) • Multiplying N by the duration (Tb) of one bit , we get the time (Tslip) between slips • In case of E1 links, fo= 2.048x106/s and Tb = 488 ns. Dividing the obtained Tslip by 60 (s), then by 60 (min) and finally by 24 (h) we get the average time interval between successive slips to be 72.3 days © P. Raatikainen Switching Technology / 2003 8 - 28 14
- 198. Synchronization of aswitch Synchronization sub-system in an exchange • Supports both plesiochronous and slave mode • Clock accuracy is chosen based on the location of the exchange in the synchronization hierarchy - accuracy decreases towards the leaves of the synchronization tree • Synchronizes itself automatically to several PCM signals and chooses the most suitable of them (primary, secondary, etc.) • Implements a timing control algorithm to eliminate - instantaneous timing differences caused by the transmission network (e.g. switchovers - automatic replacement of faulty equipment with redundant ones) - jitter • Follows smoothly incoming synchronization signal © P. Raatikainen Switching Technology / 2003 8 - 29 Synchronization of a switch (cont.) Exchange follows the synchronization signal • Relative error used to set requirements - maximum relative time interval error MRTIE≤1000 ns (S≥ 100s) • Requirement implies how well the exchange must follow the synchronization signal when the input is practically error free • When none of the synchronization inputs is good enough, the exchange clock automatically switches over to plesiochronous operation • In plesiochronous mode MRTIE≤ (aS +0.5bS2 + c) ns • Timing system monitors all incoming clock signals and when a quality signal is detected, the system switches over back to slave mode (either manually by an operator command or automatically) © P. Raatikainen Switching Technology / 2003 8 - 30 15
- 199. Stability of anexchange clock • Clock stability is measured by aging (=b) - temperature stabilized aging in the order of n x 10-10/day • MRTIE ≤ (aS +0.5bS2 + c) ns - S = measurement period - a = accuracy of the initial setting of the clock - b = clock stability (measured by aging) - c = constant Transit node clock a b Local node clock 0.5 - corresponds to an initial frequency shift of 5x10-10 1.16x10-5 - corresponds to aging of 10-9/days 10.0 - corresponds to an initial frequency shift of 1x10-8 2.3x10 -4 - corresponds to aging of 2x10-8 1000 1000 c © P. Raatikainen Switching Technology / 2003 8 - 31 MRTIE in an exchange (plesiochronous mode) 1E+10 1E+9 1E+8 MRTIE ns 1E+7 Local exchange 1E+6 1E+5 1E+4 Transit exchange 1E+3 1E+2 1E+1 1E+0 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 Observation time (S) Duration of a time-slot in a PCM-signal is 3.9 µs and duration of a bit is 488 ns © P. Raatikainen Switching Technology / 2003 8 - 32 16
- 200. Example of SRAMbased PDH switch fabric Time-interchange based 64 PCM switch 4xE1 2M 8M © P. Raatikainen 34M … 64 x E1 => E4 mux … E4 => 64 x E1 demux 4xE2 4xE3 140M Switching Technology / 2003 8 - 33 Example of SRAM based PDH switch fabric (cont.) Memory size and speed requirement: • Switch memory (SM) and control memory (CM) both are single chip solutions • Size of both SM and CM ≥ 64x32 octets = 2048 octets • Number of SM write and read cycles during a frame interval (125 µs) is 2x64x32 = 4096 • Access cycle of SM should be ≤ 125 µs/4096 = 30,5 ns • Number of CM write and read cycles during a frame interval (125 µs) is 1x64x32 = 2048 • Access cycle of CM should be ≤ 125 µs/2048 = 61 ns © P. Raatikainen Switching Technology / 2003 8 - 34 17
- 201. PDH bit ratesand related bit/octet times Hierarchy level Time-slot Bit interval interval [ns] [ns] E1/2M 3906 488 E2/8M 947 118 E3/34M 233 29 E4/140M 57.4 7.2 • When time-slots turn into parallel form (8 bits in parallel) memory speed requirement decreased by a factor of 8 • Present day memory technology enables up to 256 PDH E1 signals to be written to and read from a SRAM memory on wire speed © P. Raatikainen Switching Technology / 2003 8 - 35 Properties of full matrix switches Pros • strict-sense non-blocking • no path search - a connection can always be written into the control memory if requested output is idle • multi-cast capability • constant delay • multi-slot connections possible Cons • switch and control memory both increase in square of the number of input/outputs • broadband - required memory speed may not be available © P. Raatikainen Switching Technology / 2003 8 - 36 18
- 202. Make full useof available memory speed • At the time of design, select components that - give adequate performance - will stay on the market long enough - are not too expensive (often price limits the use of the fastest components) • To make full use of available memory speed, buses must be fast enough • When increasing required memory speed, practical bus length decreases (proportional to inverse of speed) Bus Bit-rate $/SRAM Bus bit-rate DRAM: 40 ... 70 ns 5 ns © P. Raatikainen Length of a bus Memory speed 20 ns Switching Technology / 2003 8 - 37 Power consumption - avoid heating problem Bus length © P. Raatikainen Power Power Fan-out • Power consumption of an output gate is a function of - inputs connected to it (increased number of inputs => increased power consumption) - bit rate/clock frequency (higher bit rate => increased power consumption - bus length (long buses inside switch fabric => increased power consumption and decreased fan-out) • Increase in power consumption => heating problem • Power consumption and heating problem can be reduced, e.g. by using lower voltage components (higher resolution receivers) Fan-out Switching Technology / 2003 Receiver’s resolution 8 - 38 19
- 203. Logical structure ofa full matrix switch Feasible SM with available components 1 1 Feasible SM with available components 2 2 3 ... ... ... 3 Feasible SM with available components N Replication of inputs N N = 2n Multiplexed inputs © P. Raatikainen Switching Technology / 2003 8 - 39 Example of a matrix switch (DX200) 0 63 0 63 S/P CM 8 63 0 S/P 63 S/P ... Fan-out=32 ... 7 0 0 S/P Bus buffer Address Wr SM 32x64=2k SM SM 16 SM 63 SM SM SM SM SM SM SM SM SM SM SM SM 0 P/S CM 0 P/S Read 63 0 P/S CM 63 Control & switching memory card © P. Raatikainen Switching Technology / 2003 0 P/S CM 63 8 - 40 20
- 204. Example of amatrix switch (cont.) • S/P (Serial/Parallel conversion) - incoming time-slots are turned into parallel form to reduce the speed on internal buses • P/S (Parallel/Serial conversion) - parallel form output signals converted back to serial form • 64 PCM S/P-P/S pairs implemented on one card, which is practical because PCMs are bi-directional • One switch block can serve max 4 S/P-P/S pairs - which is chosen based on required capacity (64, 128, 192 or 256 E1/PCMs) • One S/P+P/S pair feeds max 8 parallel switch blocks - chosen based on the required capacity in the installation (n * 256 E1/PCM’s) • Max size of the example DX200-system fabric is 2048 E1/PCM’s • Currently, a bigger matrix ( 8K E1/PCM’s) is available, slightly different SRAMs are needed, but principle is similar © P. Raatikainen Switching Technology / 2003 8 - 41 Example of a matrix switch (cont.) • A time-slot is forwarded from an S/P to all parallel switch blocks and in each switch block it is written to all SMs along the vertical bus • A single time-slot replicated into max 4x8=32 locations • Data in CMs used to store a time-slot in correct positions in SMs • CM also includes data to read a correct time-slot to be forwarded to each output time-slot on each output E1 link • CM includes a 16-bit pointer to a time-slot to be read – 2 bits of CM content point to an SM chip and – 5 + 6 = 11 bits point to a memory location on an SM chip – remaining 3 bits point to (source) switch block © P. Raatikainen Switching Technology / 2003 8 - 42 21
- 205. Example of amatrix switch (cont.) • Number of time-slots to be switched during a frame (125 µs): - 8x4x64x32 = 65 536 time-slots (= 64 kbytes) • Each time-slot stored in 4 SMs in each of the 8 switch blocks => max size of switch memory 8x4x65 536 = 2097152 (= 2 Mbytes) • Every 32nd memory location is read from SM in a max size switch => average memory speed requirement < 31 ns (less than the worst case requirement 64x32 write and 64x32 read operations during a 125 µs period) • Control memory is composed of 4x4 control memory banks in each of the 8 switch blocks and each memory bank includes 2.048 kwords (word= 2 bytes) for write and 2.048 kwords for read control, i.e. max CM size is 8x4x4x8kbytes = 1048576 bytes (= 1 Mbytes) © P. Raatikainen Switching Technology / 2003 8 - 43 Growth of matrix 256 PCM 512 PCM © P. Raatikainen Switching Technology / 2003 8 - 44 22
- 206. ATM Switches Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2005 L9 - 1 ATM switches • General of ATM switching • Structure of an ATM switch • Example switch implementations • Knockout switch • Abacus • Dimensioning example © P. Raatikainen Switching Technology / 2005 L9 - 2
- 207. General of ATMswitching • ATM switches correspond to layer 2 in the OSI reference model and this layer can roughly be divided into a higher and lower layer: – higher layer = ATM Adaptation Layer (AAL) – lower layer = ATM layer Layer 2 (H) Layer 2 (L) Layer 1 Error recovery & flow control Error & congestion control Limited error detection Network edge © P. Raatikainen Layer 2 (L) Layer 2 (L) Layer 1 Layer 1 Error & congestion control Limited error detection Switching node Layer 2 (H) Layer 2 (L) Layer 1 Network edge Switching Technology / 2005 L9 - 3 ATM Adaptation Layer AAL maps higher-layer information into ATM cells to be transported over an ATM network. At reception, AAL collects information from ATM cells for delivery to higher layers. • AAL offers different service classes for user data – delay, bit rate and connection type (connectionless or circuit emulation) are the basic attributes of the service classes • SAR (Segmentation and Reassembly) sub-layer for segmentation of variable length user data packets into fixed-size ATM cell payloads and at reception reassembly of ATM cell payload into user packets • CS (Convergence Sub-layer) maps specific user data requirements onto ATM transport network © P. Raatikainen Switching Technology / 2005 L9 - 4
- 208. ATM service classes Serviceclass Attribute Class A Timing relation between source and destination Class B Class C Required Bit rate Not required Constant Connection mode Variable AAL2 E1, nx64 kbit/s emulation © P. Raatikainen AAL3/4 or ALL5 AAL3/4 or ALL5 Packet video, audio AAL1 Examples Connec tionless Connection o riented ALL (s) Class D Frame Relay X.25 IP, SMDS Switching Technology / 2005 L9 - 5 ATM Adaptation layer 1 (AAL1) 1 octet 1 octet 46 octets P format SAR-PDU header Structure pointer User information Non-P format SAR-PDU header CS Sequence count Seq. number field ATM header User information CRC control Parity Seq. number protection ATM cell payload SAR-PDU - Segmentation and Reassembly Packet Data Unit CS - Convergence Sub-layer CRC - Cyclic Redundancy Check © P. Raatikainen Switching Technology / 2005 L9 - 6
- 209. ATM Adaptation layer2 (AAL2) CID 8 bits LI 6 bits RES 5 bits HEC 5 bits LLC packet header CID=1 3 octets ATM header OSF 6 bits LLC packet header CID=2 User information ... User information < 61 octets STF ATM header ATM cell payload SN 1 bit Parity 1 bit © P. Raatikainen CID HEC LI LLC RES STF ATM header ATM cell payload STF OSF - Offset SN - Sequence Number STF - Start Field - Connection Identification - Header Error Check - Length Indicator - Logical Link Control - Reserved Switching Technology / 2005 L9 - 7 ATM Adaptation layer 3/4 (AAL3/4) AAL3/4 CPCS PDU 4 octets CS-PDU header CSPDU type 0-3 octets < 65 535 octets Pad CS-PDU user information Protocol control ETag BASize Btag AAL3/4 SAR PDU 48 octets 2 octets 4 - 44 octets 2 octets SAR-PDU header SAR-PDU payload Pad SAR-PDU trailer SAR SARtype SN MID 2 bits 4 bits 10 bits ATM header © P. Raatikainen SAR-PDU User info. length SAR-PDU CRC 6 bits CS CPCS CRC MID SAR PDU Btag BAsize Etag 4 octets CS-PDU trailer CS User Info. length - Convergence Sub-layer - Common Part CS - Cyclic Redundancy Check - Message Identifier - Segmentation and Reassembly - Packet data Unit - Beginning tag - Buffer Allocation tag - Ending tag 10 bits ATM cell payload Switching Technology / 2005 L9 - 8
- 210. 0 - 47octets ATM header Pad UU CPI LEN CRC ATM cell payload - ATM header ATM cell payload 1 octet 2 octets CS-PDU payload 4 octets Pad < 65 535 octets 1 octet ATM Adaptation layer 5 (AAL5) UU CPI LEN CRC ... Padding octets AAL layer user-to-user indicator Common part indicator Length indicator Cyclic redundancy Check © P. Raatikainen Switching Technology / 2005 L9 - 9 ATM layer ATM layer (common to all services) offers transport of data in fixedsize cells and also defines the use of virtual connections (VPs and VCs) • multiplexing/demultiplexing of cells belonging to different virtual connections • translations of inbound VPIs/VCIs to outbound VPIs/VCIs • cell header generation for data received from AAL and cell header extraction when a cell is delivered to AAL • flow control © P. Raatikainen Switching Technology / 2005 L9 - 10
- 211. General of ATMswitching (cont.) • ATM is a connection-oriented transport concept • an end-to-end connection (virtual channel) established prior to transfer of cells • signaling used for connection set up and release • data transferred in fixed 53 octets long cells (5 octets for header and 48 octets for payload) • Cells routed based on two header fields • virtual path identifier (VPI) - 8 bits for UNI and 12 bits for NNI • virtual channel identifier (VCI) - 16 bits for UNI and NNI • combination of VPI and VCI determines a specific virtual connection between two end-points © P. Raatikainen Switching Technology / 2005 L9 - 11 ATM cell structure 5 octets 48 octets ATM ATM header header Cell payload Cell payload ATM header for UNI GFC GFC VPI VPI VCI VCI VCI VCI HEC HEC VPI VPI VCI VCI PTI PTI CPL CPL ATM header for NNI VPI VPI VCI VCI © P. Raatikainen VPI VPI VCI VCI HEC HEC UNI NNI VPI VCI GFC PTI CPL HEC - User Network Interface - Network-to-Network Interface - Virtual Path Identifier - Virtual Channel Identifier - Generic Flow Control - Payload Type Identifier - Cell Loss Priority - Header Error Control VCI VCI PTI PTI CPL CPL HEC = 8 x (header octets 1 to 4) / (x8 + x2 + x + 1) Switching Technology / 2005 L9 - 12
- 212. General of ATMswitching (cont.) • VPI/VCI is determined on a per-link basis => VPI/VCI on an incoming link is replaced (at the ATM switch) with another VPI/VCI for an outgoing link => number of possible paths in an ATM network increased substantially (compared to having end-to-end VPI/VCIs) • Each ATM switch includes a Routing Information Table (RIT), which is used in mapping incoming VPI/VCIs to outgoing VPI/VCIs • RIT includes: • old VPI/VCI • new VPI/VCI • output port address • priority © P. Raatikainen Switching Technology / 2005 L9 - 13 General of ATM switching (cont.) • When an ATM cell arrives to an ATM switch, VPI/VCI in the 5-octet cell header is used to point to a RIT location, which includes • new VPI/VCI to be added to an outgoing cell • output port address indicating to which port the cell should be routed • priority field allowing the switch to selectively send cells to output ports or discard them (in case of buffer overflow) • Three routing modes: • unicast - log2N bits needed to address a destination output port • multi-cast - N bits needed to address destined output ports • broadcast - N bits needed to address destined output ports • In multi-cast/broadcast case, a cell is replicated into multiple copies and each copy is routed to its intended output port/outbound VC © P. Raatikainen Switching Technology / 2005 L9 - 14
- 213. General of ATMswitching (cont.) • ATM connections are either • pre-established - permanent virtual connections (PVCs) • dynamically set up - switched virtual connections (SVCs) • Signaling (UNI or PNNI) messages carry call set up requests to ATM switches • Each ATM switch includes a call processor, which • processes call requests and decides whether the requested connection can be established • updates RIT based on established and released call connections - ensuring that VPIs/VCIs of cells, which are coming from several inputs and directed to a common output are different • finds an appropriate routing path between source and destination ports © P. Raatikainen Switching Technology / 2005 L9 - 15 VPI/VCI translation along transport path ATM switch ATM switch 15 Y ATM switch 10 Z 8 X W RIT X Y 15 RIT P Y Z 10 RIT P Old VPI/VCI New VPI/VCI Output port Priority field © P. Raatikainen Z W 8 P RIT - Routing Information Table Switching Technology / 2005 L9 - 16
- 214. VPI/VCI translation (cont.) •VPI/VCI replacement usually takes place at the output ports => RIT split into two parts • input RIT - includes old VPI/VCI and N-bit output port address • output RIT - includes log2N-bit input port address, old VPI/VCI and new VPI/VCI • Since cells from different input ports can arrive to the same output port and have the same old VPI/VCI, the input port address is needed to identify uniquely different connections © P. Raatikainen Switching Technology / 2005 L9 - 17 ATM switches • General of ATM switching • Structure of an ATM switch • Example switch implementations • Knockout switch • Abacus • Dimensioning example © P. Raatikainen Switching Technology / 2005 L9 - 18
- 215. Functional blocks ofan ATM switch Main blocks • Line interface cards (LICs), which implement input and output port controllers (IPCs and OPCs) • Switch fabric provides interconnections between input and output ports • Switch controller, which includes - a call processor for RIT manipulations - control processor to perform operations, administration and maintenance (OAM ) functions for switch fabric and LICs © P. Raatikainen Switching Technology / 2005 L9 - 19 Main functional blocks of an ATM switch SWITCHING & CONNECTION CONTROL … IPC LIC OPC SWITCH FABRIC IPC … LIC OPC SWITCH CONTROLLER LIC - Line Interface Card IPC - Input Port Controller OPC - Output Port Controller © P. Raatikainen Switching Technology / 2005 L9 - 20
- 216. Functions of inputport controller • • • • • • • Line termination and reception of incoming line signal Conversion of optical signal to electronic form if needed Decoding/descrambling of line/block coded or scrambled line signal Transport frame, e.g. SDH or PDH frame, processing Extraction of cell header for processing Storing of cell payload (or whole cells) to buffer memory HEC processing => discard corrupted cells => forward headers of uncorrupted cells to routing process • Generation of a new cell header (if RIT only at input) and routing tag to be used inside switch fabric • Cell stream is slotted and a cell is forwarded through switch fabric in a time-slot © P. Raatikainen Switching Technology / 2005 L9 - 21 Functions of output port controller • • • • • • • • • Cells received from switch fabric are stored into output buffer Generation of a new cell header (if RIT also at output) One cell at a time is transferred to the outgoing line interface If no buffering available then contention resolution => one cell transmitted and others discarded If buffering available and priorities supported then higher priority cells forwarded first to transport frame processing Cell encapsulation into transport frames, e.g. SDH or PDH frame Line/block encoding or scrambling of outgoing bit stream Conversion of electronic signal to optical form (if needed) Transmission of outgoing line signal © P. Raatikainen Switching Technology / 2005 L9 - 22
- 217. Input and outputcontroller blocks Input controller blocks: 48 To switch fabric RIT 5 W Z 10 W Z 10 … W ... … STM-1 frame ... Z 10 + SDH … From network O/E Buffer Old VPI/VCI New VPI/VCI Output port Output controller blocks: From switch fabric Z © P. Raatikainen Buffer STM-1 frame Z ... SDH Switching Technology / 2005 Z ... E/O To network L9 - 23 Switch control • Switch controller implements functions of ATM management and control layer • Control plane • responsible for establishment and release of connections, which are either pre-established (PVCs) using management functions or set up dynamically (SVCs) on demand using signaling, such as UNI and PNNI signaling • signaling/management used to update routing tables (RITs) in the switches • implements ILMI (Integrated Local Management Interface), UNI signaling and PNNI routing protocols • processes OAM cells © P. Raatikainen Switching Technology / 2005 L9 - 24
- 218. Switch control (cont.) •ILMI protocol uses SNMP (Simple Network Management Protocol) to provide ATM network devices with status and configuration information related to VPCs, SVCs, registered ATM addresses and capabilities of ATM interfaces • UNI signaling specifies the procedures to dynamically establish, maintain and clear ATM connections at UNI • PNNI protocol provides the functions to establish and clear connections, manage network resources and allow network to be easily configurable • Management plane • provides management functions and capabilities to exchange information between the user plane and control plane © P. Raatikainen Switching Technology / 2005 L9 - 25 ATM protocol reference model Management plane ATM adaptation layer ATM layer Layer management User plane Physical layer Terminal Node © P. Raatikainen Node Terminal Switching Technology / 2005 L9 - 26 Plane management Control plane Higher layer protocols Higher layer protocols
- 219. Switch fabric • Providesinterconnections between input and output interfaces • ATM specific requirements • switching of fixed length cells • no regular switching pattern between an input-output port pair, i.e., time cap between consecutive cells to be switched from an input to a specific output varies with time • Early implementations used time switching principle (mostly based on shared media fabrics) - easy to use, but limited scalability • Increased input rates forced to consider alternative solutions => small crossbar fabrics were developed => multi-stage constructions with self-routing reinvented © P. Raatikainen Switching Technology / 2005 L9 - 27 Cell routing through switch fabric • Cells usually carried through switch fabric in fabric specific frames • Carrier frames include, e.g. header, payload and trailer fields • Header field sub-divided into • source port address • destination port address • flow control sub-field (single/multi-cast cell, copy indication, etc.) • Payload field carries an ATM cell (with or without cell header) • Trailer is usually optional and implements an error indication/ correction sub-field, e.g. parity or CRC General structure of a cell carrier frame Frame header © P. Raatikainen Frame payload Switching Technology / 2005 Frame trailer L9 - 28
- 220. ATM switching andbuffering • Due to asynchronous nature of ATM traffic, buffering is an important part of an ATM switch fabric design • A number of different buffering strategies have been developed • input buffering • output buffering • input-output buffering • internal buffering • shared buffering • cross-point buffering • recirculation buffering • multi-stage shared buffering • virtual output queuing buffering © P. Raatikainen Switching Technology / 2005 L9 - 29 Buffering strategies Switch fabric Switch fabric ... ... Switch fabric ... Input-output buffered ... Output buffered ... ... Input buffered Internally buffered © P. Raatikainen Switch fabric Switching Technology / 2005 Shared memory Switch fabric ... ... Shared buffer L9 - 30
- 221. Buffering strategies (cont.) ... Switch fabric ... Recirculationbuffered ... Cross-point buffered Multi-stage shared buffer ... Switch fabric ... ... ... © P. Raatikainen ... ... ... ... ... ... ... Virtual output queuing Switching Technology / 2005 L9 - 31 ATM switching and buffering (cont.) Input buffered switches • Suffers from HOL blocking => throughput limited to 58.6 % of the maximum capacity of a switch (under uniform load) • Windowing technique can be used to increase throughput, i.e. multiple cells in each input buffer are examined and considered for transmission to output ports (however only one cell transmitted in a time-slot) => window size of two gives throughput of 70 % => windowing increases implementation complexity © P. Raatikainen Switch fabric ... ... Input buffered Switching Technology / 2005 L9 - 32
- 222. ATM switching andbuffering (cont.) Output buffered switches • No HOL blocking problem • Theoretically 100 % throughput possible • High memory speed requirement, which can be alleviated by concentrator => output port count reduced => reduced memory speed requirement => increased cell loss rate (CLR) • Output buffered systems largely used in ATM switching © P. Raatikainen Switch fabric ... ... Output buffered Switching Technology / 2005 L9 - 33 ATM switching and buffering (cont.) Input-output buffered switches • Intended to combine advantages of input and output buffering - in input buffering, memory speed comparable to input line rate - in output buffering, each output accepts up to L cells (1≤L≤N) => if there are more than L cells destined for the same output, excess cells are stored in input buffers • Desired throughput can be obtained by engineering the speed up factor L, based on the input traffic distribution • Output buffer memory needs to operate at L times the line rate => large-scale switches can be realized by applying input-output buffering • Complicated arbitration mechanism required to determine, which L cells among the N possible HOL cells go to output port © P. Raatikainen Switching Technology / 2005 L9 - 34
- 223. ATM switching andbuffering (cont.) Internally buffered switch • Buffer implemented within switch blocks • Example is a buffered banyan switch • Buffers used to store internally blocked cells => reduced cell loss rate • Suffers from low throughput and high transfer delay • Support of QoS requires scheduling and buffer management schemes => increased implementation cost © P. Raatikainen Internally buffered Switching Technology / 2005 L9 - 35 ATM switching and buffering (cont.) © P. Raatikainen Switching Technology / 2005 ... ... Shared-buffer switches • All inputs and outputs have access to a common buffer memory • All inputs store a cell and all outputs retrieve a cell in a time-slot Shared => high memory access speed buffer • Works effectively like an output buffered switch Switch Shared Switch fabric memory fabric => optimal delay and throughput performance • For a given CLR shared-buffer switches need less memory than other buffering schemes => smaller memory size reduces cost when switching speed is high (∼ Gbits/s) • Switch size is limited by the memory access speed (read/write time) • Cells destined for congested outputs can occupy shared memory leaving less room for cells destined for other outputs (solved by assigning minimum and maximum buffer capacity for each output) L9 - 36
- 224. ATM switching andbuffering (cont.) Cross-point buffered Cross-point buffered switches • A crossbar switch with buffers at cross-points • Buffers used to avoid output blocking • Each cross-point implements a buffer and an address filter • Cells addressed to an output are accepted to a corresponding buffer • Cells waiting in buffers on the same column are arbitrated to the output port one per time-slot • No performance limitation as with input buffering • Similar to output queuing, but the queue for each output is distributed over a number (N) of buffers => total memory space for a certain CLR > CLR for an output buffered system • Including cross-point memory in a crossbar chip, limits the number of cross-points © P. Raatikainen Switching Technology / 2005 L9 - 37 ATM switching and buffering (cont.) Recirculation buffered ... ... ... Recirculation buffered switches Switch fabric • Proposed to overcome output port contention problem • Cells that have lost output contention are stored in circulation buffers and they content again in the next time-slot • Out-of-sequence errors avoided by assigning priority value to cells • Priority level increased by one each time a cell loses contention => a cell with the highest priority is discarded if it loses contention • Number of recirculation ports can be engineered to fulfill required cell loss rate (CLR = 10-6 at 80 % load and Poisson arrivals => recirculation port count divided by input port count = 2.5) • Example implementations Starlite switch and Sunshine switch - Sunshine allows several cells to arrive to an output in a time-slot => dramatic reduction of recirculation ports © P. Raatikainen Switching Technology / 2005 L9 - 38
- 225. ATM switching andbuffering (cont.) Multi-stage shared buffer switches • Shared buffer switches largely used in implementing small-scale switches - due to sufficiently high throughput, low delay and high memory utilization • Large-scale switches can be realized by interconnecting multiple shared buffer switch modules => system performance degraded due to internal blocking ... ... ... ... ... ... ... • In multi-stage switches, queue lengths may be different in the 1st Multi-stage shared buffer and 2nd stage buffers and thus maintenance of cell sequence at the output module may be very complex and expensive © P. Raatikainen Switching Technology / 2005 L9 - 39 ATM switching and buffering (cont.) Virtual output queuing switches • A technique to solve HOL blocking problem in input buffered switches • Each input implements a logical buffer for each output (in a common buffer memory) • HOL blocking reduced and throughput increased ... Switch fabric ... ... ... • Fast and intelligent arbitration mechanism required, because all HOL cells need to be arbitrated in each time-slot Virtual output queuing => arbitration may become the system bottleneck © P. Raatikainen Switching Technology / 2005 L9 - 40
- 226. Design criteria forATM switches • Several criteria need to be considered when designing an ATM switch architecture • A switch should provide bounded delay and small cell loss probability while achieving a maximum throughput (close to 100%) • Capacity to support high-speed input lines (which possibly deploy different transport technologies, e.g. PDH or SDH) • Self-routing and distributed control essential to implement largescale switches • Maintenance of correct cell sequence at outputs © P. Raatikainen Switching Technology / 2005 L9 - 41 Performance criteria for ATM switches • Performance defined for different quality of service (QoS) classes • Performance parameters: • cell loss ratio (CLR) • cell transfer delay (CTD) • two-point cell transfer delay variation (CDV) Bellcore recommended performance requirements Performance parameter CLP QoS1 QoS3 QoS4 Cell loss ratio Cell loss ratio Cell transfer delay (99th percentile) Cell delay variation (10-10 quantile) Cell delay variation (10-7 quantile) 0 1 1/0 1/0 1/0 < 10-10 <10-7 N/S N/S 150 µs 150 µs 250 µs N/S N/S 250 µs <10-7 N/S 150 µs N/S 250 µs N/S - not specified © P. Raatikainen Switching Technology / 2005 L9 - 42
- 227. Distribution of celltransfer delay • Figure below shows a typical cell transfer delay distribution through a switch node • Fixed delay is attributed to table lookup delay and other cell header processing (e.g. HEC processing) • For example: - Prob(CTD > 150 µs) < 1 - 0.99 => a = 0.01 and x = 150 µs (QoS1, 3 and 4) - Prob(CTD > 250 µs) < 10-10 => a = 10-10 and x = 250 µs (QoS1) Probability density 1- a fixed density x a Cell transfer delay peak to p CDV - - eak maximum CDV © P. Raatikainen Switching Technology / 2005 L9 - 43 Cell processing times at different transmission speeds 100 ms 10 ms Processing time 221 µs/E1 2.83 µs/STM-1 1 ms 708 ns/STM-4 100 us 177 ns/STM-16 10 us 1 us 100 ns 9.6 64 kbit/s © P. Raatikainen 384 2 10 34 100 155 Mbit/s Switching Technology / 2005 622 Link speed 2.5 Gbit/s L9 - 44
- 228. Delay and jittercomponents User A 1 3 Node 1 6 5 1 2 3 4 Node 2 6 1 5 1 2 3 4 Node n 6 1 5 1 2 3 4 User B 6 1 5 1 Encapsulation/decapsulation delay 5 Admission control (smoothing) 6 Queuing delay 7 Reassembly (playtime) delay 4 7 Propagation delay 3 3 Transmission delay 2 1 Switching delay No contribution to jitter Contribution to jitter © P. Raatikainen Switching Technology / 2005 L9 - 45 ATM switches • General of ATM switching • Structure of an ATM switch • Example switch implementations • Knockout switch • Abacus • Dimensioning example © P. Raatikainen Switching Technology / 2005 L9 - 46
- 229. ATM switching fabricimplementations A lot of different switching network architectures have been experimented in ATM switch fabrics : • Batcher-banyan based switches, e.g. Sunshine • Clos network based switches, e.g. Atlanta • Crossbar/crosspoint switches, e.g. TDXP (Tandem-Crosspoint) • Ring and single/dual bus based switches Most advanced ATM switching concepts are switching network independent, e.g. Knockout and Abacus © P. Raatikainen Switching Technology / 2005 L9 - 47 Knockout switch • Output buffered switches largely used in ATM networks • Capacity of output buffered switches limited by memory speed • Problem solved by limiting the number of cells allowed to an output during each time-slot and excess cells discarded => knockout principle • How many cells to deliver to an output port during each time-slot => this number can be determined for a given cell loss rate (CLR), e.g. 12 time-slots for CLR=10-10, independent of switch size • Memory speed seemed to be no more a bottleneck, however no commercial switch implementations appeared - inputs are supposed to be uncorrelated (not the case in real networks) - idea of discarding cells not an appealing one • Knockout principle has been basis for various switch architectures © P. Raatikainen Switching Technology / 2005 L9 - 48
- 230. Knockout principle • Ninput lines each implement a broadcast input bus, which is connected to every output block • An output block is composed of cell filters that are connected to an N-to-L concentrator, which is further connected to a shared buffer • No congestion between inputs and output blocks • Congestion occurs at the interfaces of outputs (inside concentrator) • k cells passing through cell filters enter the concentrator and - if k≤L then all cells go to shared buffer ≤ - if k>L then L cells go to shared buffer and k-L cells are discarded • Shared buffer includes a barrel shifter and L output (FIFO) buffers - barrel shifter stores cells coming from concentrator to FIFO memories in round robin fashion => complete sharing of output FIFO buffers © P. Raatikainen Switching Technology / 2005 L9 - 49 Broadcast buses 1 2 ... Inputs Knockout switch interconnection architecture N ... 1 © P. Raatikainen 2 Outputs Switching Technology / 2005 Bus interfaces N L9 - 50
- 231. Knockout switch businterface 1 2 3 Inputs 4 N-1 N Cell filters ... Concentrator 1 2 ... L Barrel shifter 1 2 Shared buffer L ... Cell buffers Output © P. Raatikainen Switching Technology / 2005 L9 - 51 Operation of barrel shifter At time T ... ... ... ... ... ... ... ... B C At time T+1 D E F G H I J © P. Raatikainen Buffer Barrel shifter A Barrel shifter A B C Buffer ... ... ... ... ... ... ... ... I A J B C D E F G H Switching Technology / 2005 L9 - 52
- 232. Example construction ofconcentrator Input An 8-to-4 concentrator D D D D D D D D D D D D 1 D 2 Outputs © P. Raatikainen D 3 4 Switching Technology / 2005 L9 - 53 Cell loss probability • In every time-slot there is a probability ρ that a cell arrives at an input • Every cell is equally likely destined for any output • Pk denotes probability of k cells arriving in a time-slot to the same output, which is a binomial distribution k N− k N ρ ρ Pk = 1 − , k = 0,1, …, N N k N • Probability of a cell being dropped in N-to-L concentrator is given by P(cell loss) = k 1 N N ρ ρ ∑ (k - L ) 1 − N ρ k = L +1 k N N-k • Taking the limit as N → ∞ and with some manipulation L ρk e - ρ L ρLe-ρ P(cell loss) = 1 − 1 − ∑ + L! ρ k=0 k! © P. Raatikainen Switching Technology / 2005 L9 - 54
- 233. Cell loss probability(cont.) Cell loss probability for some switch sizes (90% load) Cell loss probability for some load values (N = ∞) 10-2 Cell loss probability 100 10-2 Cell loss probability 100 10-4 10-6 10-8 N = 16 N = 32 N = 64 N=∞ 10-10 10-12 1 2 3 4 5 10-4 10-6 Load = 100 % Load = 90 % Load = 80 % Load = 70 % Load = 60 % 10-8 10-10 6 7 8 9 10 11 10-12 1 © P. Raatikainen 2 3 4 5 6 7 8 9 10 11 Number of concentrator outputs, L Number of concentrator outputs, L Switching Technology / 2005 L9 - 55 Channel grouping Channel grouping principle used in modular two-stage networks • A group of outputs treated identically in the first stage • A cell destined for an output of a group is routed to any output (at the first stage), which is connected to that group at the second stage • First stage switch routes cells to proper output groups and second stage switches route cells to destined output ports 1st stage 2nd stage Cell to 6 0 1 2 3 Cell to 1 Cell to 4 4 5 6 7 Cell to 3 © P. Raatikainen Switching Technology / 2005 L9 - 56
- 234. Channel grouping (cont.) Asymmetricswitch with line extension ratio of KM/N • Output group of M output ports corresponds to a single output address for the 1st stage switch • At any given time-slot, M cells at most can be cleared from a particular output group (one cell on each output port) M 1 2 ... ... NxKM switch M © P. Raatikainen M MxM switch K N M MxM switch 1 Switching Technology / 2005 L9 - 57 Channel grouping (cont.) Maximum throughput per input • increases with K/N for a given M (because load per output group decreases) • increases with M for given K/N (because each output group has more ports for clearing cells) Maximum throughput per input for some values of M and K/N M 1/16 1/8 1/4 1/2 1 2 4 8 16 1 K/N = 0,061 0,117 0,219 0,382 0,586 0,764 0,877 0,938 0,969 2 0,121 0,233 0,426 0,686 0,885 0,966 0,991 0,998 0,999 4 0,241 0,457 0,768 0,959 0,996 1 1 1 1 1 8 0,476 0,831 0,991 16 0,878 0,999 1 © P. Raatikainen Switching Technology / 2005 L9 - 58
- 235. Channel grouping (cont.) •Maximum throughput per input increases with M for given KM/N • Channel grouping has a strong effect on throughput for smaller KM/N than for larger ones Maximum throughput as a function of line expansion ratio KM/N M KM/N = 1 2 4 8 16 32 1 0,586 0,764 0,877 0,938 0,969 0,984 2 0,686 0,885 0,966 0,991 0,998 0,999 4 0,768 0,959 0,966 1 1 1 8 0,831 0,991 1 16 0,878 0,999 32 0,912 1 64 0,937 128 0,955 256 0.968 512 0,978 1024 0,984 © P. Raatikainen Switching Technology / 2005 L9 - 59 Multicast output buffered ATM switch (MOBAS) • Channel grouping extends to the general Knockout principle • MOBAS adopts the general Knockout principle • MOBAS consists of • input port controllers (IPCs) • multi-cast grouping networks (MGN1 and MGN2) • multi-cast translation tables (MTTs) • output port controllers (OPCs) LxM 1 2 NxLN switch N © P. Raatikainen Switching Technology / 2005 1 M ... ... NxN switch with group extension ratio L M LMxM switch 1 LxM K M LMxM switch N-M+1 N L9 - 60
- 236. MOBAS switch performance •IPCs terminate incoming cells, look up necessary information in translation tables and attach information in front of cells so that the cells can properly be routed in MGNs • MGNs replicate multi-cast cells based on their multi-cast patterns and send one copy to each addressed output group • MTTs facilitate the multi-cast cell routing MGN2 • OPCs store temporarily multiple arriving cells (destined for their output ports) in an output buffer, generate multiple copies for multi-cast cells with a cell duplicator (CD), assign a new VCI obtained from a translation table to each copy, convert internal cell format to standard ATM cell format and finally send the cell to the next switching node • CD reduces output buffer size by storing only one copy of a multi-cast cell - each copy is updated with a new VCI upon transmission © P. Raatikainen Switching Technology / 2005 L9 - 61 MOBAS architecture SM M N IPC IPC - Input Port Controller MGN - Multi-cast Grouping Network MTT - Multi-cast Translation Table © P. Raatikainen ... Output buffer CD 1 L2 M SM 1 ... ... MTT MTT Group K SM M OPC - Output Port Controller SM - Switching Module SSM - Small Switch Module Switching Technology / 2005 L2 OPC Output buffer CD Output buffer CD N-M+1 ... MGN2 L1xM SM K CD ... ... ... Group 1 Output buffer ... ... MTT ... SM 1 SM 1 MTT OPC L2 L2 ... IPC ... 1 MGN2 L1xM ... MGN 1 CD N - Cell Duplicator L9 - 62
- 237. Abacus switch • Knockoutswitches suffer from cell loss due to concentration/channel grouping (i.e. lack of routing links inside switch fabric) • In order to reduce CLR, excess cells are stored in input buffers => result is an input-output buffered switch • Abacus switch is an example of such a switch • basic structure similar to MOBAS, but it does not discard cells in switch fabric • switching elements resolve contention for routing links based on priority level of cells • input ports store temporarily cells that have lost contention • extra feedback lines and logic added to input ports • distributed arbitration scheme allows switch to grow to a large size © P. Raatikainen Switching Technology / 2005 L9 - 63 Abacus switch (cont.) MGM LxM RM 1 ... IPC SSM 1 ... ... M IPC - Input Port Controller MGM - Multi-cast Grouping Network MTT - Multi-cast Translation Table N-M+1 ... OPC SSM K MTT IPC © P. Raatikainen ... ... MTT N M OPC LxM RM K 1 OPC MTT ... 2 M MTT ... IPC ... 1 OPC N OPC - Output Port Controller RM - Routing Module SSM - Small Switch Module Switching Technology / 2005 L9 - 64
- 238. ATM switches • Generalof ATM switching • Structure of an ATM switch • Example switch implementations • Knockout switch • Abacus • Dimensioning example © P. Raatikainen Switching Technology / 2005 L9 - 65 Dimensioning example • An ATM-switch is to be designed to support 20 STM-4 interfaces. RIT will be implemented at the input interfaces. How fast should RIT lookup process be ? • Cells are encapsulated into frames for delivery through the switch fabric. A frame includes a 53-octet payload field and 3 octets of overhead for routing and control inside the switch fabric. What is the required throughput of the switch fabric ? Solution • ATM cells are encapsulated into VC-4 containers, which include 9 octets of overhead and 9x260 octets of payload. One VC-4 container is carried in one STM-1 frame and each STM-1 frame contains 9x261 octets of payload and 9x9 octets of overhead. (See figure on the next slide) © P. Raatikainen Switching Technology / 2005 L9 - 66
- 239. ATM cell encapsulation/ SDH 9 octets 3 1 VC-4 frame SOH AU-4 PTR J1 ... B3 SOH ... C2 5 STM-1 frame 261 octets G1 F2 H4 Z4 Z5 ... ... ... Z3 ... VC-4 POH © P. Raatikainen Switching Technology / 2005 ATM cell L9 - 67 Dimensioning example (cont.) Solution (cont.) • STM-4 frame carries 4 STM-1 frames and thus there will be 4x9x260 / 53 = 176.6 cells arriving in one STM-4 frame • One STM-4 frame is transported in 125 µs => 176.6/125 µs = 1412830.2 cells will arrive to an input in 1 sec => one RIT lookup should last no more than 707,8 ns • Total throughput of the switch fabric is 20x1412830.2 cells/s • Since each cell is carried through the switch fabric in a container of 56 octets, the total load introduced by the inputs to the switch fabric is 20x1412830.2x56 octets/s ≈ 1.582 109 octets/s ≈ 12,7 Gbits/s © P. Raatikainen Switching Technology / 2005 L9 - 68
- 240. Routers implementations Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 © P. Raatikainen Switching Technology / 2005 L10 - 1 Router implementations • • • • General of routers Functions of an IP router Router architectures Introduction to routing table lookup © P. Raatikainen Switching Technology / 2005 L10 - 2
- 241. General of routers •Router is a network equipment, which • • • • performs packet switching operations operates at network layer of the OSI protocol reference model switches/routes variable length packets routing decisions based on address information carried in packets • Router is used to connect two or more networks that may or may not be similar • Routers communicate with each other by means of routing messages to • exchange routing information • resolve next hop addresses • maintain network topology to make routing decisions © P. Raatikainen Switching Technology / 2005 L10 - 3 IPv4 packet structure 4 8 Ver. 20 octets 4 Version - IP version number IHL - Internet header length in 32bit words (min. size = 5) TOS - type of service (guidance to end-system IP modules and router along transport path) Length - total length (header + payload) of IP packet in octets Identifier - sequence number, which together with address and protocol fields identify each IP packet uniquely IHL TOS Length Identifier Time to live 16 3 Flag Protocol Fragment offset Header checksum Source address (32 bits) Destination address (32 bits) Options + padding Data field Flag - used in connection with fragmentation: more bit indicates whether this fragment is the last one of a fragmented packet and don’t fragment bit inhibits/prohibits packet fragmentation Fragment offset - indicates where in the original user data message this fragment belongs, measured in 64-bit units (all but last the fragment has a data field that contains a multiple of 64-bit payload) Time-to-live - defines the maximum time in seconds a packet can be in transit across the Internet (decremented by each visited router by a defined amount) Protocol - indicates the type of protocol (TCP, UDP, etc.) carried by the IP packet Header checksum - carries a checksum calculated over the header bits © P. Raatikainen Switching Technology / 2005 L10 - 4
- 242. IPv6 packet structure 4 8 Version Trafficclass Payload length (16) 40 octets Version - version number of IP protocol Traffic class - Class-of-service (CoS) priority of the packet Flow label - identifies all packets belonging to a specific flow (requiring a specific CoS), and routers can identify these packets and handle them in a similar fashion. A flow is uniquely identified by the combination of a source address and a non-zero flow label. 20 Flow label Next header (8) Hop limit (8) Source address (128 bits) Destination address (128 bits) Data field Payload length - indicates the number of octets in the payload field Next header - indicates the type of additional (extension) header following the main header Hop limit - value for the maximum number of hops the packet is allowed to travel in a network © P. Raatikainen Switching Technology / 2005 L10 - 5 Router implementations • • • • General of routing Functions of an IP router Router architectures Introduction to routing table lookup © P. Raatikainen Switching Technology / 2005 L10 - 6
- 243. Major tasks ofa router F ... C ... F In_port S Out_port F C - Classify (classification, filtering and routing) F - Forward (transfer of packets from input interfaces to addressed output interfaces) S - Scheduling (transmission of data packets based, e.g. on priority) © P. Raatikainen Switching Technology / 2005 L10 - 7 Main functional blocks of a router Generic router architecture Input Input Interface Interface Card #1 Input port#1 Card #1 Switch fabric Input Input Interface Interface Card #1 Output port #1 Card #1 Network processor © P. Raatikainen Switching Technology / 2005 L10 - 8
- 244. Input port functionality •Layer 1 termination of incoming physical links (e.g. SDH, Ethernet) • Layer 2 frame decapsulation to inter-operate with data-link protocols of connected networks (e.g. AAL5/ATM/SDH and PPP/SDH) • Forwarding of control packets, e.g. routing information packets (RIP, OSPF, IGMP), to network processor to update routing table and network topology • Some implementations distribute a copy of routing table and table lookup to each input port, while some other implementations forward all incoming packets to a centralized routing processor Input port functionality Layer 1 func. Line termination © P. Raatikainen Layer 2 func. Protocol decapsulation Lookup/ forwarding/ queuing Switching Technology / 2005 L10 - 9 Output port functionality • Buffering of outbound packets • Scheduling of buffered packets to guarantee required QoS • Layer 2 frame generation and encapsulation of packets into frames (e.g. AAL5/ATM/SDH, PPP/SDH and Ethernet) • Layer 1 physical signal generation Output port functionality Buffer management/ queuing © P. Raatikainen Layer 2 func. Protocol encapsulation Switching Technology / 2005 Layer 1 func. Line termination L10 - 10
- 245. Switch fabric functionality •Main function is to route data packets from input ports to addressed output ports • Depending on the switch fabric implementation, packets are transported through the fabric either as uniform variable length packets or they are fragmented to fixed size data units • In either case, extra information is added in front of the packets to direct them through the fabric • switching of whole packets is usually applied in low-speed routers • switching of fragments is normally used in high-speed routers • Majority of switch fabrics are based on three basic architectures: bus based, memory based and interconnection network based © P. Raatikainen Switching Technology / 2005 L10 - 11 Network processor functionality • Maintenance of routing table • Execution of routing protocols • Maintenance of routing topology • Performance of network management • Wire-speed operation obtained by implementing key functions in hardware Network processor functionality Incoming packets Classifier Classifier Order management Embedded processor Embedded processor Embedded processor Lookup Lookup Lookup • Processing of packets - classification - order management - acceleration of lookup - queue management - QoS engine © P. Raatikainen Classifier Queue management QoS QoS QoS Outgoing packets Switching Technology / 2005 L10 - 12
- 246. Router classification • Accessrouters • link homes and small business to ISPs (Internet Service Provider) • need to support a variety of access technologies, e.g. high-speed modems, cable modems and xDSL • Enterprise/metropolitan routers • • • • used as campus and office interconnects QoS guarantees for local traffic support of several network layer protocols (e.g. IP and IPX) support of additional features, such as firewalls, security policies and virtual LANs • Backbone/long haul routers • interconnect enterprise routers • huge number of packets per second => very-high-speed requirement • critical components for interworking => reliability of utmost concern © P. Raatikainen Switching Technology / 2005 L10 - 13 Router implementations • • • • General of routing Functions of an IP router Router architectures Introduction to routing table lookup © P. Raatikainen Switching Technology / 2005 L10 - 14
- 247. Basic types ofrouter architecture Router with forwarding engines Router with added processing power in interfaces Line Int. + Forwarding Forwarding Engine Line Interface Line Int. + Forwarding Line Int. + Forwarding Line Interface Line Int. + Forwarding Line Int. + Forwarding … … Line Int. + Forwarding … Line Interface … Forwarding Engine Forwarding Engine Network processor Network processor © P. Raatikainen Switching Technology / 2005 L10 - 15 First generation router architecture • Network layer protocols were constantly changing => adaptable solution was needed => a single and common purpose processor structure was a reasonable one in which operating system in central role • Low throughput (packets transferred twice through the bus) did not scale well with increasing line speeds Shared bus, a single processor card and line interface cards CPU © P. Raatikainen Interface Interface card #1 Interface card #1 card #1 Switching Technology / 2005 L10 - 16
- 248. Second generation routerarchitecture • Each line card implemented a processor => distributed and parallel routing became available • Main processing unit took care of delivery of routing information to line interface cards • Operating system still in central role • Cache memories were introduced to speed up routing decisions (most recently used routing entries kept in cache) • Increased throughput, but shared bus still a bottleneck • Solution did not scale with increasing line speeds Shared bus and a processor on each line interface card © P. Raatikainen Interface Interface Interface card #1 card #1 card #1 + CPU Main CPU Switching Technology / 2005 L10 - 17 Third generation router architecture • Shared bus replaced with more powerful switch fabrics (e.g. multistage and crossbar) • • • • • Parallel processing units (based on general purpose processors) Cache memories to enhance routing decision making Operating system still played an important role Communication between line interfaces no more a problem QoS increases processing power requirement (IP/TCP/application) • Did not scale well enough with the most advanced line speeds Switch fabric and more processing power © P. Raatikainen CPU CPU #1 Switching Technology / 2005 Interface Interface Interface card #1 #1 card card #1 + CPU + cache L10 - 18
- 249. Support of differentiatedservices Traditional routers are limited in terms of their quality of service and differentiation features. Advances in research and hardware capabilities have provided mechanisms to overcome these limitations. Following operations, possible today to carry out in high speed, allow provisioning of differentiated services: • Packet classification - distinguish packets and group them according to their different requirements • Buffer management - determine how much buffer space should be given to certain kinds of network traffic and which packets should be discarded in case of congestion • Packet scheduling - decide that the packet servicing order meets the bandwidth and delay requirements of different types of traffic © P. Raatikainen Switching Technology / 2005 L10 - 19 DiffServ routing Appl. Appl. TCP/UDP TCP/UDP IP TCP/UDP TCP/UDP IP IP IP Eth. MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC 100 MbE 100 MbE 1 GbE 1 GbE 100 MbE 100 MbE Phys. (twisted pair) Phys. (optical) Phys. (twisted pair) Host 1 Host 2 Router 1 © P. Raatikainen Router 2 Switching Technology / 2005 L10 - 20
- 250. DiffServ routing (cont.) Appl. Appl. Appl. TCP/UDP TCP/UDP IP TCP/UDP Appl. IP IP TCP/UDP IP Eth.MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC 100 MbE 100 MbE 1 GbE 1 GbE 100 MbE 100 MbE Phys. (twisted pair) Phys. (optical) Phys. (twisted pair) Host 1 Host 2 Router 1 © P. Raatikainen Router 2 Switching Technology / 2005 L10 - 21 Sharing of processing resources and pipelining DiffServ-optimized router architecture Interface card #1 Interface card #1 + multiple special Interface card #1 + multiple special purpose CPUs Interface card #1 + multiple special purpose CPUs + multiple special purpose CPUs purpose CPUs Filtering © P. Raatikainen Concentrator Route Lookup Switching Technology / 2005 Scheduler Buffering L10 - 22
- 251. Sharing of processingresources and pipelining (cont.) • Packet processing divided into a number of consecutive processes each process has a dedicated processing unit (buffering, filtering, routing, etc.) • Pipelined processes shared by several interfaces to increase number of line interfaces - concentrator schedules packets for processes • QoS-based scheduler takes care of packet transmission from buffers to outbound interfaces © P. Raatikainen Switching Technology / 2005 L10 - 23 Packet processing capacity • Packet processing capacity of a router is given as the number of forwarded packets/second and/or forwarded bits/second • Tasks affecting forwarding speed - link protocol processing delay (input and output) - address lookup time - switching of packets from input ports to outputs ports - queuing at output ports and possibly at input ports • Other tasks that may have an impact on forwarding speed - routing table management/updates - network and router management • In high capacity routers, routing table lookups are a major problem • Queuing is the main component of routing latency • Routing capacity requirement determined by the shortest packets © P. Raatikainen Switching Technology / 2005 L10 - 24
- 252. Future challenges • Increaseof line speeds - 100 Mbit/s => 1 Gbit/s => 10 Gbit/S => 40/100 Gbit/s • QoS-support => increased processing need - DiffServ, IntServ, MPLS, ... • From “best effort” service to controlled use of network resources => programmable network nodes • Different needs in the core and edge networks - huge routing capacity in the core network ( > 10 million packets/s) - a lot of functionality and intelligence in the edge routers © P. Raatikainen Switching Technology / 2005 L10 - 25 Speedup mechanisms for routing table lookup • Caching – routing table entries of most lately arrived packets or entries most frequently accessed are stored in cache memory • Pipelining – different phases of routing table lookup are executed by different pipelined processing units • Distribution of lookup to interfaces or to several routing engines – network processor takes care of routing table updates and distributes updated tables to separate interface/routing engines • In centralized routing solutions only packet headers are sent to a routing processor • Implementation of lookup functionality in hardware (at the expense of flexibility) © P. Raatikainen Switching Technology / 2005 L10 - 26
- 253. Caching to speeduppacket processing and forwarding © P. Raatikainen Fast path … N Switching Technology / 2005 L10 - 27 High speed router examples • GSR /Cisco - first gigabit router on the market - switching capacity of 27.5 Gbits/s - equipped with POS (Packet Over Sonet) and ATM interfaces • 12000 Terabit System /Cisco - initial switching capacity of 150 Gbits/s, but scalable up to 5 Tbits/s - can be equipped with OC192/STM-64 (10 Gbits/s) interfaces • NX64000 /Lucent (Nexabit) - one of the highest capacity routers (6.4 Tbits/s) - supports interface rates up to OC192/STM-64 - distributed programmable hardware based forwarding engine - 1 million routing entries on each line card - 40 ms delay guarantee for variable size packets © P. Raatikainen Switching Technology / 2005 1 … … … • When a packet with a new destination address arrives to an input port, it passes through the conventional routing process (slow path) and its routing entry is stored in cache memory • Subsequent packets carrying the same destination address are routed using the routing entry in the cache memory (fast path) • A routing entry is removed Slow path from cache when predefined Fast path conditions to keep it in cache 1 expire, e.g. packet arrival rate declines or time since the last packet becomes Slow path too long L10 - 28 N
- 254. High speed routerexamples (cont.) • MGR (Multi-Gigabit Router) /BBN Technologies - forwarding rate up to 21 million packets per second - switching backplane capacity of 50 Gbits/s - multiple line cards and separate forwarding engine cards plugged into a high-speed switch - only packet headers are directed to forwarding engines - payloads queued on line cards • TSR (Terabit Switch-Router) / Avici - designed to be scalable from 600 Mbit/s to several Tbits/s - hardware based routing, forwarding, multi-casting and QoS service - each line card implements a 70 Gbit/s router and 20 such line cards fit into a dual-shelf chassis => total switching capacity is 1.4 Tbits/s © P. Raatikainen Switching Technology / 2005 L10 - 29 Example of routing table lookup speed determination In a distributed routing table lookup solution, each input port implements a routing table. What is the maximum allowed routing decision delay if the input link is a 100 Mbit/s Ethernet link or 1 Gbit/s link and the router should operate at wire-speed ? Solution: • In both example cases, the routing decision delay requirement corresponds to maximum packet arrival rate at these interfaces • The maximum packet arrival rate is encountered when there is a constant stream of minimum size Ethernet frames • The minimum size 100 MbE frame is 64 octets and there are 8 octets of preamble and SFD information in front of each frame and additionally there is always a 0.96 µs time gap between successive frames © P. Raatikainen Switching Technology / 2005 L10 - 30
- 255. Example of routingtable lookup determination (cont.) Solution (cont.): • Time required to transmit 72 octets (64+8) at the speed of 100 Mbit/s is 5.76 µs => minimum time interval between successive frames is 5.76 µs + 0.96 µs = 6,72 µs, which is also the maximum allowed routing decision delay for a 100 MbE input port => forwarding capacity is about 149 000 packets/s • The minimum size 1 GbE frame is 512 octets and there are 8 octets of preamble and SFD information in front of each frame and there is a 96 ns time gap between successive frames • Time required to transmit 520 octets (512+8) at the speed of 1 Gbit/s is 4.16 µs => minimum time interval between successive frames is 4.16 + 0.096 µs = 4.256 µs, which is also the maximum allowed routing decision delay for a 1 GbE input port (frame bursting excluded) => forwarding capacity is about 235 000 packets/s © P. Raatikainen Switching Technology / 2005 L10 - 31 10/100 MbE frame 64 - 1518 octets S Preamble F D 7 1 DA SA 6 6 T/L 2 Payload 46 - 1500 CRC 4 Preamble - AA AA AA AA AA AA AA (Hex) SFD - Start of Frame Delimiter AB (Hex) DA - Destination Address SA - Source Address T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator CRC - Cyclic Redundancy Check Inter-frame gap 12 octets (9,6 µs /10 MbE) © P. Raatikainen Switching Technology / 2005 L10 - 32
- 256. 1GbE frame 512 -1518 octets S Preamble F D 7 DA 6 1 SA 6 L 2 Payload 46 - 1500 CRC Extension 4 Preamble- AA AA AA AA AA AA AA (Hex) SFD- Start of Frame Delimiter AB (Hex) DA- Destination Address SA- Source Address T/L- Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator CRC- Cyclic Redundancy Check Inter frame gap 12 octets (96 ns /1 GbE) Extension- for padding short frames to be 512 octets long © P. Raatikainen Switching Technology / 2005 L10 - 33 Router implementations • • • • General of routing Functions of an IP router Router architectures Introduction to routing table lookup © P. Raatikainen Switching Technology / 2005 L10 - 34
- 257. Classful addressing scheme •In IPv4, addresses are 32 bits long - broken up into 4 groups of 8 bits and represented usually as four decimal numbers separated by dots, e.g., 10000010 01010110 00010000 01000010 = 130.86.16.66 • IP intended for interconnecting networks => routing based on network is a natural choice (rather than based on host) • IP address scheme initially used a simple two level hierarchy networks at the top level and hosts at the bottom level • Network part (i.e. address prefix) corresponds to the fist bits • Prefixes written as bit strings up to 32 bits in IPv4 followed by “*” - e.g. 1000001001010110* represents all the 216 addresses that begin with bit pattern 1000001001010110 - an alternative way is to use dotted-decimal expression, i.e., 130.86/16 (number after the slash indicates length of prefix) © P. Raatikainen Switching Technology / 2005 L10 - 35 Classful addressing scheme • With the two level hierarchy, IP routers forwarded packets based on the network part, until packets reached their destination network • Forwarding table only needed to store a single entry to forward packets to all hosts attached to the same network - technique is called address aggregation and allows prefixes to represent a group of addresses • Three different network sizes were defined: A, B and C (see figure) 7 Class A 24 0 14 Class B 10 Class C 16 110 21 © P. Raatikainen Switching Technology / 2005 8 L10 - 36
- 258. Classful addresses • Classfuladdressing scheme worked well in the early days of the Internet • Two basic problems appeared when the number of hosts and networks grew • address space was not efficiently used (only three possible network sizes available) and was getting exhausted very rapidly • forwarding tables in the backbone routers grew rapidly, because routers maintain an entry in the forwarding table for every allocated network address => larger memory requirement => long lookup times © P. Raatikainen Switching Technology / 2005 L10 - 37 Classless InterDomain Routing (CIDR) • CIDR was introduced to allow more efficient use of IP address space and to slow down growth of backbone routing tables • CIDR allows prefixes to be of arbitrary length, not just 8, 16 or 24 bits as in classful address scheme • A network that has identical routing information for all sub-nets, except for a single one, requires only two entries in the routing table • In CIDR, each IP route is represented by a route_prefix / prefix_length pair – prefix length indicates the number of significant bits in a route prefix – e.g. a routing table may have prefixes 12.0.54.8/32, 12.0.54.0/24 and 12.0.0.0/16. If a packet is destined for address 12.0.54.2, the second prefix matches © P. Raatikainen Switching Technology / 2005 L10 - 38
- 259. Difficulties with longestmatch prefix search • In classful addressing scheme, prefix length is coded in the most significant bits of an IP address => address lookup is a relatively simple operation - prefixes are organized in three separate tables (A, B and C) => an exact prefix match could be found using standard search algorithms based on hashing or binary search • CIDR allows reduced size of forwarding tables, but address lookup problem becomes more complex => prefixes are of arbitrary length and no longer correspond to the network part => search in the forwarding table can no longer be performed by exact matching, because the length of the prefix cannot be derived from the address itself => searching in two dimensions: bit pattern value and length © P. Raatikainen Switching Technology / 2005 L10 - 39 Route lookup • Primary goal in designing a data structure to be used in a forwarding table is to minimize lookup time, i.e. - minimize number of memory accesses required during lookups - minimize size of data structure (to fit partly or entirely into a cache) • A binary tree, spanning the entire IPv4 address space has a height of 32 and number of leaves is 232 Depth 32 • Secondary goals of a data structure - as few instructions during lookup as possible - keep the entities naturally aligned as much as possible to avoid expensive instructions and cumbersome bit-extraction operations 232 leaves (IP addresses) © P. Raatikainen Switching Technology / 2005 L10 - 40
- 260. Route lookup (cont.) •A prefix of a routing table entry defines a path in the tree ending in some point and all IP addresses (leaves) in a sub-tree, rooted at that node, should be routed according to that routing entry, i.e. each routing table entry defines a range of IP addresses with identical routing information • If several routing entries cover an IP address, the longest matching rule is applied, i.e. the longest applicable prefix should be used • In the figure below, e2 represents a longer match than e1 for addresses in range r e1 e2 r © P. Raatikainen Switching Technology / 2005 L10 - 41 Route lookup based on binary trie • A trie is a tree-based structure allowing to organize prefixes on a digital basis by using the bits of prefixes to direct the branching • In a trie, a node on level k represents the set of all addresses that begin with the same k bits that label the path from the root to that node, e.g. node c in the figure on the next slide is at level 3 and represents all addresses beginning with the sequence 011 • Nodes that correspond to prefixes are shown in a darker shade these nodes contain the forwarding information or a pointer to it • Some addresses may match several prefixes, e.g. addresses beginning with 011 will match prefixes c and a => prefix c is preferred because it is more specific (longest match rule) © P. Raatikainen Switching Technology / 2005 L10 - 42
- 261. A binary triefor a set of prefixes Information stored by a node: Prefixes: a - 0* b - 01000* c - 011* d - 1* e - 100* f - 1100* g - 1101* h - 1110* I - 1111* 0 a Left-ptr d 1 0 Next-hop pointer (if prefix) 1 1 0 1 c 0 0 0 e 1 1 i 1 0 g h 0 f 0 Right-ptr b © P. Raatikainen Switching Technology / 2005 L10 - 43 Address space of 5-bit long addresses Prefixes: a - 0* b - 01000* c - 011* d - 1* e - 100* f g h i - 1100* - 1101* - 1110* - 1111* a d c e f a a a a a a © P. Raatikainen a a b a a a c c c c e e e e Switching Technology / 2005 d d d d f g f g h g h i h i L10 - 44 i
- 262. Route lookup basedon binary trie • Tries allow finding the longest prefix that matches a given destination address and the search is guided by the bits of the destination address • While traversing the trie and visiting a node marked as a prefix, this prefix is marked as the longest match found so far • The search ends when no more branches to take exist and the longest match is the prefix of the latest visited prefix node • An example address 10110 – from root move to the right (1st bit value = 1) to node d marked as a prefix, i.e. 1st found prefix is 1* – then move to the left (2nd bit value = 0) to a node not marked as a prefix => prefix d still valid – 3rd address bit = 1, but at this point there is no branch to the right => search stops => d is the last visited prefix node and prefix of d is the longest match © P. Raatikainen Switching Technology / 2005 L10 - 45 Route lookup based on binary trie (cont.) • Going trough a trie is a sequential prefix search by length when trying to find a better match – begin looking in the set of length-1 prefixes, located at level 1 – then proceed in the set of length-2 prefixes at level 2, – then proceed to level 3 and so on • While stepping through a trie, the search space reduces hierarchically – at each step, the set of potential prefixes reduces and the search ends when this set is reduces to one • Update operations are straightforward – inserting a new prefix proceeds as a normal search and when arriving to a node with no branch to take, insert the necessary node – deleting a prefix proceeds also as a search and when finding the required node, unmark it as a prefix node and delete it if necessary © P. Raatikainen Switching Technology / 2005 L10 - 46
- 263. Path-compressed tries • Inbinary tries, long sequences of one-child nodes may exist and these bits need to be inspected even though the actual branching decision has been made => search time can be longer than necessary => one-child nodes consume additional memory • Lookup time of a binary trie is O(W) and memory requirement O(NW) – W is the address length in bits and N the number of entries in a table • Path-compression technique can be used to remove unnecessary one-way branch nodes and reduce search time and memory consumption © P. Raatikainen Switching Technology / 2005 L10 - 47 Path-compressed tries (cont.) • Path-compression was first introduced in a scheme called Patricia, which is an improvement of the binary trie structure • it is based on the observation that an internal node, which does not contain a prefix and has only one child, can be removed • removal of internal nodes requires information of missing nodes to be added in remaining nodes so that search operations can be performed correctly, e.g. a simple mechanism is to store a number, which indicates how many nodes have been skipped (skip value) or the number of the next address bit to be inspected • There are many ways to exploit path-compression technique, an example is shown on the next slide • Lookup time is O(W) and worst case storage requirement O(NW) © P. Raatikainen Switching Technology / 2005 L10 - 48
- 264. A path-compressed trieexample Prefixes: a - 0* b - 01000* c - 011* d - 1* e - 100* f - 1100* g - 1101* h - 1110* I - 1111* Compressed binary trie Uncompressed binary trie 0 a 0 0 1 d 1 0 1 c b 0 0 e 0 f 0 0 6 b 1 1 0 g h i 0 1 1 1 0 c 4 4 e 2 d 4 0 5 f 1 1 3 0 1 1 0 g h i Information stored by a node: Bit string Left-ptr © P. Raatikainen 1 3 a Next-hop ptr (if prefix) Bit position Right-ptr Switching Technology / 2005 L10 - 49 A path-compressed trie example (cont.) • Two nodes preceding b have been removed • Since prefix a was located at one child node, it was moved to the nearest descendant, which is not a one-child node • If several one-child nodes, in a path to be compressed, contain prefixes, a list of prefixes must be maintained in some of the nodes • Due to removal of one-child nodes, search jumps directly to an address bit where a significant decision is to be made => bit position of the next address bit to be inspected must be stored => bit strings of prefixes must be explicitly stored © P. Raatikainen Switching Technology / 2005 L10 - 50 4 1
- 265. Search in apath-compressed trie Search goes as follows: • Start from the root and descent in the trie under the guidance of the address bits, but this time only inspect bit positions indicated by the bit position number in the nodes traversed • When a node marked as a prefix is encountered, comparison with the actual prefix is performed - this is needed, because during the descent in the trie, we may skip some bits • If a match is found, we proceed traversing the trie and keep the prefix as the best match prefix (BMP) so far • Search ends when a leaf is encountered or a mismatch found • BMP is the last matching prefix encountered © P. Raatikainen Switching Technology / 2005 L10 - 51 A path-compressed trie example (cont.) In the previous example case, take an address beginning with 010110 • start from root and since its bit position number is 1, inspect the first bit of the address => 1st bit is 0 => go to the left => since this node is marked as a prefix, compare prefix a (“0”) with the corresponding part of the address => they match => keep a as the BMP so far => bit position number of the new node is 3 so skip the 2nd address bit and inspect the 3rd one, which is 0 => proceed left => next node includes a prefix so compare prefix b with the corresponding part of address => no match => stop search => the last recorded BMP is a © P. Raatikainen Switching Technology / 2005 L10 - 52
- 266. Multibit trie • Drawbackof binary (1-bit) trie is that one bit at a time is inspected and the number of memory accesses (in the worst case) can be 32 for IPv4 • Number of lookups can be substantially decreased by using the multibit trie structure, i.e. several bits are inspected at a time • for example, inspecting four bits at a time would lead to only 8 memory accesses in the worst case for an IPv4 address • Number of bits (K) to be inspected is called a stride and the stride can be constant or variable • In a K-bit trie, each node has 2K pointers (children) • If a route prefix is not a multiple of K, it needs to be expanded to K or its multiples • Lookup time is O(W/K) and storage requirement O(2 (K-1) NW/K) © P. Raatikainen Switching Technology / 2005 L10 - 53 Multibit trie example 1 • Prefixes a and d are expanded to length 2 and prefix c has been expanded to length 4 (rest of the prefixes remain unchanged) • Height of the trie has been decreased and so has the number of memory accesses when doing a search Uncompressed binary trie 0 a 0 1 d 1 0 1 0 0 b © P. Raatikainen Variable stride multibit trie c 00 1 0 0 e 0 f 01 a a 1 1 0 g h 10 d 00 01 10 11 0 c c e i 1 0 1 b Switching Technology / 2005 11 d 1 00 01 10 11 f g h i Information stored by a node: Next-hop pointer (if prefix) Ptr00 Ptr01 Ptr10 Ptr11 L10 - 54
- 267. Multibit trie example2 • An alternative multibit trie of the previous example case - prefixes a and d have been expanded to length 3 - rest of the prefixes remain the same as before expansion • When an expanded prefix collides with an existing one, forwarding information of the existing one must be maintained (to respect the longest match) Fixed stride multibit trie 000 a 001 a 010 a 011 c 100 101 e 00 01 10 11 111 d d d 00 01 10 11 00 01 10 11 b © P. Raatikainen 110 f Switching Technology / 2005 f g g h h i L10 - 55 Search in a multibit trie • Search in a multibit trie is essentially the same as search in a binary (1-bit) trie - successively look for longer prefixes that match and the last one found is the longest match prefix for a given address • Multibit tries do linear search on length as do the binary tries, but the search is faster because the trie is traversed using larger strides • A multibit trie is a fixed stride system, if all nodes at the same level have the same stride size, otherwise it a variable stride system • Fixed strides are simpler to implement than variable strides, but usually consume more memory © P. Raatikainen Switching Technology / 2005 L10 - 56 i
- 268. Choice of stridesize and update of tries • Choice of stride size is a trade-off between search speed and memory consumption • in the extreme case, a trie with a single level could be made (stride size = 32) and search would take only one memory access, but a huge amount of memory would be required (232 entries for IPv4) • a natural way to choose stride size and memory consumption is to let the binary trie structure determine this • Update bounds determined by stride size • a multibit trie with several levels allows, by varying stride K, an interesting trade-off between search time, memory consumption and update time - larger strides make faster search => memory consumption increases and updates will require more entries to be modified (due to expansion) © P. Raatikainen Switching Technology / 2005 L10 - 57 Level compression (LC) trie • Path-compressed trie is an effective way to compress a trie when nodes are sparsely populated • LC-tries were developed to compress densely populated tries • LC-tries combine the path-compression and multibit trie compression to optimize binary trie structures • first, a binary trie is developed to a “compact” path-compressed trie • second, the largest full binary sub-trie with multilevels is transformed into a corresponding one-level multibit sub-trie – this process starts from the root node and repeats recursively on each child node of the obtained multibit sub-trie • all bit strings that are proper prefixes of other ones are removed from the LC-trie meaning that only leaf nodes contain prefixes © P. Raatikainen Switching Technology / 2005 L10 - 58
- 269. LC-trie example Uncompressed binary trie Prefixes: a- 0* b - 01000* c - 011* d - 1* e - 100* f g h I Compressed binary trie 0 3 a 0 1 b c - 1100* 1101* 1110* 1111* 1 d 1 0 1 1 1 e 0 0 0 e c 0 f 0 2 d 1 0 0 1 1 0 g h i 1 b LC-trie 1 3 0 4 0 f © P. Raatikainen 0 a 1 0 g h 1 i 4 1 b c e f g Switching Technology / 2005 h i L10 - 59 Level compression trie (cont.) • To save memory, all nodes in LC-trie are stored in a single node array • first root, then all nodes at the second level, then all nodes at third level, and so on • all the descendants of an internal nodes are stored in consecutive memory locations => an internal node only needs to point to its first descendant • Information stored in each node • branch – number of descendants of a node (always power of 2) • skip number – number of bits to be skipped at this node during search operation • pointer – an internal node points to its first descendant (given as the index value of the first child node) and leaf node points to one entry of another base vector table, where the real prefix and next-hop information are stored © P. Raatikainen Switching Technology / 2005 Index Branch Skip 0 /root 2 0 Pointer 1 1 /b 0 0 b 2 /c 0 0 c 3 /e 0 0 e 4 2 3 5 5 /f 0 0 f 6 /g 0 0 g 7 /h 0 0 h 8 /i 0 0 i L10 - 60
- 270. Level compression trie(cont.) • Each entry of the base vector table includes • complete string of the prefix • next-hop information • special prefix vector, which Index Prefix bit string Next hop Special prefix vector b 01000 ptr_b a=0/ptr_a c 011 ptr_c • contains information of strings that e 100 ptr_e are proper prefixes of other strings f 1100 ptr_f • is needed because internal nodes g 1101 ptr_g of an LC-trie do not contain pointers h 1110 ptr_h to the base vector table i 1111 ptr_i • this information implies whether there exists a longer prefix matching the IP address and gives the next-hop information in case of a match a=0/ptr_a d=1/ptr_d d=1/ptr_d d=1/ptr_d d=1/ptr_d d=1/ptr_d • Lookup time is O(W/K) and memory requirement is O(2 K NW/K) © P. Raatikainen Switching Technology / 2005 L10 - 61 Multibit tries in hardware • In core network routers, lookup times are very short and lookup algorithms are implemented in hardware to obtain required speed • Basic scheme uses two level multibit trie with fixed strides - 24 bits at the first level and 8 at the second level • In backbone routers, most of the entries have a prefix length of 24 bits or less => longest match prefix found in one memory access in the majority of cases • Only a small number of sub-entries at the 2nd level • To save memory, internal nodes not allowed to store prefixes => prefixes corresponding to internal nodes expanded to 2nd level => result is a multibit trie with disjoint expanded prefixes - 1st level has 224 nodes and is implemented as a table with the same number of entries © P. Raatikainen Switching Technology / 2005 L10 - 62
- 271. Multibit tries inhardware (cont.) • An entry at the 1st level contains either the forwarding information or a pointer to the corresponding sub-trie at the 2nd level - two bytes needed to store a pointer/forwarding information => a memory bank of 32 Mbytes is needed to store 224 entries Destination address 0 24 1st memory bank 0 2nd memory bank 1 23 31 © P. Raatikainen Forwarding information 224 entries 8 220 entries Switching Technology / 2005 L10 - 63 Multibit tries in hardware (cont.) • Number of sub-tries at the 2nd level depends on the number of prefixes longer than 24 bits • 2nd level stride is 8 bits => a sub-trie at the 2nd level has 28=256 leaves • Size of 2nd memory bank depends on the expected worst case prefix length distribution, e.g. 220 one byte entries (a memory bank of 1 Mbytes) supports a maximum of 212= 4096 sub-tries at the 2nd level • Lookup requires a maximum of two memory accesses - memory accesses can be pipelined or parallelized to speed up performance • Since the first stride is 24 bits and leaf pushing is used, updates may take a long time in some cases © P. Raatikainen Switching Technology / 2005 L10 - 64
- 272. New directions inIP lookup • More efficient lookup schemes have been developed to improve the average lookup performance and storage complexity • Examples of new methods are • Binary search on trie levels, which decomposes the longest prefix operation into W exact matching operations, each performed on prefixes of equal length • Multiway or K-way range search, which applies a binary search to best matching prefixes by using two routing entries per prefix and with some precomputation • Ternary CAM uses a special CAM (Content Addressable Memory), which performs parallel comparisons internally. TCAM stores each W-bit field as a [val, mask] pair and when a bit string is presented to the input, TCAM outputs the location (or address) where a match is found. © P. Raatikainen Switching Technology / 2005 L10 - 65 New directions in IP lookup (cont.) • Conventional routers offer the best-effort service by processing each incoming packet in the same way. New applications require different QoS levels and to meet these requirements new mechanisms, such as admission control, resource reservation and per-flow queuing, need to be implemented in routers. • Routers are required to distinguish and classify incoming traffic into different flows • Flows are specified by rules and each rule consists of operations for comparing packet fields with certain values • Packet fields to be inspected are collected from different protocols => packet classification © P. Raatikainen Switching Technology / 2005 L10 - 66
- 273. Comparison of somelookup schemes Worst case lookup Memory Update Binary trie O(W) O(NW) O(W) Path compressed trie O(W) O(N) O(W) Scheme K-stride multibit trie O(W/K) O(2 NW/K) O(W/K+2K) LC-trie O(W/K) O(2KNW/K) - Binary search on tries level O(log2W) O(Nlog2W) O(log2W) K-way rang search O(log2W) O(N) O(N) O(1) O(N) - TCAM K W - length of address in bits, N - number of prefixes in a prefix set, K - stride size Source: Proceedings of the IEEE, vol. 90, No. 9, 2002 © P. Raatikainen Switching Technology / 2005 L10 - 67 Lookup scalability and IPv6 • On scalability point of view, important aspects are the number of entries in a lookup table and the prefix length • Multibit tries improve lookup speed with respect to binary tries, but only by a constant factor on the length dimension => multibit tries scale badly to longer addresses (128 bit in IPv6) • Binary search on tries level has logarithmic complexity with respect to prefix length => scalability very good for IPv6 • Range search has logarithmic lookup complexity with respect to the number of entries, but independent of prefix length => if the number of entries does not grow excessively, range search is scalable for IPv6 © P. Raatikainen Switching Technology / 2005 L10 - 68
- 274. Introduction to Multiwavelength OpticalNetworks Switching Technology S38.165 http://www.netlab.hut.fi/opetus/s38165 Source: Stern-Bala (1999), Multiwavelength Optical Networks P. Raatikainen Switching Technology / 2003 11 - 1 Contents • The Big Picture • Network Resources • Network Connections P. Raatikainen Switching Technology / 2003 11 - 2 1
- 275. Optical network • Whyoptical networks? – “The information superhighway is still a dirt road; more accurately, it is a set of isolated multilane highways with cow paths for entrance.” • Definition: An optical network is a telecommunications network – with transmission links that are optical fibers, and – with an architecture designed to exploit the unique features of fibers • Thus, the term optical network (as used here) – does not necessarily imply a purely optical network, – but it does imply something more than a set of fibers terminated by electronic switches • The “glue” that holds the purely optical network together consists of – optical network nodes (ONN) connecting the fibers within the network – network access stations (NAS) interfacing user terminals and other nonoptical end-systems to the network P. Raatikainen Switching Technology / 2003 11 - 3 Network categories Multiwavelength optical network = WDM network = optical network utilizing wavelength division multiplexing (WDM) – Transparent optical network = purely optical network • Static network = broadcast-and-select network • Wavelength Routed Network (WRN) • Linear Lightwave Network (LLN) = waveband routed network – Hybrid optical network = layered optical network • Logically Routed Network (LRN) P. Raatikainen Switching Technology / 2003 11 - 4 2
- 276. Physical picture ofthe network ATM LAN Workstation Supercomputer NAS NAS NAS NAS ATM NAS ONN ATM NAS Multimedia terminal ATM Multimedia terminal P. Raatikainen LAN LAN ONN - Optical Network Node NAS - Network Access Station LAN - Local Area Network Switching Technology / 2003 11 - 5 Wide area optical networks - a wish list – efficient and rapid means of fault identification and recovery – support of a very large number of stations and end systems •Structural features – support of a very large number of – scalability concurrent connections including multiple – modularity connections per station – survivability (fault tolerance) – efficient support of multi-cast connections •Connectivity •Technology/cost issues •Performance – high aggregate network throughput (hundreds of Tbps) – high user bit rates (few Gbps) – small end-to-end delay – low error rate / high SNR – low processing load in nodes and stations – adaptability to changing and unbalanced loads P. Raatikainen – access stations: small number of optical transceivers per station and limited complexity of optical transceivers – network: limited complexity of the optical network nodes, limited number and length of cables and fibers, and efficient use (and reuse) of optical spectrum Switching Technology / 2003 11 - 6 3
- 277. Optics vs. electronics Opticaldomain Electrical domain • photonic technology is well suited to certain simple (linear) signal-routing and switching functions •optical power combining, dividing and filtering •wavelength multiplexing, demultiplexing and routing • channelizing needed to make efficient use of enormous bandwidth of the fiber •by wavelength division multiplexing (WDM) •many signals operating on different wavelengths share each fiber => optics is fast but dumb - connectivity bottleneck • electronics is needed to perform more complex (nonlinear) functions •signal detection, regeneration and buffering •logic functions (e.g. reading and writing packet headers) • however, these complex functions limit the throughput • electronics also gives a possibility to include in-band control information (e.g. in packet headers) •enabling a high degree of virtual connectivity • easier to control => electronics is slow but smart - electronic bottleneck P. Raatikainen Switching Technology / 2003 11 - 7 Optics and electronics Hybrid approach: – a multiwavelength purely optical network as a physical foundation – one or more logical networks (LN) superimposed on the physical layer, each • designed to serve some subset of user requirements and • implemented as an electronic overlay – electronic switching equipment in the logical layer acts as a middleman • taking the high-bandwidth transparent channels provided by the physical layer and organizing them into an acceptable and cost-effective form Why this hybrid approach ? – purely optical wavelength selective switches: • huge aggregate throughput of few connections – electronic packet switches: • large number of relatively low bit rate virtual connections – hybrid approach exploits the unique capabilities of optical and electronic switching while circumventing their limitations P. Raatikainen Switching Technology / 2003 11 - 8 4
- 278. Example LAN interconnection •Consider a future WAN serving as a backbone that interconnects a large number of high-speed LANs (say 10,000), accessing the WAN through LAN gateways (with aggregate traffic of tens of Tbps) • Purely optical approach – each NAS connects its LAN to the other LAN’s through individual optical connections ⇒ 9,999 connections per NAS – this is far too much for current optical technology • Purely electronic approach – electronics easily supports required connectivity via virtual connections – however, the electronic processing bottleneck in the core network does not allow such traffic • Hybrid approach: both objectives achieved, since – LN composed of ATM switches provides the necessary connectivity – optical backbone at the physical layer supports the required throughput P. Raatikainen Switching Technology / 2003 11 - 9 Contents • The Big Picture • Network Resources – – – – – Network Links: Spectrum Partitioning Layers and Sublayers Optical Network Nodes Network Access Stations Electrical domain resources • Network Connections P. Raatikainen Switching Technology / 2003 11 - 10 5
- 279. Network links A largenumber of concurrent connections can be supported on each network link through successive levels of multiplexing – Space division multiplexing in the fiber layer: • a cable consists of several (sometimes more than 100) fibers, which are used as bi-directional pairs – Wavelength division multiplexing (WDM) in the optical layer: • a fiber carries connections on many distinct wavelengths (λ-channels) • assigned wavelengths must be spaced sufficiently apart to keep neighboring signal spectra from overlapping (to avoid interference) – Time division multiplexing (TDM) in the transmission channel sublayer: • a λ-channel is divided (in time) into frames and time-slots • each time-slot in a frame corresponds to a transmission channel, which is capable of carrying a logical connection • location of a time-slot in a frame identifies a transmission channel P. Raatikainen Switching Technology / 2003 11 - 11 Fiber resources Cable Fibers Wavebands { Transmission channel out ... ... λ-channels ... λ-channels out ... in Space P. Raatikainen Wavelength Switching Technology / 2003 { Transmission channel in Time 11 - 12 6
- 280. Optical spectrum • Sincewavelength λ and frequency f are related by f λ = c, where c is the velocity of light in the medium, we have the relation ∆ f ≈ − c ∆λ 2 λ • Thus, 10 GHz ≈ 0.08 nm and 100 GHz ≈ 0.8 nm in the range of 1,550 nm, where most modern lightwave networks operate • The 10-GHz channel spacing is sufficient to accommodate λ-channels carrying aggregate digital bit rates on the order of 1 Gbps - modulation efficiency of 0.1 bps/Hz typical for optical systems • The 10-GHz channel spacing is suitable for optical receivers, but much too dense to permit independent wavelength routing at the network nodes - for this, 100-GHz channel spacing is needed. • In a waveband routing network, several λ-channels (with 10-GHz channel spacing) comprise an independently routed waveband (with 100-GHz spacing between wavebands). P. Raatikainen Switching Technology / 2003 11 - 13 Wavelength partitioning of the optical spectrum Unusable spectrum λ1 λ2 λm ... λ f/λ [GHz/nm] 10 GHz 0.08 nm λ-channel spacing for separability at receivers λ1 λ2 λm ... f/λ λ 100 GHz/0.8 nm λ-channel spacing for separability at network nodes P. Raatikainen Switching Technology / 2003 11 - 14 7
- 281. Wavelength and wavebandpartitioning of the optical spectrum 10 GHz λ1,1 λ2,1 λ10,1 ... 100 GHz/0.8 nm w1 w2 ... wm f/λ λ 100 GHz/ 0.08 nm P. Raatikainen Switching Technology / 2003 11 - 15 Network based on spectrum partitioning λ1, λ2 ,..., λm Single waveband λ1 λ2 w2 Wavelength-routed P. Raatikainen ... wm w1 w2 λ1,10 -λ 10,2 λ ... λm λ1,1 -λ10,1 λ w1 λ1,m -λ 10,m λ wm Waveband-routed Switching Technology / 2003 11 - 16 8
- 282. Contents • The BigPicture • Network Resources – – – – – Network Links: Spectrum Partitioning Layers and Sublayers Optical Network Nodes Network Access Stations Electrical domain resources • Network Connections P. Raatikainen Switching Technology / 2003 11 - 17 Layered view of optical network (1) VIRTUAL CONNECTION Logical layer LOGICAL PATH LOGICAL CONNECTION TRANSMISSION CHANNEL OPTICAL LAYER Physical layer OPTICAL CONNECTION λ-CHANNEL OPTICAL/WAVEBAND PATH FIBER LAYER FIBER LINK FIBER SECTION Sub- layers P. Raatikainen Switching Technology / 2003 11 - 18 9
- 283. Layered view ofoptical network (2) NAS E Access Link Network Link O TP OT RP OR NAS OA OA ONN E ONN O OR RP OT TP Fiber Section Fiber Link Optical/Wavelength Path λ-channel Optical Connection Transmission Channel Logical Connection -E -O - OA - ONN P. Raatikainen Electronic Optical Optical Amplifier Optical Network Node - OR - OT - RP - TR Optical Receiver Optical Transmitter Reception Processor Transmission Processor Switching Technology / 2003 11 - 19 Layers and sublayers • Main consideration in breaking down optical layer into sublayers is to account for – multiplexing – multiple access (at several layers) – switching • Using multiplexing – several logical connections may be combined on a λ-channel originating from a station • Using multiple access – λ-channels originating from several stations may carry multiple logical connections to the same station • Through switching – many distinct optical paths may be created on different fibers in the network, using (and reusing) λ-channels on the same wavelength P. Raatikainen Switching Technology / 2003 11 - 20 10
- 284. Typical connection Virtual Connection ES ES LogicalPath LSN LSN LSN Logical Connection NAS Optical Connection ONN Optical Connection NAS ONN ONN P. Raatikainen Logical Connection OA ONN NAS ONN OA ONN ES LSN NAS ONN OA = End System = Logical Switching Node = Network Access Node = Optical Network Node = Optical Amplifier Switching Technology / 2003 11 - 21 Contents • The Big Picture • Network Resources – – – – – Network Links: Spectrum Partitioning Layers and Sublayers Optical Network Nodes Network Access Stations Electrical domain resources • Network Connections P. Raatikainen Switching Technology / 2003 11 - 22 11
- 285. Optical network nodes(1) • Optical Network Node (ONN) operates in the optical path sublayer connecting N input fibers to N outgoing fibers • ONNs are in the optical domain 1 • Basic building blocks: 2 – wavelength multiplexer (WMUX) – wavelength demultiplexer (WDMUX) N – directional coupler (2x2 switch) • static input fibers • dynamic – wavelength converter (WC) P. Raatikainen 1′ ′ 2′ ′ N′ ′ output fibers Switching Technology / 2003 11 - 23 Optical network nodes (2) • Static nodes – without wavelength selectivity • NxN broadcast star (= star coupler) • Nx1 combiner • 1xN divider – with wavelength selectivity • NxN wavelength router (= Latin router) • Nx1 wavelength multiplexer (WMUX) • 1xN wavelength demultiplexer (WDMUX) P. Raatikainen Switching Technology / 2003 11 - 24 12
- 286. Optical network nodes(3) • Dynamic nodes – without wavelength selectivity (optical crossconnect (OXC)) • NxN permutation switch • RxN generalized switch • RxN linear divider-combiner (LDC) – with wavelength selectivity • NxN wavelength selective crossconnect (WSXC) with M wavelengths • NxN wavelength interchanging crossconnect (WIXC) with M wavelengths • RxN waveband selective LDC with M wavebands P. Raatikainen Switching Technology / 2003 11 - 25 Wavelength multiplexer and demultiplexer λ1 λ1 λ2 λ1,…,λ4 λ3 λ1,…,λ4 λ4 λ3 λ4 WMUX P. Raatikainen λ2 WDMUX Switching Technology / 2003 11 - 26 13
- 287. Directional Coupler (1) •Directional coupler (= 2x2 switch) is an optical four-port – ports 1 and 2 designated as input ports – ports 1’ and 2’ designated as output ports • Optical power – enters a coupler through fibers attached to input ports, – divided and combined linearly – leaves via fibers attached to output ports • Power relations for input signal powers powers P1′ and P2′ are given by P1 and P2 and output P ′ = a11 P + a12 P2 1 1 P2′ = a21 P + a22 P2 1 1 • Denote the power transfer matrix by A P. Raatikainen = [aij] 2 a11 a21 a12 1′ 2′ a22 Switching Technology / 2003 11 - 27 Directional Coupler (2) • Ideally, the power transfer matrix A is of the form 1 − α A= α α , 1−α 0 ≤α ≤1 • If parameter α is fixed, the device is static, e.g. with α = 1/2 and signals present at both inputs, the device acts as a 2x2 star coupler • If α can be varied through some external control, the device is dynamic or controllable, e.g. add-drop switch • If only input port 1 is used (i.e., P2 = 0), 1 the device acts as a 1x2 divider • If only output port 1’ is used (and port 2’ is 2 terminated), the device acts as a 2x1 combiner P. Raatikainen Switching Technology / 2003 1−α α α 1−α 1′ 2′ 11 - 28 14
- 288. Add-drop switch OT OR OT Add-drop state P.Raatikainen OR Bar state Switching Technology / 2003 11 - 29 Broadcast star • Static NxN broadcast star with N wavelengths can carry – N simultaneous multi-cast optical connections (= full multipoint optical connectivity) 1 λ1,… , 4 λ 1/N 1/N 1/N 1/N 2 λ2 3 λ3 λ1,… , 4 λ λ4 λ1,… , 4 λ 4 • Power is divided uniformly • To avoid collisions each input signal 1 must use different wavelength 2 • Directional coupler realization – (N/2) log2N couplers needed λ1 1/2 1/2 3 λ1,… , 4 λ 1/2 1/2 1/2 1/2 4 1′ 2′ 3′ 4′ 1′ 2′ 3′ 4′ broadcast star realized by directional couplers P. Raatikainen Switching Technology / 2003 11 - 30 15
- 289. Wavelength router • StaticNxN wavelength router with N wavelengths can carry – N2 simultaneous unicast optical connections (= full point-to-point optical connectivity) • Requires – N 1xN WDMUX’s – N Nx1 WMUX’s 1 2 3 4 λ1,… , 4 λ λ1,… , 4 λ λ1,… , 4 λ λ1,… , 4 λ λ1,… , 4 λ λ1,… , 4 λ λ1,… , 4 λ λ1,… , 4 λ WDMUX’s P. Raatikainen 1′ 2′ 3′ 4′ WMUX’s Switching Technology / 2003 11 - 31 Crossbar switch • Dynamic RxN crossbar switch consists of – R input lines 1 – N output lines 2 – RN crosspoints • Crosspoints implemented by 3 controllable optical couplers – RN couplers needed 4 • A crossbar can be used as – a NxN permutation switch (then R = N) or – a RXN generalized switch P. Raatikainen Switching Technology / 2003 1′ 2′ 3′ 4′ crossbar used as a permutation switch 11 - 32 16
- 290. Permutation switch P. Raatikainen 1′ 2′ 3′ 4′ outputports 1′ 2′ 3′ 4′ input ports 1 • Dynamic NxN permutation switch (e.g. crossbar switch) 2 – unicast optical connections 3 between input and output ports 4 – N! connection states (if nonblocking) – each connection state can carry N simultaneous unicast optical connections – representation of a connection state by a NxN connection matrix 1 1 2 1 3 1 4 1 Switching Technology / 2003 11 - 33 Generalized switch • Dynamic RxN generalized switch (e.g. crossbar switch) 1/N 1/N 1/N 1/N 1 – any input/output pattern possible 2 – 2NR connection states 3 – each connection state can carry (at most) R simultaneous multicast optical 4 connections – a connection state represented by a RxN connection matrix 1 , aij = NR 0, P. Raatikainen if switch (i,j ) is on otherwise Switching Technology / 2003 2′ 3′ 4′ output ports 1′ 2′ 3′ 4′ input ports • Input/output power relation P’ = AP with NxR power transfer matrix A = [aij], where 1/R1/R 1/R 1/R 1′ 1 1 1 2 1 1 3 1 4 1 1 1 11 - 34 17
- 291. Linear Divider-Combiner (LDC) 1′ 1 δ11 •Linear Divider-Combiner (LDC) is δ δ21 δ41 31 a generalized switch that 2 – controls power-dividing and power-combining ratios 3 σ41 – less inherent loss than in crossbar σ σ42 σ4443 4 • Power-dividing and power-combining ratios – δij = fraction of power from input port j directed to output port i’ – σij = fraction of power from input port j combined onto output port i • In an ideal case of lossless couplers, we have constraints 2′ 3′ 4′ ∑ δ ij = 1 and ∑ σ ij = 1 i j • The resulting power transfer matrix A = [aij] is such that aij = δ ijσ ij P. Raatikainen Switching Technology / 2003 11 - 35 LDC and generalized switch realizations 1 rx1 combiner directional couplers 11 12 1r ... 22 2r ... 21 2 1xn splitter n ... δ - σ linear divider-combiner 1 2 n1 r n2 nr Generalized optical switch P. Raatikainen Switching Technology / 2003 11 - 36 18
- 292. Wavelength selective cross-connect (WSXC) •Dynamic NxN wavelength selective crossconnect (WSXC) with M wavelengths – includes N 1xM WDMUXs, M NxN permutation switches, λ ,… , 4 λ λ1,… , 4 λ 1 1 and N Mx1 WMUXs λ ,… , 4 λ λ1,… , 4 λ – (N!)M connection states 2 1 if the permutation switches λ ,… , 4 λ λ1,… , 4 λ 3 1 are nonblocking λ ,… , 4 λ λ1,… , 4 λ 4 1 – each connection state can carry NM simultaneous unicast optical connections WDMUX’s WMUX’s – representation of a connection state by M NxN connection matrices optical switches P. Raatikainen Switching Technology / 2003 1′ 2′ 3′ 4′ 11 - 37 Wavelength interchanging cross-connect (WIXC) • Dynamic NxN wavelength interchanging crossconnect (WIXC) with M wavelengths – includes N 1xM WDMUXs, 1 NM x NM permutation switch, NM WCs, and N Mx1 WMUXs – (NM)! connection states if λ ,… , 4 λ λ1,… , 4 λ 1 1 the permutation switch is λ ,… , 4 λ λ1,… , 4 λ nonblocking 2 1 λ ,… , 4 λ λ1,… , 4 λ – each connection state can 3 1 carry NM simultaneous λ ,… , 4 λ λ1,… , 4 λ 4 1 unicast connections – representation of a connection WC’s state by a NMxNM WDMUX’s WMUX’s connection matrix 1′ 2′ 3′ 4′ optical switch P. Raatikainen Switching Technology / 2003 11 - 38 19
- 293. Waveband selective LDC •Dynamic RxN waveband selective LDC with M wavebands – includes R 1xM WDMUXs, M RxN LDCs, and N Mx1 WMUXs – 2RNM connection states (if used as a generalized switch) w ,… , 4 w w1,… , 4 w 1 1 – each connection state can w ,… , 4 w w1,… , 4 w carry (at most) RM 2 1 simultaneous multi-cast w ,… , 4 w w1,… , 4 w 3 1 connections w ,… , 4 w w1,… , 4 w 4 1 – representation of a connection state by a M RxN connection matrices WDMUX’s 1′ 2′ 3′ 4′ WMUX’s LDC’s P. Raatikainen Switching Technology / 2003 11 - 39 Contents • The Big Picture • Network Resources – – – – – Network Links: Spectrum Partitioning Layers and Sublayers Optical Network Nodes Network Access Stations Electrical domain resources • Network Connections P. Raatikainen Switching Technology / 2003 11 - 40 20
- 294. Network access stations(1) • Network Access Station (NAS) operates in the logical connection, transmission channel and λ-channel sublayers • NASs are the gateways between the electrical and optical domains e/o • Functions: – interfaces the external LC ports to the optical transceivers – implements the functions necessary to move signals between the electrical and optical domains 1 2 L 1′ ′ ′ 2′ L′ ′ electronic wires P. Raatikainen Switching Technology / 2003 a a’ optical fibers 11 - 41 Network access stations (2) • Transmitting side components: – Transmission Processor (TP) with a number of LC input ports and transmission channel output ports connected to optical transmitters (converts each logical signal to a transmission signal) – Optical Transmitters (OT) with a laser modulated by transmission signals and connected to a WMUX (generates optical signals) – WMUX multiplexes the optical signals to an outbound access fiber • Receiving side components: – WDMUX demultiplexes optical signals from an inbound access fiber and passes them to optical receivers – Optical Receivers (OR) convert optical power to electrical transmission signals, which are corrupted versions of the original transmitted signals – Reception Processor (RP) converts the corrupted transmission signals to logical signals (e.g. regenerating digital signals) P. Raatikainen Switching Technology / 2003 11 - 42 21
- 295. Elementary network accessstation logical connection ports e/o OT WMUX TP OT ONN OR WDMUX RP OR NAS access fiber pair internodal fiber pairs P. Raatikainen Switching Technology / 2003 11 - 43 Nonblocking network access station logical connection ports e/o TP OT WMUX’s OT ONN RP OR OR WDMUX’s NAS access fiber pairs internodal fiber pairs P. Raatikainen Switching Technology / 2003 11 - 44 22
- 296. Wavelength add-drop multiplexer (WADM) WADM WMUX λ2 ... WDMUX λ1 λm λ1 OT λ2 OR OT OR ... λm OT OR NAS TP/RP ... P.Raatikainen Switching Technology / 2003 11 - 45 Contents • The Big Picture • Network Resources – – – – – Network Links: Spectrum Partitioning Layers and Sublayers Optical Network Nodes Network Access Stations Electrical domain resources • Network Connections P. Raatikainen Switching Technology / 2003 11 - 46 23
- 297. End System • Endsystems are in the electrical domain • In transparent optical networks, they are directly connected to NASs – purpose is to create full logical connectivity between end stations • In hybrid networks, they are connected to LSNs – purpose is to create full virtual connectivity between end stations a a’ access wires P. Raatikainen Switching Technology / 2003 11 - 47 Logical Switching Node (LSN) • Logical switching nodes (LSN) are needed in hybrid networks, i.e. logically routed networks (LRN) • LSNs are in the electrical domain • They may be e.g. – SONET digital cross-connect systems 1′ ′ 1 (DCS), or 2′ ′ 2 – ATM switches, or – IP routers N input wires P. Raatikainen Switching Technology / 2003 N′ ′ output wires 11 - 48 24
- 298. Logically routed network Logically switching node LS Logicallayer NAS LSN ONN Physical layer LSN - Logically Switching Node LS - Logical Switch NAS - Network Access Station ONN - Optical Network Node P. Raatikainen Switching Technology / 2003 11 - 49 Contents • The Big Picture • Network Resources • Network Connections – Connectivity – Connections in various layers – Example: realizing full connectivity between five end systems P. Raatikainen Switching Technology / 2003 11 - 50 25
- 299. Connectivity • Transmitting side: –one-to-one • (single) unicast – one-to-many • multiple unicasts • (single) multicast • multiple multicasts • Receiving side: – one-to-one • (single) unicast • (single) multicast – many-to-one • multiple unicasts • multiple multicasts • Network wide: – point-to-point – multipoint P. Raatikainen Switching Technology / 2003 11 - 51 Connection Graph (CG) • Representing point-to-point connectivity between end systems transmitting side receiving side 3 Connection graph P. Raatikainen 2 3 4 2 1 3 4 1 2 1 4 Bipartite representation Switching Technology / 2003 11 - 52 26
- 300. Connection Hypergraph (CH) •Representing multipoint connectivity between end systems transmitting side 1 E1 1 2 1 3 E1 2 3 E2 3 4 Connection hypergraph P. Raatikainen receiving side 2 E2 4 hyperedges 4 Tripartite representation Switching Technology / 2003 11 - 53 Contents • The Big Picture • Network Resources • Network Connections – Connectivity – Connections in various layers – Example: realizing full connectivity between five end systems P. Raatikainen Switching Technology / 2003 11 - 54 27
- 301. Connections in variouslayers • Logical connection sublayer – Logical connection (LC) is a unidirectional connection between external ports on a pair of source and destination network access stations (NAS) • Optical connection sublayer – Optical connection (OC) defines a relation between one transmitter and one or more receivers, all operating in the same wavelength • Optical path sublayer – Optical path (OP) routes the aggregate power on one waveband on a fiber, which could originate from several transmitters within the waveband P. Raatikainen Switching Technology / 2003 11 - 55 Notation for connections in various layers • Logical connection sublayer – [a, b] = point-to-point logical connection from an external port on station a to one on station b – [a, {b, c, …}] = multi-cast logical connection from a to set {b, c, …} • station a sends the same information to all receiving stations • Optical connection sublayer – (a, b) = point-to-point optical connection from station a to station b – (a, b)k = point-to-point optical connection from a to b using wavelength λk – (a,{b,c,…}) = multi-cast optical connection from a to set {b,c,…} • Optical path sublayer – 〈a, b〉 = point-to-point optical path from station a to station b – 〈a, b〉k = point-to-point optical path from a to b using waveband wk – 〈a, {b, c, …}〉 = multi-cast optical path from a to set {b,c,…} P. Raatikainen Switching Technology / 2003 11 - 56 28
- 302. Example of alogical connection between two NASs Logical connection [A,B] NAS NAS TP RP Transmission channel Electrical Optical connection (A,B)λ1 OT Optical λ-channel λ1 ... λm WMUX Electrical OR λm ... λ1 Optical WDMUX Optical path <A,B>w1 w1 ONN w2 P. Raatikainen ONN ONN Switching Technology / 2003 11 - 57 Contents • The Big Picture • Network Resources • Network Connections – Connectivity – Connections in various layers – Example: realizing full connectivity between five end systems P. Raatikainen Switching Technology / 2003 11 - 58 29
- 303. Example: realization offull connectivity between 5 end systems 1 5 2 4 P. Raatikainen 3 Switching Technology / 2003 11 - 59 Solutions • Static network based on star physical topology – full connectivity in the logical layer (20 logical connections) – 4 optical transceivers per NAS, 5 NASs, 1 ONN (broadcast star) – 20 wavelengths for max throughput by WDM/WDMA • Wavelength routed network (WRN) based on bi-directional ring physical topology – full connectivity in the logical layer (20 logical connections) – 4 optical transceivers per NAS, 5 NASs, 5 ONNs (WSXCs) – 4 wavelengths (assuming elementary NASs) • Logically routed network (LRN) based on star physical topology and unidirectional ring logical topology – full connectivity in the virtual layer but only partial connectivity in the logical layer (5 logical connections) – 1 optical transceiver per NAS, 5 NASs, 1 ONN (WSXC), 5 LSNs – 1 wavelength P. Raatikainen Switching Technology / 2003 11 - 60 30
- 304. Static network realization 1 1 1 2 5 2 5 2 3 4 4 3 4 5 3 5x5broadcast star LCG P. Raatikainen Switching Technology / 2003 11 - 61 Wavelength routed network realization 3x3 WSXC 1 1 1 2 2 5 5 2 3 4 4 3 4 3 5 LCG P. Raatikainen Switching Technology / 2003 11 - 62 31
- 305. Logically routed networkrealization 1 LSN 1 1 2 5 5 2 2 3 4 4 3 5x5 WSXC P. Raatikainen 4 3 5 LCG Switching Technology / 2003 11 - 63 32
- 306. Multiwavelength Optical Network Architectures SwitchingTechnology S38.165 http://www.netlab.hut.fi/opetus/s38165 Source: Stern-Bala (1999), Multiwavelength Optical Networks P. Raatikainen Switching Technology / 2003 12 - 1 Router implementations • • • • Static networks Wavelength Routed Networks (WRN) Linear Lightwave Networks (LLN) Logically Routed Networks (LRN) P. Raatikainen Switching Technology / 2003 12 - 2
- 307. Static networks • Staticnetwork, also called broadcast-and-select network, is a purely optical shared medium network • passive splitting and combining nodes are interconnected by fibers to provide static connectivity among some or all OTs and ORs • OTs broadcast and ORs select • Broadcast star network is an example of such a static network • star coupler combines all signals and broadcasts them to all ORs - static optical multi-cast paths from any station to the set of all stations - no wavelength selectivity at the network node • optical connection is created by tuning the source OT and/or destination OR to the same wavelength • two OTs must operate at different wavelengths (to avoid interference) - this is called the distinct channel assignment (DCA) constraint • however, two ORs can be tuned to the same wavelength - by this way, optical multi-cast connections are created P. Raatikainen Switching Technology / 2003 12 - 3 Realization of logical connectivity • Methods to realize full point-to-point logical connectivity in a broadcast star with N nodes: • WDM/WDMA - a whole λ-channel allocated for each LC - N(N-1) wavelengths needed (one for each LC) - N-1 transceivers needed in each NAS • TDM/TDMA - 1/[N(N-1)] of a λ-channel allocated for each LC - 1 wavelength needed - 1 transceiver needed in each NAS • TDM/T-WDMA - 1/(N-1) of a λ-channel allocated for each LC - N wavelengths needed (one for each OT) - 1 transceiver needed in each NAS, e.g. fixed OT and tunable OR (FT-TR), or tunable OT and fixed OR (TT-FR) P. Raatikainen Switching Technology / 2003 12 - 4
- 308. Broadcast star usingWDM/WDMA LCs [1,2] [1,3] [2,1] [2,3] [3,1] [3,2] LCs NAS 1 TP TP TP λ1 OT λ 2 OT λ3 OT λ 4 OT λ5 OT λ 6 OT λ1,2 λ1-6 λ3,4 λ1-6 λ1-6 λ5,6 λ3 λ5 OR OR λ1 λ6 OR OR λ2 λ4 OR OR RP [2,1] [3,1] RP [1,2] [3,2] RP [1,3] [2,3] star coupler P. Raatikainen Switching Technology / 2003 12 - 5 Broadcast star using TDM/TDMA LCs NAS 1 [1,2] [1,3] TP OT [2,1] [2,3] TP OT [3,1] [3,2] TP OT λ1 λ1 λ1 LCs λ1 λ1 OR RP [2,1] [3,1] OR RP [1,2] [3,2] OR RP [1,3] [2,3] λ1 star coupler P. Raatikainen Switching Technology / 2003 12 - 6
- 309. Effect of propagationdelay on TDM/TDMA OT1 [1,2]1 [1,2]2 [1,3]1 [1,2]2 From 1 [2,3]2 From 2 From 1 F1 From 2 From 1 F1 From 2 F1 From 2 F2 From 1 P. Raatikainen From 2 F2 From 1 OR2 OR3 [1,3]1 [2,3]1 OT2 Coupler [1,2]1 From 1 A TDM/TDMA schedule From 2 F2 Switching Technology / 2003 12 - 7 Broadcast star using TDM/T-WDMA in FT-TR mode LCs fixed [1,2] [1,3] TP OT [2,1] [2,3] TP OT [3,1] [3,2] TP OT NAS 1 λ1 λ2 λ3 tunable λ1-3 λ1-3 λ1-3 LCs λ2 λ3 OR RP [2,1] [3,1] λ1 λ3 OR RP [1,2] [3,2] λ1 λ2 OR RP [1,3] [2,3] star coupler P. Raatikainen Switching Technology / 2003 12 - 8
- 310. Broadcast star usingTDM/T-WDMA in TT-FR mode LCs [1,2] [1,3] [2,1] [2,3] [3,1] [3,2] tunable TP λ2 OT λ3 TP λ1 OT λ3 TP λ1 OT λ2 NAS 1 fixed λ1 λ2,3 λ1,3 λ1,2 λ1-3 λ1-3 λ1-3 λ2 λ3 LCs OR RP [2,1] [3,1] OR RP [1,2] [3,2] OR RP [1,3] [2,3] star coupler P. Raatikainen Switching Technology / 2003 12 - 9 Channel allocation schedules for circuit switching WDM/WDMA λ1 λ2 λ3 λ4 [1,2] [1,2] [1,2] [1,2] [1,3] [1,3] [1,3] [1,3] [2,1] [2,1] [2,1] [2,1] TDM/T-WDMA with FT-TR λ1 [1,2] [1,3] [1,2] [1,3] λ2 [2,3] [2,1] [2,3] [2,1] λ3 [3,1] [3,2] [3,1] [3,2] TDM/T-WDMA with TT-FR λ1 [2,1] [3,1] [2,1] [3,1] λ2 [3,2] [1,2] [3,2] [1,2] λ3 [1,3] [2,3] [1,3] [2,3] [2,3] [2,3] [2,3] [2,3] λ5 [3,1] [3,1] [3,1] [3,1] λ6 [3,2] [3,2] [3,2] [3,2] frame TDM/TDMA frame frame Channel allocation schedule (CAS) should be - realizable = only one LC per each OT and time-slot - collision-free = only one LC per each λ and time-slot - conflict-free = only one LC per each OR and time-slot λ1 [1,2] [1,3] [2,1] [2,3] [3,1] [3,2] [1,2] [1,3] [2,1] [2,3] [3,1] [3,2] frame P. Raatikainen Switching Technology / 2003 12 - 10
- 311. Packet switching inthe optical layer • Fixed capacity allocation, produced by periodic frames, is well adapted to stream-type traffic. However, in the case of bursty packet traffic this approach may produce a very poor performance • By implementing packet switching in the optical layer, it is possible to maintain a very large number of LCs simultaneously using dynamic capacity allocation - packets are processed in TPs/RPs of the NASs (but not in ONNs) - TPs can schedule packets based on instantaneous demand - as before, broadcast star is used as a shared medium - control of this shared optical medium requires a Medium Access Control (MAC) protocol NAS equipped for packet switching TP MAC RP P. Raatikainen OT ONN OR Switching Technology / 2003 12 - 11 Additional comments on static networks • The broadcast-and-select principle cannot be scaled to large networks for three reasons: – Spectrum use: Since all transmissions share the same fibers, there is no possibility of optical spectrum reuse => the required spectrum typically grows at least proportionally to the number of transmitting stations – Protocol complexity: Synchronization problems, signaling overhead, time delays, and processing complexity all increase rapidly with the number of stations and with the number of LCs. – Survivability: There are no alternate routes in case of a failure. Furthermore, a failure at the star coupler can bring the whole network down. – For these reasons, a practical limit on the number of stations in a broadcast star is approximately 100 P. Raatikainen Switching Technology / 2003 12 - 12
- 312. Contents • • • • Static networks Wavelength RoutedNetworks (WRN) Linear Lightwave Networks (LLN) Logically Routed Networks (LRN) P. Raatikainen Switching Technology / 2003 12 - 13 Wavelength Routed Networks (WRN) • Wavelength routed network (WRN) is a purely optical network – each λ-channel can be recognized in the ONNs (= wavelength selectivity) and routed individually – ONNs are typically wavelength selective crossconnects (WSXC) • network is dynamic (allowing switched connections) • a static WRN (allowing only dedicated connections) can be built up using static wavelength routers • All optical paths and connections are point-to-point – each point-to-point LC corresponds to a point-to-point OC – full point-to-point logical/optical connectivity among N stations requires N-1 transceivers in each NAS – multipoint logical connectivity only possible by several point-to-point optical connections using WDM/WDMA P. Raatikainen Switching Technology / 2003 12 - 14
- 313. Static wavelength routedstar • Full point-to-point logical/optical connectivity in a static wavelength routed star with N nodes can be realized by – WDM/WDMA • a whole λ-channel allocated for each LC • N-1 wavelengths needed - spectrum reuse factor is N (= N(N-1) optical connections / N-1 wavelengths) • N-1 transceivers needed in each NAS P. Raatikainen Switching Technology / 2003 12 - 15 Static wavelength routed star using WDM/WDMA LCs NAS 1 [1,2] [1,3] TP [2,1] [2,3] TP [3,1] [3,2] TP λ1 OT λ 2 OT λ2 OT λ 1 OT λ1 OT λ 2 OT λ1,2 λ1,2 λ1,2 LC’ λ1,2 λ1,2 λ1,2 λ2 λ1 OR OR λ1 λ2 OR OR λ2 λ1 OR OR RP [2,1] [3,1] RP [1,2] [3,2] RP [1,3] [2,3] wavelength router P. Raatikainen Switching Technology / 2003 12 - 16
- 314. Routing and channelassignment • Consider a WRN equipped with WSXCs (or wavelength routers) – no wavelength conversion possible • Establishing an optical connection requires – channel assignment – routing • Channel assignment (executed in the λ-channel sublayer) involves – allocating an available wavelength to the connection and – tuning the transmitting and receiving station to the assigned wavelength • Routing (executed in the optical path sublayer) involves – determining a suitable optical path for the assigned λ-channel and – setting the switches in the network nodes to establish that path P. Raatikainen Switching Technology / 2003 12 - 17 Channel assignment constraints • Following two channel assignment constraints apply to WRNs • wavelength continuity: wavelength of each optical connection remains the same on all links it traverses from source to destination • this is unique to transparent optical networks, making routing and wavelength assignment a more challenging task than the related problem in conventional networks 1 • distinct channel assignment (DCA): all optical 2 connections sharing a common fiber must be assigned distinct λ-channels (i.e. distinct wavelengths) 3 - this applies to access links as well as internodal links - although DCA is necessary to ensure distinguishability 1 of signals on the same fiber, it is possible (and generally advantageous) to reuse the same wavelength on 2 fiber-disjoint paths 3 P. Raatikainen Switching Technology / 2003 1 2 3 1 2 3 12 - 18
- 315. Routing and ChannelAssignment (RCA) problem • Routing and channel assignment (RCA) is the fundamental control problem in large optical networks – Generally, the RCA problem for dedicated connections can be treated off-line => computationally intensive optimization techniques are appropriate – On the other hand, RCA decisions for switched connections must be made rapidly, and hence suboptimal heuristics must normally be used 1 3 5 1 3 (1,3)1 5 1 (3,5)1 3 (1,3)1 (3,5)1 (4,6)2 2 4 6 2 dedicated P. Raatikainen 4 5 (4,6)2 6 2 switched 1 4 6 switched 2 Switching Technology / 2003 12 - 19 Example bi-directional ring with elementary NASs • Consider a bi-directional ring of 5 nodes and 3 stations with single access fiber pairs • Full point-to-point logical/optical connectivity requires 2 - 4 wavelengths => spectrum reuse factor is 20/4 = 5 physical topology - 4 transceivers in each NAS 3 2 1 2 5 1 Fiber from ONN1 to ONN2 P. Raatikainen Switching Technology / 2003 1 2 3 4 5 1 -1R 3R 4L 2L 2 1L -4R 2R 3L 4 L 5 R 1 3 2L 3L -1R 4R 4 3R 4L 2L -1R 5 4R 2R 1L 3L -- RCA 12 - 20
- 316. Example bi-directional ringwith nonblocking NASs • Consider a bi-directional ring of 5 nodes and 3 stations with two access fiber pairs • Full point-to-point logical/optical connectivity requires 2 - 3 wavelengths => spectrum reuse factor is 20/3 = 6.67 physical topology - 4 transceivers in each NAS 3 2 1 2 5 1 1 2 3 4 5 1 -1R 2R 2L 1L Fiber from ONN1 to ONN2 P. Raatikainen 2 1L -1R 3R 3L 4 L 5 R 1 3 2L 1L -2R 1R 4 2R 3L 2L -3R 5 1R 3R 1L 3L -- RCA Switching Technology / 2003 12 - 21 Example mesh network with elementary NASs • Consider a mesh network of 5 nodes and stations with single access fiber pairs • Full point-to-point logical/optical connectivity requires – 4 wavelengths => spectrum reuse factor is 20/4 = 5 – 4 transceivers in each NAS – despite the richer physical topology, no difference with the corresponding bidirectional ring (thus, the access fibers are the bottleneck) 4 3 5 1 2 physical topology RCA? P. Raatikainen Switching Technology / 2003 12 - 22
- 317. Example mesh networkwith nonblocking NASs • Consider a mesh network of 5 nodes and stations with three/four access fiber pairs • Full point-to-point logical/optical connectivity requires – only 2 wavelengths => spectrum reuse factor is 20/2 = 10 – 4 transceivers in each NAS 4 3 5 1 2 physical topology RCA? P. Raatikainen Switching Technology / 2003 12 - 23 Contents • • • • Static networks Wavelength Routed Networks (WRN) Linear Lightwave Networks (LLN) Logically Routed Networks (LRN) P. Raatikainen Switching Technology / 2003 12 - 24
- 318. Linear Lightwave Networks(LLN) • Linear lightwave network (LLN) is a purely optical network – nodes perform (only) strictly linear operations on optical signals • This class includes – both static and wavelength routed networks – but also something more • The most general type of LLN has waveband selective LDC nodes – LDC performs controllable optical signal dividing, routing and combining – these functions are required to support multipoint optical connectivity • Waveband selectivity in nodes means that – optical path layer routes signals as bundles that contain all λ-channels within one waveband • Thus, all layers of connectivity and their interrelations must be examined carefully P. Raatikainen Switching Technology / 2003 12 - 25 Routing and channel assignment constraints • Two constraints of WRNs need also to be satisfied by LLNs • Wavelength continuity: wavelength of each optical connection remains the same on all the links it traverses from source to destination • Distinct channel assignment (DCA): all optical connections sharing a common fiber must be assigned distinct λ-channels • Additionally, the following two routing constraints apply to LLNs • Inseparability: channels combined on a single fiber and situated within the same waveband cannot be separated within the network - this is a consequence of the fact that the LDCs operate on the aggregate power carried within each waveband • Distinct source combining (DSC): only signals from distinct sources are allowed to be combined on the same fiber - DSC condition forbids a signal from splitting, taking multiple paths, and then recombining with itself - otherwise, combined signals would interfere with each other P. Raatikainen Switching Technology / 2003 12 - 26
- 319. Inseparability 1 S1 C a A B F H 2 D 1 2 S2 2* S1 C a B F H D 1* G 3* E S2 3 P. Raatikainen S1 S2 S1 A S2 G 3* E 3 1* 2* Switching Technology/ 2003 12 - 27 Two violations of DSC C A B C A P. Raatikainen B Switching Technology / 2003 12 - 28
- 320. Inadvertent violation ofDSC 1 C S1 A 2 S2 B H F S1 + S2 D 3 P. Raatikainen d 1* S1 + S2 G f S1 + S2 + S3 E 3* S1 + S2 + S3 S3 2* S1 + S2 + S3 Switching Technology / 2003 12 - 29 Avoidance of DSC violations 1 C S1 A 2 S2 B F H D 3 1 2 S2 H F b D 3 P. Raatikainen S1 + S2 + S3 C B h S3 d 3* 2* S2 + S3 c a G S2 + S3 E S3 S1 A 1* S1 f E S1 + S2 Switching Technology / 2003 1* G S1 + S2 + S3 3* 2* 12 - 30
- 321. Color clash 1 S1 A 2 S2 C (1, 1*)1 B H F D (2,2*)1 d 3* 2* C S1 A 2 S2 F H D S3 d S2 1* S1 B 3 P. Raatikainen G E 3 1 1* S1 f S2 + S3 E G 3* (3, 3*)2 2* Switching Technology / 2003 12 - 31 Power distribution • In a LDC it is possible to specify combining and dividing ratios • ratios determine how power from sources is distributed to destinations • combining and dividing ratios can be set differently for each waveband • How should these ratios be chosen? • The objective could be • to split each source’s power equally among all destinations it reaches • to combine equally all sources arriving at the same destination • Resultant end-to-end power transfer coefficients are independent of • routing paths through the network • number of nodes they traverse • order in which signals are combined and split • Coefficients depend only on • number of destinations for each source • number of sources reaching each destination P. Raatikainen Switching Technology / 2003 12 - 32
- 322. Illustration of powerdistribution (1/2)(S1+ S2) a 1/3 a’ 2/3 1 S3 b’ b (1/6) )(S1+ S2) 1 h h’ 2/3 c P. Raatikainen 1/3 c’ (2/9) )(S1+ S2)+(1/3) S3 Switching Technology / 2003 12 - 33 Multipoint subnets in LLNs • Attempts to set up several point-to-point optical connections within a common waveband leads to unintentional creation of multipoint paths => complications in routing, channel assignment and power distribution • On the other hand, waveband routing leads to more efficient use of the optical spectrum • In addition, the multipoint optical path capability is useful when creating intentional multipoint optical connections – LLNs can deliver a high degree of logical connectivity with minimal optical hardware in the access stations – this is one of the fundamental advantages of LLNs over WRNs • Multipoint optical connections can be utilized when creating a full logical connectivity among specified clusters of stations within a larger network => such fully connected clusters are called multipoint subnets (MPS) P. Raatikainen Switching Technology / 2003 12 - 34
- 323. Example - sevenstations on a mesh 4 • Consider a network containing seven stations interconnected on a LLN with a mesh physical topology and bidirectional fiber links - notation for fiber labeling: a and a´ form 4 d P. Raatikainen 5 1 5 c g 7 A 6 6 3 7 b´ a 1 C E e a fiber pair with opposite directions • Set of stations {2,3,4} should be interconnected to create a MPS with full logical connectivity • This can be achieved, e.g. by creating an optical path on a single waveband in the form of a tree joining the three stations (embedded broadcast star) f D B h 2 2 physical topology 2 2 2 2 3 3 3 3 4 4 4 4 LCG LCH Switching Technology / 2003 12 - 35 Realization of MPS by a tree embedded in mesh 4 f D 3 C Optical path g c B 2 2’ B 3’ 3 4 4’ P. Raatikainen f 2 g 3 C D 2 B g’ f’ D 3 4 4 2 f f’ g’ g c’ c 3’ 3 Switching Technology / 2003 12 - 36
- 324. Contents • Static networks •Wavelength Routed Networks (WRN) • Linear Lightwave Networks (LLN) – Seven-station example • Logically Routed Networks (LRN) P. Raatikainen Switching Technology / 2003 12 - 37 Seven-station example • Assume: – nonblocking access stations – each transmitter runs at a bit rate of R0 • Physical topologies (PT): – bi-directional ring – mesh – multistar of seven physical stars • Logical topologies (LT): – fully connected (point-to-point logical topology with 42 edges) - realized using WRN – fully shared (hypernet logical topology with a single hyperedge) - realized using a broadcast-and-select network (LLN of a single MPS) – partially shared (hypernet of seven hyperedges) - realized using LLN of seven MPSs P. Raatikainen Switching Technology / 2003 12 - 38
- 325. Physical topologies 3 G 2 A 1 ring P. Raatikainen B 3 C E 4 D 5 E 6 F G D 6 F B 2 5 E C A 7 D 1 4 5 4 7 C 3 7 1 A B 2 6 mesh multistar SwitchingTechnology / 2003 12 - 39 Fully connected LT - WRN realizations • Ring PT: – 6 λs with spectrum reuse factor of 42/6 = 7 => RCA? – 6 transceivers in each NAS ⇒ network capacity = 7*6 = 42 R0 • Mesh PT: – 4 λs with spectrum reuse factor of 42/4 = 10.5 => RCA? – 6 transceivers in each NAS ⇒ network capacity = 7*6 = 42 R0 • Multistar PT: – 2 λs with spectrum reuse factor of 42/2 = 21 => RCA? – 6 transceivers in each NAS ⇒ network capacity = 7*6 = 42 R0 P. Raatikainen Switching Technology / 2003 1 1 2 2 3 3 4 4 5 5 6 6 7 7 LCG 12 - 40
- 326. Fully shared LT- Broadcast and select network realizations • Any PT • WDM/WDMA: – 42 λs with spectrum reuse factor of 1 – 6 transceivers in each NAS ⇒ network capacity = 7*6 = 42 R0 • TDM/T-WDMA in FT-TR mode: – 7 λs with spectrum reuse factor of 1 – 1 transceiver in each NAS ⇒ network capacity = 7*1 = 7 R0 • TDM/TDMA: – 1 λ with spectrum reuse factor of 1 – 1 transceiver in each NAS ⇒ network capacity = 7*1/7 = 1 R0 P. Raatikainen 1 1 2 2 3 3 E1 4 4 5 5 6 6 7 7 LCH Switching Technology / 2003 12 - 41 Partially shared LT - LLN realizations • Note: Full logical connectivity among all stations • Mesh PT using TDM/T-WDMA in FT-TR mode: – 2 wavebands with spectrum reuse factor of 7/2 = 3.5 => RCA? – 3 λs per waveband – 3 transceivers in each NAS ⇒ network capacity = 7*3 = 21 R0 • Multistar PT using TDM/T-WDMA in FT-TR mode: – 1 waveband with spectrum reuse factor of 7/1 = 7 => RCA? – 3 λs per waveband – 3 transceivers in each NAS ⇒ network capacity = 7*3 = 21 R0 P. Raatikainen Switching Technology / 2003 E1 1 1 E2 2 2 E3 3 3 E4 4 4 E5 5 5 E6 6 6 E7 7 7 LCH 12 - 42
- 327. Contents • • • • Static networks Wavelength RoutedNetworks (WRN) Linear Lightwave Networks (LLN) Logically Routed Networks (LRN) P. Raatikainen Switching Technology / 2003 12 - 43 Logically Routed Networks (LRN) • For small networks, high logical connectivity is reasonably achieved by purely optical networks. However, when moving to larger networks, the transparent optical approach soon reaches its limits. • For example, to achieve full logical connectivity among 22 stations on a bi-directional ring using wavelength routed point-to-point optical connections 21 transceivers are needed in each NAS and totally 61 wavelengths. Economically and technologically, this is well beyond current capabilities. => we must turn to electronics (i.e. logically routed networks) • Logically routed network (LRN) is a hybrid optical network – which performs logical switching (by logical switching nodes (LSN)) on top of a transparent optical network – LSNs create an extra layer of connectivity between the end systems and NASs P. Raatikainen Switching Technology / 2003 12 - 44
- 328. Two approaches tocreate full connectivity • Multihop networks based on point-to-point logical topologies – realized by WRNs • Hypernets based on multipoint logical topologies – realized by LLNs P. Raatikainen Switching Technology / 2003 12 - 45 Point-to-point logical topologies • In a point-to-point logical topology – a hop corresponds to a logical link between two LSNs – maximum throughput is inversely proportional to the average hop count • One of the objectives of using logical switching on top of a transparent optical network is – to reduce cost of station equipment (by reducing the number of optical transceivers and complexity of optics) while maintaining high network performance • Thus, we are interested in logical topologies that – achieve a small average number of logical hops at a low cost (i.e., small node degree and simple optical components) • An example is a ShuffleNet – for example, an eight-node ShuffleNet has 16 logical links and an average hop count of 2 (if uniform traffic is assumed) – these networks are scalable to large sizes by adding stages and/or increasing the degree of the nodes P. Raatikainen Switching Technology / 2003 12 - 46
- 329. Eight-node ShuffleNet 1 2 6 3 7 4 8 4 5 6 3 4 5 2 3 4 1 2 3 6 7 8 5 2 7 1 1 8 logical topology P.Raatikainen LCG Switching Technology / 2003 12 - 47 ShuffleNet embedded in a bi-directional ring WRN • Bi-directional ring WRN with elementary NASs – 2 λs with spectrum reuse factor of 16/2 = 8 – 2 transceivers in each NAS – average hop count = 2 ⇒ network cap. = 8*2/2 = 8 R0 6 R L 1 Note: station labeling! RCA P. Raatikainen 7 2 1 2 3 4 5 6 7 8 -- -- -- -- 1L 2L -- --- -- -- -- -- -- 1R 2R -- -- -- -- 2R 1R -- --- -- -- -- -- -- 2L 1L 1R 2R -- -- -- -- -- --- -- 1L 2L -- -- -- -2L 1L -- -- -- -- -- --- -- 2R 1R -- -- -- -- 5 1 2 3 4 5 6 7 8 8 3 4 Switching Technology / 2003 12 - 48
- 330. Details of aShuffleNet node λ2 R 1 λ1, λ2 λ1, λ2 λ2 λ1, λ2 L λ1, λ2 L R 1 5 1 5 2 6 1 6 2 1 1 ONN1 1 2 1 2 OT1 5 1 OR1 OR2 TP R 6 OT2 TP RP RP 2 L 5 1 Fibers between ONN5 and ONN1 P. Raatikainen Switching Technology / 2003 12 - 49 Multipoint logical topologies • High connectivity may be maintained in transparent optical networks while economizing on optical resource utilization through the use of multipoint connections • These ideas are even more potent when combined with logical switching • For example, a ShuffleNet may be modified to a Shuffle Hypernet – an 8-node Shuffle Hypernet has 4 hyperarcs – each hyperarc presents a directed MPS that contains 2 transmitting and 2 receiving stations – an embedded directed broadcast star is created to support each MPS – for a directed star, a (physical) tree is found joining all stations in both the transmitting and receiving sets of the MPS – any node on the tree can be chosen as a root – LDCs on the tree are set to create optical paths from all stations in the transmitting set to the root node, and paths from the root to all receiving stations P. Raatikainen Switching Technology / 2003 12 - 50
- 331. Eight-node Shuffle Hypernet 1 1 2 E1 1 5 3 6 2 2 7 3 4 8 3 1 4 2 E1 3 E2 4 4 E3 5 6 5 6 E4 7 7 8 8 transformation P.Raatikainen LCH Switching Technology / 2003 12 - 51 Shuffle Hypernet embedded in a bidirectional ring LLN • Bi-directional ring LLN with elementary NASs using TDM/T-WDMA in FT-TR mode – 1 waveband with spectrum reuse factor of 4/1 = 4 E1 E2 E3 E4 a, b´, c´ e, f´, g´ g, a´, h´ c, d´, e´ root ONN5 ONN8 ONN2 ONN3 RCA P. Raatikainen outbound fibers e c f b g 6 7 a´ a waveband b f h d 4´ 1 1 1 1 h 5 inbound fibers 4 2 – 2 λs per waveband – 1 transceiver in each NAS ⇒ network cap. = 8*1/2 = 4 R0 d 8 3 4 1 Note: station and fiber labeling! Switching Technology / 2003 12 - 52
- 332. Details of nodein Shuffle Hypernet 5 w1 w1 b´ 5 w1 w1 a w1 w1 a´ 5, 2 7, 1 7, 2 b c´ 3 3´ 3 6 6´ 6 a´ 5 b 5 5´ 5 1 1, 6 RP TP OR OT 1´ 1 Fibers between ONN3 and ONN1 P. Raatikainen 6 E1 1 a 5 3 7, 1 b´ 6 c 1, 6 3, 5 2 5´ ONN5 3 E2 7 1 7, 2 1, 6 7, 1 5, 2 1 ... Switching Technology / 2003 12 - 53 Contents • • • • Static networks Wavelength Routed Networks (WRN) Linear Lightwave Networks (LLN) Logically Routed Networks (LRN) – Virtual connections: an ATM example P. Raatikainen Switching Technology / 2003 12 - 54
- 333. Virtual connections -an ATM example • Recall the problem of providing full connectivity among five locations – suppose each location contains a number of end systems that access the network through an ATM switch. The interconnected switches form a transport network of 5*4 = 20 VPs. • The following five designs are now examined and compared: – – – – – Stand-alone ATM star Stand-alone ATM bi-directional ring ATM over a network of SONET cross-connects ATM over a WRN ATM over a LLN • Traffic demand: each VP requires 600 Mbits/s (≈ STM-4/STS-12) • Optical resources: λ-channels and transceivers run at the rate of 2.4 Gbits/s (≈ STM-16/STS-48) P. Raatikainen Switching Technology / 2003 12 - 55 Stand-alone ATM networks 1 5 1 2 6 4 5 3 2 4 3 ATM switch/cross-connect with transceiver P. Raatikainen Switching Technology / 2003 12 - 56
- 334. Embedded ATM networks A A S A 5 2 S 2 S 6 S 6 A 4 A A P.Raatikainen S S 5 A 3 4 3 Optical network ATM switch A 2 A A DCS network A A 1 A 3 S S 4 S A S 1 1 S 5 S A A S SDH/SONET DCS Shared medium ONN Switching Technology / 2003 12 - 57 Case 1 - Stand-alone ATM star • Fiber links are connected directly to ports on ATM switches, creating a pointto-point optical connection for each fiber – each link carries 4 VPs in each direction ⇒ each optical connection needs 2.4 Gbits/s, which can be accomodated using a single λ-channel – one optical transceiver is needed to terminate each end of a link, for a total of 10 transceivers in the network • Processing load is unequal: – end nodes process their own 8 VPs carrying 4.8 Gbits/s – center node 6 processes all 20 VPs carrying 12.0 Gbits/s ⇒ bottleneck • Inefficient utilization of fibers, since – even though only one λ-channel is used, the total bandwidth of each fiber is dedicated to this system • Poor survivability, since – if any link is cut, network is cut in two – if node 6 fails, the network is completely distroyed P. Raatikainen Switching Technology / 2003 12 - 58
- 335. Case 2 -Stand-alone ATM bi-directional ring • Fiber links are connected directly to ports on ATM switches, creating a pointto-point optical connection for each fiber – assuming shortest path routing, each link carries 3 VPs in each direction ⇒ each optical connection needs 1.8 Gbits/s, which can be accommodated using a single λ-channel (leaving 25% spare capacity) – 1 optical transceiver is needed to terminate each end of a link, for a total of 10 transceivers in the network • Equal processing load: – each ATM node processes its own 8 VPs and 2 additional transit VPs carrying an aggregate traffic of 6.0 Gbits/s • Thus, – no processing bottleneck – the same problem with optical spectrum allocation as in case 1 – but better survivability, since network can recover from any single link cut or node failure by rerouting the traffic P. Raatikainen Switching Technology / 2003 12 - 59 Case 3 - ATM embedded in DCS network • ATM end nodes access DCSs through 4 electronic ports • Fiber links are now connected to ports on DCSs, creating a point-to-point optical connection for each fiber – each link carries 4 VPs in each direction => each optical connection needs 2.4 Gbits/s, which can be accommodated using a single λ-channel – again, 1 optical transceiver is needed to terminate each end of a link • Processing load is lighter – ATM nodes process their own 8 VPs carrying 4.8 Gbits/s – but it is much simpler to perform VP cross-connect functions at the STM4/STS-12 level than at the ATM cell level (as was done in case 1) – a trade-off must be found between optical spectrum utilization and costs – the more λ-channels on each fiber (to carry “background” traffic), the more (expensive) transceivers are needed • Survivability and reconfigurability are good – since alternate paths and additional bandwidth exist in the DCS network P. Raatikainen Switching Technology / 2003 12 - 60
- 336. Case 4 -ATM embedded in a WRN • DCSs are now replaced by optical nodes containing WSXCs • Each ATM end node is connected electronically to a NAS • Each VP in the virtual topology must be supported by – a point-to-point optical connection occupying one λ-channel – thus, 4 tranceivers are needed in each NAS (and totally 20 transceivers) – however, no tranceivers are needed in the network nodes • With an optimal routing and wavelength assignment, – the 20 VPs can be carried using 4 wavelengths (= 800 GHz) • Processing load is very light – due to optical switching (without optoelectronic conversion at each node) – Note: ATM nodes still process their own 8 VPs carrying 4.8 Gbits/s • As in case 3, survivability and reconfigurability are good – since alternate paths and additional bandwidth exist in the underlying WRN P. Raatikainen Switching Technology / 2003 12 - 61 Case 5 - ATM embedded in an LLN • WSXCs are now replaced by LDCs • A single waveband is assigned to the ATM network, and the LDCs are set to create an embedded tree (MPS) on that waveband – the 20 VPs are supported by a single hyperedge in the logical topology – since each λ-channel can carry 4 VPs, 5 λ-channels are needed totally, all in the same waveband (= 200 GHz) – only 1 transceiver is needed in each NAS (and totally 5 transceivers) using TDM/T-WDMA in FT-TR mode • Processing load is again very light – due to optical switching (without optoelectronic conversion at each node) – Note: ATM nodes still process their own 8 VPs carrying 4.8 Gbits/s • As in cases 3 and 4, survivability and reconfigurability are good – since alternate paths and additional bandwidth exist in the underlying LLN P. Raatikainen Switching Technology / 2003 12 - 62
- 337. Comparison of ATMnetwork realizations Case Optical spectrum usage 1 2 3 4 5 Very high Very high Lowest Medium Low P. Raatikainen Number of optical transceivers 10 10 10 20 5 Node processing load Very high High Medium Very low Very low Switching Technology / 2003 Others Poor survivability High DCS Rapid tunability required, optical multi-cast possible 12 - 63
- 338. Optical switches Switching TechnologyS38.165 http://www.netlab.hut.fi/opetus/s38165 P. Raatikainen Switching Technology / 2003 13 - 1 Optical switches • Components and enabling technologies • Contention resolution • Optical switching schemes P. Raatikainen Switching Technology / 2003 13 - 2 1
- 339. Components and enablingtechnologies • Optical fiber • Light sources, optical transmitters • Photodetectors, optical receivers • Optical amplifiers • Wavelength converters • Optical multiplexers and demultiplexers • Optical add-drop multiplexers • Optical cross connects • WDM systems P. Raatikainen Switching Technology / 2003 13 - 3 Optical fiber • Optical fiber is the most important transport medium for highspeed communications in fixed networks • Pros – immune to electromagnetic interference – does not corrode – huge bandwidth (25 Tbit/s) • Cons – connecting fibers requires special techniques (connectors, specialized personnel to splice and connect fibers) – does not allow tight bending • An optical fiber consists of – ultrapure silica – mixed with dopants to adjust the refractive index P. Raatikainen Switching Technology / 2003 13 - 4 2
- 340. Optical fiber (cont.) •Optical cable consists of several layers – silica core – cladding, a layer of silica with a different mix of dopants – buffer coating, which absorbs mechanical stresses – coating is covered by a strong material such as Kevlar – outermost is a protective layer of plastic material Plastic Cladding Glassy core Buffer coating KevlarTM Cross section (not to scale) P. Raatikainen Switching Technology / 2003 13 - 5 Optical fiber (cont.) • Fiber cable consists of a bundle of optical fibers, up to 432 fibers. • Refractive index profile of a fiber is carefully controlled during manufacturing phase n(x) n • Typical refractive index profiles Step index – step index profile n profile – graded index profile n 2 1 x Cladding 2 Core fiber n(x) n2 Graded index profile n1 x P. Raatikainen Switching Technology / 2003 n2 ∆ 13 - 6 3
- 341. Optical fiber (cont.) •Light beams are confined in the fiber - by total reflection at the core-cladding interface in step-index fibers - by more gradual refraction in graded index fibers n2 n1 Step index Graded index P. Raatikainen Switching Technology / 2003 13 - 7 Optical fiber (cont.) • Fiber can be designed to support • several propagation modes => multimode fiber • just a single propagation mode => single-mode fiber D = 125 ± 2 µm D = 125 ± 2 µm d = 50 µm d = 8.6 - 9.5 µm Core fiber ncore Cladding nclad Cladding nclad Multimode fiber (many directional rays) P. Raatikainen Single-mode fiber (one directional rays due to small d/D ratio) Switching Technology / 2003 13 - 8 4
- 342. Optical fiber (cont.) •Multimode graded index fiber • small delay spread • 1% index difference between core and cladding amounts to 1-5 ns/km delay spread • easy to splice and to couple light into it • bit rate limited up to 100 Mbit/s for lengths up to 40 km • fiber span without amplification is limited • Single mode fiber • almost eliminates delay spread • more difficult to splice and to exactly align two fibers together • suitable for transmitting modulated signals at 40 Gbit/s or higher and up to 200 km without amplification P. Raatikainen Switching Technology / 2003 13 - 9 Optical fiber characteristics • Dispersion is an undesirable phenomenon in optical fibers • causes an initially narrow light pulse to spread out as it propagates along the fiber • There are different causes for dispersion • modal dispersion • chromatic dispersion • Modal dispersion • occurs in multimode fibers • caused by different (lengths) propagation paths of different modes • Chromatic dispersion • material properties of fiber, such as dielectric constant and propagation constant, depend on the frequency of the light • each individual wavelength of a pulse travels at different speed and arrives at the end of the fiber at different time P. Raatikainen Switching Technology / 2003 13 - 10 5
- 343. Optical fiber characteristics(cont.) • Chromatic dispersion (cont.) • dispersion is measured in ps/(nm*km), i.e. delay per wavelength variation and fiber length • Dispersion depends on the wavelength • at some wavelength dispersion may be zero • in conventional single mode fiber this typically occurs at 1.3 µm - below, dispersion is negative, above it is positive • For long-haul transmission, single mode fibers with specialized index of refraction profiles have been manufactured • dispersion-shifted fiber (DSF) • zero-dispersion point is shifted to 1.55 µm P. Raatikainen Switching Technology / 2003 13 - 11 Optical fiber characteristics (cont.) • Fiber attenuation is the most important transmission characteristic • limits the maximum span a light signal can be transmitted without amplification • Fiber attenuation is caused by light scattering on • fluctuations of the refractive index • imperfections of the fiber • impurities (metal ions and OH radicals have a particular effect) • A conventional single-mode fiber has two low attenuation ranges • one at about 1.3 µm • another at about 1.55 µm P. Raatikainen Switching Technology / 2003 13 - 12 6
- 344. Optical fiber characteristics(cont.) • Between these ranges is a high attenuation range (1.35-1.45 µm), with a peak at 1.39 µm, due to OH radical • special fibers almost free of OH radicals have been manufactured • such fibers increase the usable bandwidth by 50% • the whole range from 1.335 µm to 1.625 µm is usable, allowing about 500 WDM channels at 100 GHz channel spacing P. Raatikainen Switching Technology / 2003 13 - 13 Optical fiber characteristics (cont.) Transmitted optical loss or attenuation (dB) Without OH- Absorption due to OH(peak at 1385 nm) Zero-dispersion line 1.2 1.4 1.6 λ (µm) µ • The attenuation is measured in dB/km; typical values are • 0.4 dB/km at 1.31 µm • 0.2 dB/km at 1.55 µm • for comparison, attenuation in ordinary clear glass is about 1 dB/cm = 105 dB/km P. Raatikainen Switching Technology / 2003 13 - 14 7
- 345. Light sources andoptical transmitters • One of the key components in optical communications is the monochromatic (narrow band) light source • Desirable properties • compact, monochromatic, stable and long lasting • Light source may be one of the following types: • continuous wave (CW); emits at a constant power; needs an external modulator to carry information • modulated light; no external modulator is necessary • Two most popular light sources are • light emitting diode (LED) • semiconductor laser P. Raatikainen Switching Technology / 2003 13 - 15 Light emitting diode (LED) • LED is a monolithically integrated p-n semiconductor diode • Emits light when voltage is applied across its two terminals • In the active junction area, electrons in the conduction band and holes in the valence band are injected • Recombination of the electron with holes releases energy in the form of light • Can be used either as a CW light source or modulated light source (modulated by the injection current) Terminal P-type Emitted light Active junction N-type Terminal P. Raatikainen Switching Technology / 2003 13 - 16 8
- 346. Characteristics of LED • • • • • Relativelyslow - modulation rate < 1 Gbit/s Bandwidth depends on the material - relatively wide spectrum Amplitude and spectrum depend on temperature Low cost Transmits light in wide cone - suitable for multimode fibers 1.0 Relative intensity As temperature rises, spectrum shifts and intensity decreases 0.5 0.0 P. Raatikainen 45 oC 50 oC ~690 ~ 700 λ (nm) Switching Technology / 2003 13 - 17 Semiconductor laser • LASER (Light amplification by stimulated emission of radiation) • Semiconductor laser is also known as laser diode and injection laser • Operation of a laser is the same as for any other oscillator - gain (amplification) and feedback • As a device semiconductor laser is similar to a LED (i.e. p-n semiconductor diode) • A difference is that the ends of the active junction area are carefully cleaved and act as partially reflecting mirrors • this provides feedback • The junction area acts as a resonating cavity for certain frequencies (those for which the round-trip distance is multiple of the wavelength in the material - constructive interference) P. Raatikainen Switching Technology / 2003 13 - 18 9
- 347. Semiconductor laser (cont.) •Light fed back by mirrors is amplified by stimulated emission • Lasing is achieved above a threshold current where the optical gain is sufficient to overcome losses (including the transmitted light) from the cavity + p Cleaved surface n i Cleaved surface P. Raatikainen Switching Technology / 2003 13 - 19 Semiconductor laser (cont.) • Cavity of a Fabry-Perot laser can support many modes of oscillation => it is a multimode laser • In single frequency operation, all but a single longitudinal mode must be suppressed - this can be achieved by different approaches: • cleaved-coupled cavity (C3) lasers • external cavity lasers p p n p p p n • distributed Bragg reflector (DBR) lasers Active Active • distributed feedback (DFB) lasers layer layer Λ Diffraction • The most common light sources gratings for high-bit rate, long-distance Guiding layer • transmission are the DBR and DFB lasers. P. Raatikainen Switching Technology / 2003 13 - 20 10
- 348. Semiconductor laser (cont.) •Laser tunability is important for multiwavelength network applications • Slow tunability (on ms time scale) is required for setting up connections in wavelength or waveband routed networks • achieved over a range of 1 nm via temperature control • Rapid tunability (on ns-µs time scale) is required for TDM-WDM multiple access applications • achieved in DBR and DFB lasers by changing the refractive index, e.g. by changing the injected current in grating area • Another approach to rapid tunability is to use multiwavelength laser arrays • one or more lasers in the array can be activated at a time P. Raatikainen Switching Technology / 2003 13 - 21 Semiconductor laser (cont.) • Lasers are modulated either directly or externally • direct modulation by varying the injection current • external modulation by an external device, e.g. Mach-Zehnder interferometer V Light input Ii Modulated light Io 0 Mach-Zehnder interferometer P. Raatikainen Switching Technology / 2003 13 - 22 11
- 349. Photodetectors and optical receivers •A photodetector converts the optical signal to a photocurrent that is then electronically amplified (front-end amplifier) • In a direct detection receiver, only the intensity of the incoming signal is detected • in contrast to coherent detection, where the phase of the optical signal is also relevant • coherent systems are still in research phase • Photodetectors used in optical transmission systems are semiconductor photodiodes • Operation is essentially reverse of a semiconductor optical amplifier • junction is reverse biased • in absence of optical signal only a small minority carrier current is flowing (dark current) P. Raatikainen Switching Technology / 2003 13 - 23 Photodetectors and optical receivers (cont.) • Operation is essentially reverse of a semiconductor optical amplifier (cont.) • a photon impinging on surface of a device can be absorbed by an electron in the valence band, transferring the electron to the conduction band • each excited electron contributes to the photocurrent • PIN photodiodes (p-type, intrinsic, n-type) • An extra layer of intrinsic semiconductor material is sandwiched between the p and n regions • Improves the responsivity of the device • captures most of the light in the depletion region P. Raatikainen Switching Technology / 2003 13 - 24 12
- 350. Photodetectors and optical receivers(cont.) • Avalanche photodiodes (APD) • In a photodiode, only one electron-hole pair is produced by an absorbed photon • This may not be sufficient when the optical power is very low • The APD resembles a PIN • an extra gain layer is inserted between the i (intrinsic) and n layers • a large voltage is applied across the gain layer • photoelectrons are accelerated to sufficient speeds • produce additional electrons by collisions => avalanche effect • largely improved responsivity P. Raatikainen Switching Technology / 2003 13 - 25 Optical amplifiers • Optical signal propagating in a fiber suffers attenuation • Optical power level of a signal must be periodically conditioned • Optical amplifiers are key components in long haul optical systems • An optical amplifier is characterized by • gain - ratio of output power to input power (in dB) • gain efficiency - gain as a function of input power (dB/mW) • gain bandwidth - range of frequencies over which the amplifier is effective • gain saturation - maximum output power, beyond which no amplification is reached • noise - undesired signal due to physical processes in the amplifier P. Raatikainen Switching Technology / 2003 13 - 26 13
- 351. Optical amplifiers (cont.) •Types of amplifiers • Electro-optic regenerators • Semiconductor optical amplifiers (SOA) • Erbium-doped fiber amplifiers (EDFA) P. Raatikainen Switching Technology / 2003 13 - 27 Electro-optic regenerators • Optical signal is • received and transformed to an electronic signal • amplified in electronic domain • converted back to optical signal at the same wavelength λ O/E Amp E/O Fiber λ Fiber Optical receiver Photonic domain Optical transmitter Electronic domain Photonic domain O/E - Optical to Electronic E/O - Electronic to Optical Amp - Amplifier P. Raatikainen Switching Technology / 2003 13 - 28 14
- 352. Semiconductor optical amplifiers (SOA) •Structure of SOA is similar to that of a semiconductor laser • It consists of an active medium (p-n junction) in the form of waveguide - usually made of InGaAs or InGaAsP • Energy is provided by injecting electric current over the junction Current pump AR Weak input signal Fiber P. Raatikainen AR OA Amplified output signal Switching Technology / 2003 Fiber 13 - 29 Semiconductor optical amplifiers (cont.) • SOAs are small, compact and can be integrated with other semiconductor and optical components • They have large bandwidth and relatively high gain (20 dB) • Saturation power in the range of 5-10 dBm • SOAs are polarization dependent and thus require a polarizationmaintaining fiber • Because of nonlinear phenomena SOAs have a high noise figure and high cross-talk level P. Raatikainen Switching Technology / 2003 13 - 30 15
- 353. Erbium-doped fiber amplifiers (EDFA) •EDFA is a very attractive amplifier type in optical communications systems • EDFA is a fiber segment, a few meters long, heavily doped with erbium (a rare earth metal) • Energy is provided by a pump laser beam Pump (980 or 1480 nm at 3 W) EDFA Weak signal in Fiber Isolator P. Raatikainen Fiber Amplified signal out Isolator Fiber Switching Technology / 2003 13 - 31 Erbium-doped fiber amplifiers (cont.) • Amplification is achieved by quantum mechanical phenomenon of stimulated emission • erbium atoms are excited to a high energy level by pump laser signal • they fall to a lower metastable (long-lived, 10 ms) state • an arriving photon triggers (stimulates) a transition to the ground level and another photon of the same wavelength is emitted Excited erbium atoms at high energy level Longer wavelenght source (1480 nm) ~1 µs Atoms at metastable energy (~10 ms) Short- wavelenght source (980 nm) Stimulated emission (1520 - 1620 nm) Erbium atoms at low energy level P. Raatikainen Switching Technology / 2003 13 - 32 16
- 354. Erbium-doped fiber amplifiers (cont.) •EDFAs have a high pump power utilization (> 50 %). • Directly and simultaneously amplify a wide wavelength band (> 80 nm in the region 1550 nm) with a relatively flat gain • Flatness of gain can be improved with gain-flattening optical filters • Gain in excess of 50 dB • Saturation power is as high as 37 dBm • Low noise figure • Transparent to optical modulation format • Polarization independent • Suitable for long-haul applications • EDFAs are not small and cannot easily be integrated with other semiconductor devices P. Raatikainen Switching Technology / 2003 13 - 33 Wavelength converters Wavelength converters • Enable optical channels to be relocated • Achieved in optical domain by employing nonlinear phenomena Types of wavelength converters • Optoelectronic approach • Optical gating - cross-gain modulation • Four-wave mixing P. Raatikainen Switching Technology / 2003 13 - 34 17
- 355. Wavelength converters optoelectronicapproach • Simplest approach • Input signal is • received • converted to electronic form • regenerated • transmitted using a laser at a different wavelength. λs P. Raatikainen Receiver Regenerator Transmitter Switching Technology / 2003 λp 13 - 35 Optical gating cross-gain modulation • Makes use of the dependence of the gain of a SOA (semiconductor optical amplifier) on its input power • Gain saturation occurs when high optical power is injected Signal λs • carrier concentration is depleted Signal λp Filter λp SOA • gain is reduced Probe λp • Fast • can handle 10 Gbit/s rates Signal Carrier density Gain Sprobe output Time P. Raatikainen Switching Technology / 2003 13 - 36 18
- 356. Four-wave mixing • Four-wavemixing is usually an undesirable phenomenon in fibers • Can be exploited to achieve wavelength conversion • In four-wave mixing, three waves at frequencies f1, f2 and f3 produce a wave at the frequency f1 + f2 - f3 • When • f1 = fs (signal) • f2 = f3 = fp (pump) => a new wave is produces at 2fp - fs • Four-wave mixing can be enhanced by using SOA to increase the power levels • Other wavelengths are filtered out P. Raatikainen Switching Technology / 2003 13 - 37 Four-wave mixing (cont.) P. Raatikainen fp 2fp- fs fp fs fs 2fs- fp 2fp- fs SOA Switching Technology / 2003 Filter 2fp- fs 13 - 38 19
- 357. Optical multiplexers and demultiplexers •An optical multiplexer receives many wavelengths from many fibers and converges them into one beam that is coupled into a single fiber • An optical demultiplexer receives a beam (consisting of multiple optical frequencies) from a fiber and separates it into its frequency components, which are directed to separate fibers (a fiber for each frequency) λ1 λ2 λ1 λ2 , …,λN λ1 ,λ2 Optical multiplexer P. Raatikainen ... ... λ1 ,λ2 λN , …,λN λN Optical demultiplexer Switching Technology / 2003 13 - 39 Prisms and diffraction gratings • Prisms and diffraction gratings can be used to achieve these functions in either direction (reciprocity) • in both of these devices a polychromatic parallel beam impinging on the surface is separated into frequency components leaving the device at different angles • based on different refraction (prism) or diffraction (diffraction grating) of different wavelengths λ1 λ2 Fibers λ1 λ2 λN Multiplexed beam λ 1+ λ2+ ...+λN λ Diffraction grating Incident beam λ 1+ λ2+ ...+λN λ Lens P. Raatikainen Diffracted wavelenghts ... ... λN Fibers Lens Switching Technology / 2003 13 - 40 20
- 358. Prisms and diffractiongratings (cont.) n1 Multiplexed beam λ1+ λ2+ ...+λN λ λ1 λ2 λ3 n2 ... Fiber Lens Prism λN Lens n1 λ1 λ2 λ3 n2 Multiplexed beam λ1+ λ2+ ...+λN λ ... λN P. Raatikainen Switching Technology / 2003 13 - 41 Arrayed waveguide grating (AWG) • AWGs are integrated devices based on the principle of interferometry • a multiplicity of wavelengths are coupled to an array of waveguides with different lengths • produces wavelength dependent phase shifts • in the second cavity the phase difference of each wavelengths interferes in such a manner that each wavelength contributes maximally at one of the output fibers • Reported systems • SiO2 AWG for 128 channels with 250 GHz channel spacing • InP AWG for 64 channels with 50 GHz channel spacing w1 Array of waveguides λ1+ λ2+ ...+λN λ S1 wN S 2 Array of fibers ... λ1 λN P. Raatikainen Switching Technology / 2003 13 - 42 21
- 359. Optical add-drop multiplexers (OADM) •Optical multiplexers and demultiplexers are components designed for wavelength division (WDM) systems • multiplexer combines several optical signals at different wavelengths into a single fiber • demultiplexer separates a multiplicity of wavelengths in a fiber and directs them to many fibers • The optical add-drop multiplexer • selectively removes (drops) a wavelength from the multiplex • then adds the same wavelength, but with different data λ1, λ2, ... ,λN λ2, ... ,λN λ1, λ2, ... ,λN OADM λ1 P. Raatikainen λ1 Switching Technology / 2003 13 - 43 Optical add-drop multiplexers (cont.) • An OADM may be realized by doing full demultiplexing and multiplexing of the wavelengths • a demultiplexed wavelength path can be terminated and a new one created OADM λ1, λ2, ... ,λ N λ OA λ1, λ2, ... ,λN-1 λ λN P. Raatikainen OA λ1, λ2, ... ,λ N λ λN Switching Technology / 2003 13 - 44 22
- 360. Optical cross-connects • Channelcross-connecting is a key function in communication systems • Optical cross-connection may be accomplished by • hybrid approach: converting optical signal to electronic domain, using electronic cross-connects, and converting signal back to optical domain • all-optical switching: cross-connecting directly in the photonic domain • Hybrid approach is currently more popular because the all-optical switching technology is not fully developed • all optical NxN cross-connects are feasible for N = 2…32 • large cross-connects ( N ∼1000) are in experimental or planning phase • All-optical cross-connecting can be achieved by • optical solid-state devices (couplers) • electromechanical mirror-based free space optical switching devices P. Raatikainen Switching Technology / 2003 13 - 45 Solid-state cross-connects • Based on semiconductor directional couplers • Directional coupler can change optical property of the path Propagation constant • polarization control (voltage) Lightguide • propagation constant • absorption index Signal “on” Signal in • refraction Signal “off” • Optical property may be changed by means of • heat, light, mechanical pressure • current injection, electric field • Technology determines the switching speed, for instance • LiNbO3 crystals: order of ns • SiO2 crystals: order of ms P. Raatikainen Switching Technology / 2003 13 - 46 23
- 361. Solid-state cross-connects (cont.) •A multiport switch, also called a star coupler, is constructed by employing several 2x2 directional couplers • For instance, a 4x4 switch can be constructed from six 2x2 directional couplers • Due to cumulative losses, the number of couplers in the path is limited and, therefore, also the number of ports is limited, perhaps to 32x32 1 2 2x2 2x2 2x2 1 2 3 4 2x2 2x2 2x2 3 4 Waveguide Control Substrate P. Raatikainen Switching Technology / 2003 13 - 47 Microelectromechanical switches (MEMS) • Tiny mirrors micromachined on a substrate • outgrowth of semiconductor processing technologies: deposition, etching, lithography • a highly polished flat plate (mirror) is connected with an electrical actuator • cab be tilted in different directions by applied voltage R.J. Bates, Optical switching and networking handbook, McGraw-Hill, 2001 P. Raatikainen Switching Technology / 2003 13 - 48 24
- 362. Optical cross connects •MEMS technology is still complex and expensive. • Many MEMS devices may be manufactured on the same wafer • reduces cost per system • Many mirrors can be integrated on the same chip • arranged in an array • experimental systems with 16x16=256 mirrors have been built • each mirror may be independently tilted • An all-optical space switch can be constructed using mirror arrays R.J. Bates, Optical switching and networking handbook, McGraw-Hill, 2001 P. Raatikainen Switching Technology / 2003 13 - 49 Optical switches • Components and enabling technologies • Contention resolution • Optical switching schemes P. Raatikainen Switching Technology / 2003 13 - 50 25
- 363. Contention resolution • Contentionoccurs when two or more packets are destined to same output at the same time instant • In electronic switches, contention solved usually by store-and-forward techniques • In optical switches, contention resolved by – optical buffering (optical delay lines) – deflection routing – exploiting wavelength domain • scattered wavelength path (SCWP) • shared wavelength path (SHWP) P. Raatikainen Switching Technology / 2003 13 - 51 Optical delay loop mT 2T ... ... T In_2 Out_2 In_n P. Raatikainen ... Out_1 ... In_1 Switching Technology / 2003 Out_n 13 - 52 26
- 364. Deflection routing Out_2 In_3 Out_3 In_4 Out_4 ... Out_1 In_2 ... In_1 Out_n In_n P. Raatikainen SwitchingTechnology / 2003 13 - 53 Wavelength conversion λ3 λ1 λ2 λ1 In_1 Out_1 Out_2 In_3 Out_3 In_4 Out_4 ... ... In_2 Out_n In_n P. Raatikainen Switching Technology / 2003 13 - 54 27
- 365. Optical switches • Componentsand enabling technologies • Contention resolution • Optical switching schemes P. Raatikainen Switching Technology / 2003 13 - 55 Optical packet switching • User data transmitted in optical packets – packet length fixed or variable • Packets switched in optical domain packet-by-packet • No optical-to-electrical (and reverse) conversions for user data • Switching utilizes TDM and/or WDM • Electronic switch control • Different solutions suggested – broadcast-and-select – wavelength routing – optical burst switching P. Raatikainen Switching Technology / 2003 13 - 56 28
- 366. Optical packet switch Switch control Sync. control •packet delineation • packet alignment • header and payload separation • header information processing • header removal P. Raatikainen Output interfaces ... ... Switch fabric ... ... Input interfaces Header rewrite • switching of packets from inputs to correct outputs in optical domain • contention resolution Switching Technology / 2003 • header insertion • optical signal regeneration 13 - 57 Broadcast-and-select • Input ports support different wavelengths (e.g. only one wavelength/port) • Data packets from all input ports combined and broadcasted to all output ports • Each output port selects dynamically wavelengths, i.e. packets, addressed to it • Inherent support for multi-casting • Requires that control unit has received routing/connection information before packets arrive P. Raatikainen Switching Technology / 2003 13 - 58 29
- 367. Broadcast-and-select TWC/FWC In_n TWC FWC Out_1 ... ... In_2 Wavelength selection 1 COMBINER In_1 Buffering k ... Wavelength encoding Out_n -Tunable Wavelength Converter - Fixed Wavelength Converter P. Raatikainen Switching Technology / 2003 13 - 59 Wavelength routing • Input ports usually support the same set of wavelengths • Incoming wavelengths arrive to “contention resolution and buffering” block, where the wavelengths are – converted to other wavelenths (used inside the switch) – demultiplexed – routed to delay loops of parallel output port logics • Contetion free wavelengths of the parallel output port logics are combined and directed to “wavelength switching” block • Wavelength switching block converts internally routed λ-channels to wavelengths used in output links and routes these wavelengths to correct output ports • Correct operation of the switch requires that control unit has received routing/connection information before packets arrive P. Raatikainen Switching Technology / 2003 13 - 60 30
- 368. Wavelength routing Contention resolutionand buffering 1 TWC Out_1 ... ... k ... .. TWC ... In_1 Wavelength switching 1 TWC Out_n .. In_n TWC k TWC - Tunable Wavelength Converter P. Raatikainen Switching Technology / 2003 13 - 61 Optical burst switching • Data transmitted in bursts of packets • Control packet precedes transmission of a burst and is used to reserve network resources – no acknowledgment, e.g. TAG (Tell-and-Go) – acknowledgment, e.g. TAW (Tell-and-Wait) • High bandwidth utilization (lower avg. processing and synchronization overhead than in pure packet switching) • QoS and multicasting enabled P. Raatikainen Switching Technology / 2003 13 - 62 31
- 369. Header and packetformats • In electronic networks, packet headers transmitted serially with the payload (at the same bit rate) • In optical networks, bandwidth is much larger and electronic header inspection cannot be done at wire speed • Header cannot be transmitted serially with the payload • Different approaches for optical packet format – – – – packets switched with sub-carrier multiplexed headers header and payload transmitted in different λ-channels header transmitted ahead of payload in the same λ-channel tag (λ) switching - a short fixed length label containing routing information P. Raatikainen Switching Technology / 2003 13 - 63 Header and packet formats (cont.) Packets with sub-carrier headers λ1 Payload Fiber Header Sub-carrier λ2 Header and payload in different λ-channels Fiber Header transmitted ahead of payload in the same λ-channel Fiber P. Raatikainen λ1 Payload Header Header Payload Payload Switching Technology / 2003 Header λ2 λ1 λ2 13 - 64 32
- 370. e d tim Gua r load Pay load patt synch . ern Pay e dtim Gua r tag Ro u ting e d tim Gua r He a der s patt ynch. ern Example optical packet format (KEOPS) Time slot P. Raatikainen Switching Technology / 2003 13 - 65 Research issues in optical switching • Switch fabric interconnection architectures • Packet coding techniques (bit serial, bit parallel, out-of-band) • Optical packets structure (fixed vs. variable length) • Packet header processing and insertion techniques • Contention resolution techniques • Optical buffering (delay lines, etc.) • Reduction of protocol layers between IP and fiber • Routing and resource allocation (e.g. GMPLS, RSVP-TE) • Component research (e.g. MEMS) P. Raatikainen Switching Technology / 2003 13 - 66 33