The document discusses network-on-chip (NoC) technology. NoC uses a packet switched network approach to connect intellectual property cores on a chip. It provides advantages over traditional bus-based interconnects like higher bandwidth, energy efficiency, and scalability. NoCs operate using a layered approach with physical, transport, and transaction layers. Common routing algorithms for NoCs include dimension order routing, XY routing, fully adaptive routing, and minimal adaptive routing. NoCs allow for modular and reconfigurable integration of IP cores from different vendors.

1. Network-on-Chip
(NoC) Technology
Department of Electronics Engineering
By
Karthikesan R
17304014
12/9/2020

2. CONTENTS
• Defintion,Significance & Evolution
• Why We Need NOCs?
• Bus vs Networks-on-Chip (NoCs)
• Characteristics
• Network On-chip Interconnection
• NoC layers
• Routing algorithms
• Advantages With NOCs
• Commercial providers
• References
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3. DEFINITION
According to Arteris
Network-on-chip (NoC) interconnect technology
is often called “a front-end solution to a back-end
problem.
Network on Chip (NoC) is a new paradigm to
make the interconnections inside a System on
Chip (SoC) system
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4. SIGNIFICANCE
Source:
International Roadmap for Semiconductors (http://www.itrs.net/)
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5. EVOLUTION OF PARADIGM SHIFT
Computing
module
Network
router
Network
link
 Architectural paradigm shift
 Replace wire by an intelligent network infrastructure
 Design paradigm shift
 Busses and signals replaced by packets
 Organizational paradigm shift
 Create a new discipline, a new infrastructure responsibility
Bus
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6. NoC: A paradigm Shift in VLSI
6
s
s
s
s
s s
s
s
Module
Modul
e
s
Modul
e
From: Dedicated signal wires To: Shared network
Point-
To-point
Link
Network
switch
Computing
Module
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7. Why We Need NOCs?
• Traditionally, ICs have been designed with dedicated point-to-
point connections, with one wire dedicated to each signal.
• For large designs, in particular, this has several limitations
from a physical design viewpoint.
• The wires occupy much of the area of the chip, and in
nanometer CMOS technology, interconnects dominate both
performance and dynamic power dissipation, as signal
propagation in wires across the chip requires multiple clock
cycles. (According to Rent's rule of wiring requirements for
point-to-point connections)
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8. Bus vs Networks-on-Chip (NoCs)
Bus
 Low cost
 Easier to Implement
 Flexible
Networks on Chip
 Layered Approach
 Buses replaced with Networked
architectures
 Higher bandwidth
 Energy efficiency
 Scalable
Irregular architectures Regular ArchitecturesBus-based architectures
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9. CHARACTERISTICS
IP
 In electronic design a semiconductor intellectual property core,
IP core, or IP block is a reusable unit of logic,
cell, or integrated circuit (commonly called a "chip") layout
design that is the intellectual property of one party.
 IP cores may be licensed to another party or can be owned and
used by a single party alone
 Today, the most widely licensed IP cores are from ARM
Holdings (43.2% market share), Synopsys Inc. (13.9% market
share ), Imagination Technologies (9% market share )
and Cadence Design Systems (5.1% market share )
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10. Scalability
10
NoC:
O(n)
O(n)
Point –to-Point
O(n^2 √n)
O(n √n)
Simple Bus
O(n^3 √n)
O(n√n)
Segmented Bus:
O(n^2 √n)
O(n√n)
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11. Parallelism
• The wires in the links of the NoC are shared by
many signals. A high level of parallelism is
achieved, because all links in the NoC can operate
simultaneously on different data packets.
• Therefore, as the complexity of integrated
systems keeps growing, a NoC provides enhanced
performance (such as throughput)
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12. Critical problems addressed by NoC
1) Global interconnect design problem:
delay, power, noise, scalability, reliability
2) System integration
productivity problem
3) Multicore Processors
key to power-efficient
computing
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13. Processing
element
Network
Interface
Router
Input
buffers
Unidirectional
links
Network On-chip Interconnection
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14. NoC layers
IP blocks communicate over the NoC using a
three layered communication referred to as the
1. Transaction
2. Transport and
3. Physical layers
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15. Arteries' NoC layers
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16. Physical Layer
• The Physical layer defines how packets are physically
transmitted over an interface.
• In addition, Arteris has defined a special physical
interface that allows independent hardening of
physical cores, and then connection of those cores
together, regardless of each core clock speed and
physical distance within the cores (within reasonable
limits guaranteeing signal integrity). This enables true
hierarchical physical design practices.
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17. Transport Layer
• The Transport layer defines rules that apply as
packets are routed through the switch fabric.
• The packet format is very flexible and easily
accommodates changes at transaction level without
impacting transport level.
• The Transport Layer may be optimized to application
needs.
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18. Transaction Layer
• The Transaction layer defines the communication
primitives available to interconnected IP blocks.
• Special NoC Interface Units (NIUs), located at
the NoC periphery, provide transaction-layer
services to IP blocks with which they are paired.
• The transaction layer defines how information is
exchanged between NIUs to implement a
particular transaction
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19. NoC Layer mapping summary
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20. 2/9/2020 20

21. ROUTING ALGORITHMS
Oblivious routing algorithms
 It have no information about conditions of the
network, like traffic amounts or congestions.
 A router makes routing decisions on the grounds of
some algorithm or for example randomly.
 The simplest oblivious routing algorithm is a minimal
turn routing. It routes packets using as few turns as
possible.
Example: Dimension Order Routing
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22. Dimension Order Routing
• Dimension order routing (DOR) is a typical
minimal turn algorithm.
• The algorithm determines to what direction
packets are routed during every stage of the
routing
Example: XY routing
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23. XY routing
• XY routing is a dimension order routing which
routes packets first in x- or horizontal direction
to the correct column and then in y- or vertical
direction to the receiver.
• XY routing suits well on a network using mesh
or torus topology. Addresses of the routers are
their xy-coordinates
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24. Adaptive Routing Algorithms
Fully Adaptive Routing
• Fully adaptive routing algorithm uses always a
route which is not congested.
• The algorithm does not care although the route is
not the shortest path between sender and receiver.
• Typically an adaptive routing algorithm sets
alternative congestion free routes to order of
superiority
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25. Minimal Adaptive Routing
• Minimal adaptive routing algorithm always
routes packets along the shortest path.
• The algorithm is effective when more than one
minimal, or as short as possible,
routes between sender and receiver exist.
• The algorithm uses route which is least
congested
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26. Turnaround Routing
• Turnaround routing is a routing algorithm for butterfly and fat-
tree networks.
• Senders and receivers of packets are all on the same side of the
network.
• Packets are first routed from sender to some random
intermediate node on the other side of the network.
• In this node the packets are turned around and then routed to
the destination on the same side of the network, where the
whole routing started.
• The routing from the intermediate node to the definite receiver
is done with the destination-tag routing
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27. ADVANTAGES WITH NOCs
 It is possible to take packet switched networks in the field of
communication theory and computer networks, adapting those concepts to
the particular constraints of on chip interconnection.
 It is possible to achieve a very high grade of flexibility, using
Modularity (extensive use of parameterized independent functional blocks)
Reconfigurability (functional blocks can be mutually connected in different
manners in order to create the particular topology needed for a given
application).
 It is possible to easily integrate IP cores developed by different people or
companies, provided that this modules share a common interface for
communication with the external environment
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28. COMMERCIAL PROVIDERS
• Net Speed Systems
(http://www.netspeedsystems.com/
• Arteris (http://www.arteris.com/)
• Sonics (http://sonicsinc.com/)
• Aims Technology Inc
(http://aimstechnologyinc.com/)
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29. REFERENCES
1) NoCS (http://nocsymposium.org/) website
2) On-Chip Networks Bibliography
(http://www.cl.cam.ac.uk/)
3) “Network on Chip Routing Algorithms “, Ville
Rantala ,Teijo Lehtonen ,Juha Plosila,
University of Turku, Department of Information
Technology Joukahaisenkatu 3-5 B, 20520
Turku, Finland
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30. 302/9/2020