The document provides an overview of Inter-Integrated Circuit (I2C) communication in Cisco Unified Computing System (UCS) chassis. I2C is used to connect low-speed peripheral devices like fans, power supplies, and sensors to the chassis management controller. It describes the various I2C components in the UCS 5108 chassis, including multiplexers that divide the I2C bus into segments. Potential issues from I2C congestion are discussed, such as sensor reading failures and fans running at high speed. Methods for analyzing I2C activity via CLI commands and log files are presented. Suggested workarounds for I2C problems involve removing and reseating components while maintaining redundancy.
The document provides an overview of Das U-Boot, a universal boot loader used to load operating systems and applications into memory on embedded systems. It discusses U-Boot's features such as its command line interface, ability to load images from different sources, and support for various architectures and boards. It also covers compiling and configuring U-Boot, as well as its basic command set and image support capabilities.
The document discusses the SPI protocol used in the LPC2148 microcontroller. It describes the SPI communication modes of master and slave. It explains the various SPI registers used for configuration - SPCCR for clock settings, SPCR for control settings like CPHA and CPOL, SPDR for data transfer, and SPSR for status. It provides steps for initialization and data transfer in both master and slave modes. The document also discusses factors like clock frequency, data length, and interrupt handling related to SPI communication using LPC2148.
The document describes the Serial Peripheral Interface (SPI) protocol which allows for full duplex synchronous serial communication between a master and slave device using 4 pins - MOSI, MISO, SCK, and an optional SS pin. It details the SPI registers for control, status, and data and provides examples of SPI communication with peripherals like digital pots and shift registers. Common issues like conflicts with programming interfaces and ensuring proper chip select signaling are also covered.
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.
This document provides an overview of the I2C protocol. It describes that I2C was designed by Philips in the 1980s to allow communication between components on the same circuit board. It has since been migrated to NXP and expanded to support higher bus speeds and lower voltages. The document outlines the I2C architecture as a half-duplex, synchronous, multi-master bus using a serial data line and serial clock. It defines I2C nodes can function as a master or slave and transmit or receive data. Electrical characteristics, start/stop conditions, packet formats, clock stretching, arbitration and multi-byte transactions are also summarized.
USB 2.0 allows for high-speed data transfer and easy plug-and-play connectivity between devices. It uses a star topology with a single host and up to 127 devices. Data flows bidirectionally through pipes between endpoints on devices and software on the host. The protocol layer handles translation between application data and USB transactions using packets identifying the transfer type and target endpoint.
The document provides an overview of Das U-Boot, a universal boot loader used to load operating systems and applications into memory on embedded systems. It discusses U-Boot's features such as its command line interface, ability to load images from different sources, and support for various architectures and boards. It also covers compiling and configuring U-Boot, as well as its basic command set and image support capabilities.
The document discusses the SPI protocol used in the LPC2148 microcontroller. It describes the SPI communication modes of master and slave. It explains the various SPI registers used for configuration - SPCCR for clock settings, SPCR for control settings like CPHA and CPOL, SPDR for data transfer, and SPSR for status. It provides steps for initialization and data transfer in both master and slave modes. The document also discusses factors like clock frequency, data length, and interrupt handling related to SPI communication using LPC2148.
The document describes the Serial Peripheral Interface (SPI) protocol which allows for full duplex synchronous serial communication between a master and slave device using 4 pins - MOSI, MISO, SCK, and an optional SS pin. It details the SPI registers for control, status, and data and provides examples of SPI communication with peripherals like digital pots and shift registers. Common issues like conflicts with programming interfaces and ensuring proper chip select signaling are also covered.
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.
This document provides an overview of the I2C protocol. It describes that I2C was designed by Philips in the 1980s to allow communication between components on the same circuit board. It has since been migrated to NXP and expanded to support higher bus speeds and lower voltages. The document outlines the I2C architecture as a half-duplex, synchronous, multi-master bus using a serial data line and serial clock. It defines I2C nodes can function as a master or slave and transmit or receive data. Electrical characteristics, start/stop conditions, packet formats, clock stretching, arbitration and multi-byte transactions are also summarized.
USB 2.0 allows for high-speed data transfer and easy plug-and-play connectivity between devices. It uses a star topology with a single host and up to 127 devices. Data flows bidirectionally through pipes between endpoints on devices and software on the host. The protocol layer handles translation between application data and USB transactions using packets identifying the transfer type and target endpoint.
The Advanced Microcontroller Bus Architecture (AMBA) specification defines interfaces for connecting processor and peripherals. It aims to standardize connections to enable modular system design. The Advanced Peripheral Bus (APB) is defined by AMBA for simple peripherals like timers and I/O. It uses few signals for non-pipelined transfers in two cycles to reduce power and complexity.
COVERAGE DRIVEN VERIFICATION OF I2C PROTOCOL USING SYSTEM VERILOGIAEME Publication
The document describes coverage driven verification of an I2C protocol using SystemVerilog. Key aspects include:
1. An I2C master core is used as the design under test (DUT) to read and write data to virtual slaves.
2. A layered testbench is created with components like an interface, generator, driver, monitor and scoreboard.
3. Test cases include reset, write, read and read after write operations to verify the DUT functionality. Constraint random verification and coverage analysis are used to achieve 100% functional coverage.
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I2C-bus which is a 8-bit oriented serial bus. Only two bus lines are required:
a serial data line (SDA)
a serial clock line (SCL).
This document provides an overview of the I2C communication protocol. It describes that I2C is a serial communication protocol used to connect slow devices like EEPROMs and ADCs. It can operate at speeds from 100 kbps to 5 Mbps and supports both single master-multi slave and multi master-multi slave configurations. The document outlines the electrical characteristics, bus features, data frame structure, data transfer process, clock synchronization, arbitration and advantages of the I2C protocol.
LAS16-402: ARM Trusted Firmware – from Enterprise to EmbeddedLinaro
LAS16-402: ARM Trusted Firmware – from Enterprise to Embedded
Speakers:
Date: September 29, 2016
★ Session Description ★
ARM Trusted Firmware has established itself as a key part of the ARMv8-A software stack. Broadening its applicability across all segments, from embedded to enterprise, is challenging. This session discusses the latest developments, including extension into the 32-bit space.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-402
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-402/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
This document discusses challenges in using the Universal Verification Methodology (UVM) at the system-on-chip (SoC) level and proposes solutions. It outlines key features of UVM, then describes challenges like lack of control over UVM verification components from C code and difficulty reusing test cases across different levels. The document proposes a wrapper to connect UVM and SystemC ports and adds a TLM export and register-controlled sequence to allow processor control over sequences. It demonstrates controlling a sequence from a processor through this interface. Finally, it discusses areas like seamless UVM-SystemC connections that could be improved in future UVM versions.
This document provides an overview and examples of configuring Class of Service (CoS) on Juniper Networks devices running the Junos operating system. It describes the key CoS elements like classifiers, policers, schedulers, shapers, and rewrite rules. It also includes an example CoS configuration snippet showing how these elements can be implemented and referenced in the firewall, class-of-service, interfaces, and scheduler-maps sections of the Junos configuration.
The document describes conventions and signals used in the AMBA 3 APB protocol specification version 1.0. It summarizes write and read transfer procedures, including optional wait states using the PREADY signal. Error responses are also described. The operating states of the APB include IDLE, SETUP, and ACCESS states. PREADY controls exiting the ACCESS state.
Intellectual property (IP) in VLSI design refers to reusable logic or functionality units that can be licensed and used as building blocks in chip designs. There are two main types of IP: hard IP, which includes a pre-designed layout, and soft IP, which is delivered as synthesizable code. Soft IP is more vulnerable to theft since it is in a synthesizable form. Memories are often delivered as hard IP since they require careful analog design and peripheral circuitry to be useful. IP differs from custom chip design in that it is created before a specific use, with the goal of reuse across multiple designs. The IP lifecycle involves initial creation through specification, design, testing, and documentation, followed by integration into
The document describes the verification of an SPI master core using UVM. It provides details on the SPI protocol, the master core architecture and features, testbench components like agents and scoreboard, testcases that were run, and two bugs that were discovered. The verification covered functionality like different data transfer configurations and achieved 92.85% coverage of the design.
An Overview Study on I/O Expander with I2C and SMBus InterfacePremier Farnell
This document provides an overview of an I/O expander chip that uses the I2C and SMBus interfaces. It has 8 or 16 programmable GPIO pins that are configurable as inputs or outputs. The chip includes input and output registers, configuration registers to set pin directions, and polarity inversion registers. It is commonly used for applications like keypad control, LED control, sensor monitoring, and fan control. Block diagrams and typical application circuits are shown to illustrate its features and interface.
A reusable verification environment for NoC platforms using UVMSameh El-Ashry
This document proposes reusable UVM verification environments for network-on-chip (NoC) platforms. It describes motivations for using NoCs instead of buses for multicore system interconnects. The document then outlines the benefits of the UVM methodology for verifying complex designs. It proposes separate UVM environments for verifying a single router using either a predictor or reference model, and an environment for verifying an entire NoC by reusing the single router environment. Simulation results are presented to evaluate average latency and throughput metrics. The goal is to develop reusable UVM environments that can be easily adapted for different NoC configurations and router architectures.
The document discusses the I2C protocol, which uses just two bidirectional serial data lines (SDA and SCL) to allow multiple devices to communicate on the same bus. It supports synchronous communication at various speeds up to 5 Mbps. Devices are addressed using 7- or 10-bit addresses. Data is transferred in bytes, with start and stop conditions defining the beginning and end of each transmission. All data transitions must occur when the clock signal SCL is low.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
Join this video course on udemy . Click here :
https://www.udemy.com/microcontroller-programming-stm32-timers-pwm-can-bus-protocol/?couponCode=SLIDESHARE
learn STM32 TIMERS, CAN,RTC, PWM,LOW POWER embedded systems and program them using STM32 Device HAL APIs STEP by STEP
>>Welcome to the course which teaches you advanced Micro-controller programming. In this course you are going to learn and master TIMERS, PWM, CAN, RTC, LOW POWER MODES of STM32F4x Micro-controller with step by step guidance. Highly recommended if you are seeking a career in the domain of Embedded software. <<
In this course, you will understand behind the scene working of peripherals with supportive code exercises. I have included various real-time exercises which help you to master every peripheral covered in this course and this course thoroughly covers both theory and practical aspects of TIMERS, PWM, CAN, RTC, LOW POWER MODES of STM32F4x Micro-controller.
This document provides details about the MSP430x5xx microcontroller including its block diagram, CPU architecture, memory map, I/O ports, interrupts, clock system, low power modes, watchdog timer and more. Key aspects include its 16-bit RISC CPU, various clock signals, flash memory up to 512KB, RAM up to 66KB, 8 I/O ports, analog to digital converter, timers, real-time clock, and low power modes down to 0.1uA. Example code is provided to configure ports for output and LED interfacing.
This document provides information about microprocessors, microcontrollers, and the Intel 8085 and 8051 chips. It discusses how a microprocessor incorporates a computer's central processing unit on a single integrated circuit, and how microcontrollers are designed for embedded applications. Key aspects of microcontrollers covered include on-chip RAM, timers, serial ports, interrupt controllers, analog-to-digital converters, and pulse width modulation controllers. An example block diagram and features are given for the Intel 8051 microcontroller. Example Arduino/Freeduino programs are also summarized.
The Advanced Microcontroller Bus Architecture (AMBA) specification defines interfaces for connecting processor and peripherals. It aims to standardize connections to enable modular system design. The Advanced Peripheral Bus (APB) is defined by AMBA for simple peripherals like timers and I/O. It uses few signals for non-pipelined transfers in two cycles to reduce power and complexity.
COVERAGE DRIVEN VERIFICATION OF I2C PROTOCOL USING SYSTEM VERILOGIAEME Publication
The document describes coverage driven verification of an I2C protocol using SystemVerilog. Key aspects include:
1. An I2C master core is used as the design under test (DUT) to read and write data to virtual slaves.
2. A layered testbench is created with components like an interface, generator, driver, monitor and scoreboard.
3. Test cases include reset, write, read and read after write operations to verify the DUT functionality. Constraint random verification and coverage analysis are used to achieve 100% functional coverage.
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I2C-bus which is a 8-bit oriented serial bus. Only two bus lines are required:
a serial data line (SDA)
a serial clock line (SCL).
This document provides an overview of the I2C communication protocol. It describes that I2C is a serial communication protocol used to connect slow devices like EEPROMs and ADCs. It can operate at speeds from 100 kbps to 5 Mbps and supports both single master-multi slave and multi master-multi slave configurations. The document outlines the electrical characteristics, bus features, data frame structure, data transfer process, clock synchronization, arbitration and advantages of the I2C protocol.
LAS16-402: ARM Trusted Firmware – from Enterprise to EmbeddedLinaro
LAS16-402: ARM Trusted Firmware – from Enterprise to Embedded
Speakers:
Date: September 29, 2016
★ Session Description ★
ARM Trusted Firmware has established itself as a key part of the ARMv8-A software stack. Broadening its applicability across all segments, from embedded to enterprise, is challenging. This session discusses the latest developments, including extension into the 32-bit space.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-402
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-402/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
This document discusses challenges in using the Universal Verification Methodology (UVM) at the system-on-chip (SoC) level and proposes solutions. It outlines key features of UVM, then describes challenges like lack of control over UVM verification components from C code and difficulty reusing test cases across different levels. The document proposes a wrapper to connect UVM and SystemC ports and adds a TLM export and register-controlled sequence to allow processor control over sequences. It demonstrates controlling a sequence from a processor through this interface. Finally, it discusses areas like seamless UVM-SystemC connections that could be improved in future UVM versions.
This document provides an overview and examples of configuring Class of Service (CoS) on Juniper Networks devices running the Junos operating system. It describes the key CoS elements like classifiers, policers, schedulers, shapers, and rewrite rules. It also includes an example CoS configuration snippet showing how these elements can be implemented and referenced in the firewall, class-of-service, interfaces, and scheduler-maps sections of the Junos configuration.
The document describes conventions and signals used in the AMBA 3 APB protocol specification version 1.0. It summarizes write and read transfer procedures, including optional wait states using the PREADY signal. Error responses are also described. The operating states of the APB include IDLE, SETUP, and ACCESS states. PREADY controls exiting the ACCESS state.
Intellectual property (IP) in VLSI design refers to reusable logic or functionality units that can be licensed and used as building blocks in chip designs. There are two main types of IP: hard IP, which includes a pre-designed layout, and soft IP, which is delivered as synthesizable code. Soft IP is more vulnerable to theft since it is in a synthesizable form. Memories are often delivered as hard IP since they require careful analog design and peripheral circuitry to be useful. IP differs from custom chip design in that it is created before a specific use, with the goal of reuse across multiple designs. The IP lifecycle involves initial creation through specification, design, testing, and documentation, followed by integration into
The document describes the verification of an SPI master core using UVM. It provides details on the SPI protocol, the master core architecture and features, testbench components like agents and scoreboard, testcases that were run, and two bugs that were discovered. The verification covered functionality like different data transfer configurations and achieved 92.85% coverage of the design.
An Overview Study on I/O Expander with I2C and SMBus InterfacePremier Farnell
This document provides an overview of an I/O expander chip that uses the I2C and SMBus interfaces. It has 8 or 16 programmable GPIO pins that are configurable as inputs or outputs. The chip includes input and output registers, configuration registers to set pin directions, and polarity inversion registers. It is commonly used for applications like keypad control, LED control, sensor monitoring, and fan control. Block diagrams and typical application circuits are shown to illustrate its features and interface.
A reusable verification environment for NoC platforms using UVMSameh El-Ashry
This document proposes reusable UVM verification environments for network-on-chip (NoC) platforms. It describes motivations for using NoCs instead of buses for multicore system interconnects. The document then outlines the benefits of the UVM methodology for verifying complex designs. It proposes separate UVM environments for verifying a single router using either a predictor or reference model, and an environment for verifying an entire NoC by reusing the single router environment. Simulation results are presented to evaluate average latency and throughput metrics. The goal is to develop reusable UVM environments that can be easily adapted for different NoC configurations and router architectures.
The document discusses the I2C protocol, which uses just two bidirectional serial data lines (SDA and SCL) to allow multiple devices to communicate on the same bus. It supports synchronous communication at various speeds up to 5 Mbps. Devices are addressed using 7- or 10-bit addresses. Data is transferred in bytes, with start and stop conditions defining the beginning and end of each transmission. All data transitions must occur when the clock signal SCL is low.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
Join this video course on udemy . Click here :
https://www.udemy.com/microcontroller-programming-stm32-timers-pwm-can-bus-protocol/?couponCode=SLIDESHARE
learn STM32 TIMERS, CAN,RTC, PWM,LOW POWER embedded systems and program them using STM32 Device HAL APIs STEP by STEP
>>Welcome to the course which teaches you advanced Micro-controller programming. In this course you are going to learn and master TIMERS, PWM, CAN, RTC, LOW POWER MODES of STM32F4x Micro-controller with step by step guidance. Highly recommended if you are seeking a career in the domain of Embedded software. <<
In this course, you will understand behind the scene working of peripherals with supportive code exercises. I have included various real-time exercises which help you to master every peripheral covered in this course and this course thoroughly covers both theory and practical aspects of TIMERS, PWM, CAN, RTC, LOW POWER MODES of STM32F4x Micro-controller.
This document provides details about the MSP430x5xx microcontroller including its block diagram, CPU architecture, memory map, I/O ports, interrupts, clock system, low power modes, watchdog timer and more. Key aspects include its 16-bit RISC CPU, various clock signals, flash memory up to 512KB, RAM up to 66KB, 8 I/O ports, analog to digital converter, timers, real-time clock, and low power modes down to 0.1uA. Example code is provided to configure ports for output and LED interfacing.
This document provides information about microprocessors, microcontrollers, and the Intel 8085 and 8051 chips. It discusses how a microprocessor incorporates a computer's central processing unit on a single integrated circuit, and how microcontrollers are designed for embedded applications. Key aspects of microcontrollers covered include on-chip RAM, timers, serial ports, interrupt controllers, analog-to-digital converters, and pulse width modulation controllers. An example block diagram and features are given for the Intel 8051 microcontroller. Example Arduino/Freeduino programs are also summarized.
The document discusses the hardware control capabilities and selection criteria of Siemens S7-1200 and S7-1500 programmable logic controllers (PLCs). The S7-1200 has a maximum of 256 digital inputs/outputs while the S7-1500 can support up to 960. Both PLCs support analog and communication modules. Key factors for PLC selection include the application requirements, required input/output capacity, memory needs, and communication requirements. The document also compares the two PLC models.
The document describes the features of an AVR 8-bit microcontroller, including its RISC architecture, memory capabilities, I/O ports, timers, USB and peripheral features. It has 8/16/32KB of flash memory, 512/512/1024 bytes of EEPROM and SRAM, and 22 programmable I/O lines. It includes analog and digital features such as timers, USART, SPI and a USB controller.
INDUSTRIAL TRAINING REPORT EMBEDDED SYSTEM.pptxMeghdeepSingh
This document provides an overview of embedded systems and microcontrollers. It defines a microcontroller as a single-chip computer containing memory, input/output circuitry, and other components to function without additional support. The document describes the features and components of a typical microcontroller, including registers, instruction sets, addressing modes, and peripherals. It compares microcontrollers to microprocessors and provides examples of using LEDs and 7-segment displays with microcontrollers.
The user manual provides step-by-step instructions for installing and configuring the AKCP Door Control Unit (DCU) and its access control components. It describes the DCU hardware, how to wire the DCU to card readers, fingerprint readers, exit buttons, and door locks. It also provides diagrams of typical installations and specifications for cable runs. The manual is intended to guide users through setup and common configurations.
This document contains a two mark question bank for the subject EE 6602 - Embedded Systems. It includes 15 questions related to introduction to embedded systems, embedded networking, and embedded firmware development environment. The questions cover topics such as defining embedded systems, challenges in designing embedded systems, ROM image, RAM role, watchdog timer, target system, real time clock, system clock, embedded system components, classifications, examples, DMA, device drivers, communication protocols and standards, and embedded product development life cycle phases.
The document provides an introduction to the 8085 microprocessor. It discusses the basic components of a microcomputer including the CPU, memory (RAM and ROM), and I/O unit. It then describes the internal structure of the 8085 CPU including its registers, flag bits, program counter, and stack pointer. The document outlines the 8085 bus structure including its address bus, data bus, and control signals. It provides timing diagrams for opcode fetch, memory read, and memory write operations. Finally, it discusses addressing modes, instruction size, and includes a table of the 8085 instruction set.
The document discusses Inter-Integrated Circuit (I2C), a serial communication protocol used to connect integrated circuits. It describes I2C's history, structure, communication process, addressing scheme, and provides a sample code for reading analog to digital converter values from a chip via I2C.
The document discusses the history and use of programmable logic controllers (PLCs) in industrial automation. It notes that PLCs were first specified in 1968 by General Motors to provide a solid-state, reusable system for controlling industrial processes more flexibly than relay-based systems. A PLC consists of a central processing unit, power supply, programming unit, memory, and input/output interfacing circuitry. It scans inputs, executes user-programmed logic instructions, and updates outputs on a continuous cycle. Common programming methods for PLCs include ladder logic, functional block diagrams, and structured text. PLCs communicate with field devices and one another using various interfaces and protocols.
PIC Introduction and explained in detailedAnkita Tiwari
The document provides an introduction to the PIC microcontroller. It discusses what a microcontroller is, compares microcontrollers to general purpose microprocessors, and briefly outlines the history of the PIC microcontroller. It then describes features of the PIC16F84 microcontroller including its clock generator, reset function, ports, central processing unit, and memory organization including flash memory, RAM, and ROM. It also covers the timer and prescalar functions.
The document describes a distributed control system (DCS) used to control manufacturing processes. It discusses the key components of a DCS including CPUs, input/output modules, communication systems, and human interface systems. The DCS allows for distributed controllers throughout a system connected by networks for monitoring and control. Specific DCS applications are controlling electrical grids, chemical plants, oil refineries, and other continuous industrial processes.
The document describes a distributed control system (DCS) used to control manufacturing processes. A DCS uses distributed controllers connected by a network for communication and monitoring. It typically uses custom processors as controllers and proprietary protocols for communication. Key components include input/output modules, a central processor, communication cards and a human interface system for monitoring and operation. DCS systems are applied to control continuous or batch processes in various industries like power generation, environmental systems and traffic control.
This document outlines the syllabus for a course on Internet of Things (IoT) technology taught by Dr. Syed Mustafa at HKBK College of Engineering, Bengaluru. It covers key modules including IoT physical devices and endpoints such as Arduino and Raspberry Pi. The Arduino section describes the Arduino microcontroller board and its components. It also covers Arduino programming basics like setup and loop functions, input/output functions, variables, conditional statements, and serial communication. The Raspberry Pi section provides an overview of the single-board computer and its hardware layout.
This document outlines the objectives and units of study for a course on microprocessors and microcontrollers. The aim is to learn the architecture, programming, and interfacing of microprocessors and microcontrollers. Key topics covered include the 8085 and 8086 microprocessors as well as the 8051 microcontroller. Specific units will cover the architecture and programming of these chips, interfacing with peripheral devices, timers, serial communication, and application programming. The textbook references provided relate to the 8085, 8086, and 8051.
Cisco 3900 and cisco 2900 series routers3Anetwork com
The document provides details on Cisco 2900 and 3900 series routers, including specifications of various router models. These routers provide data functionality through Ethernet ports and security with VPN acceleration. They also provide voice capabilities with DSP and support add-on modules for additional functions. The routers have slots that support EHWICs, ISMs, PVDM3s, SMs and SPEs to enable different features. They connect internal and external modules through a high-speed fabric for improved switching.
A programmable logic controller (PLC) uses a programmable memory to store instructions for controlling machines and processes. It monitors inputs, executes logic functions, and controls outputs to automate industrial processes. The PLC consists of a central processing unit, input/output modules, power supply, and programming devices. It provides flexibility to change control programs easily compared to rewiring relay panels.
AN INTEGRATED FOUR-PORT DC-DC CONVERTER-CEI0080Vivek Venugopal
This document proposes a novel four-port DC/DC converter topology for renewable energy applications. The proposed topology adds two switches and two diodes to a traditional half-bridge topology to interface two power sources, one bidirectional storage port, and one isolated load port. Zero-voltage switching is achieved for all four main switches. Three ports can be tightly regulated through independent duty cycles while the fourth is unregulated to maintain power balance. Experimental results confirm independent control over three processing paths with low component count and losses.
GraphSummit Singapore | The Art of the Possible with Graph - Q2 2024Neo4j
Neha Bajwa, Vice President of Product Marketing, Neo4j
Join us as we explore breakthrough innovations enabled by interconnected data and AI. Discover firsthand how organizations use relationships in data to uncover contextual insights and solve our most pressing challenges – from optimizing supply chains, detecting fraud, and improving customer experiences to accelerating drug discoveries.
Communications Mining Series - Zero to Hero - Session 1DianaGray10
This session provides introduction to UiPath Communication Mining, importance and platform overview. You will acquire a good understand of the phases in Communication Mining as we go over the platform with you. Topics covered:
• Communication Mining Overview
• Why is it important?
• How can it help today’s business and the benefits
• Phases in Communication Mining
• Demo on Platform overview
• Q/A
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
Introducing Milvus Lite: Easy-to-Install, Easy-to-Use vector database for you...Zilliz
Join us to introduce Milvus Lite, a vector database that can run on notebooks and laptops, share the same API with Milvus, and integrate with every popular GenAI framework. This webinar is perfect for developers seeking easy-to-use, well-integrated vector databases for their GenAI apps.
Let's Integrate MuleSoft RPA, COMPOSER, APM with AWS IDP along with Slackshyamraj55
Discover the seamless integration of RPA (Robotic Process Automation), COMPOSER, and APM with AWS IDP enhanced with Slack notifications. Explore how these technologies converge to streamline workflows, optimize performance, and ensure secure access, all while leveraging the power of AWS IDP and real-time communication via Slack notifications.
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
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Essentials of Automations: The Art of Triggers and Actions in FME
My i2c
1. Presented by : Avinash Singhal
Customer Support Engineer
Cisco Unified Computing System(UCS)
‘
Inter- Integrated Circuit
on CISCO UCS
2. Table of Contents
What it is ? , What it does ??
Various components and how they work??
I2C architecture (and components linked )within UCS 5108
chassis??
Various issues that may arise due to I2C congestion??
Show Tech Analysis and Collecting information via UCS CLI ??
I2C use case scenarios and suggested workarounds w.r.t UCS ??
Reference Links
Question????????????????????????
3. What it is ? , What it does ??
I2C provides support for communication with various slow, on-board
peripheral devices that are accessed intermittently.
Most available I2C devices operate at speeds up to 400Kbps, with
some venturing up into the low megahertz range.
I2C is easy to use to link multiple devices together since it has a
built-in addressing scheme(7 bit and 10 bit addressing scheme).
It is widely used in varieties of embedded systems to connect low
speed peripherals listed here :external SEEPROMs, digital sensors,
remote I/O ports, GPIO expanders, RAM, etc) to the main controller
4. Various components and how they work??
I2C BUS has two shared bidirectional lines:
SDA – Serial Data Line is used to transfer data between the devices in the BUS.
SCL – Serial Clock Line is used to send the clock.
The device that initiates a transaction on the I2C bus is termed the master.
The master normally controls the clock signal.
A device being addressed by the master is called a slave.
5. I²C in the UCS Chassis
The UCS uses the PCA9541 IC and the PCA9518 (Hub / Mux) located in the IOM as an I2c MUX.
The PCA9541 chip is included in each fan, each PSU, and the UCS 5108 chassis mid plane (up to
13 chips per fully loaded UCS 5108 chassis). The chip is the i2c-bus master/slave selector
designed for high reliability dual master i2c bus applications.
The UCS has 13 different i2c multiplexers (pca9541) in it:
6 - one on each fan
4 - one on each PSU
2 - one on each IOM
1 - one on the chassis mid plane
It is used by the Chassis Management Controller (CMC) to monitor components and to control the
master/slave selection on the bus.
The IOM CPU needs to initialize its I2C interfaces as masters prior to using the I2C bus. If acting
as a slave, the CPU’s slave address is programmable, but defaulted to 0x00. Due to the relatively
large number of devices the I2C devices are divided into several branches behind I2C Mux devices.
The 9541 device on the mid plane is used as the lock to determine which IOM has exclusive
access to the fans and power supplies in addition to configuring which IOM can access the chassis
seeprom and chassis FRU also located on the mid plane.
There are two I2C buses in the UCS 5108 chassis.
Each of these buses has multiple segments.
Bus has 5 segments.
- 0-IOM, - 1 chassis- 2 blade- 3 fan- 4 psu
6. I2C architecture and components
within UCS 5108 chassis??
I2C resides/lives on the UCS chassis Mid-plane.
7. “IOM reboot” can cause a lockup condition between CMC and IOM switch
component resulting in IOM outage.
“Multiple false positive events” invalidating UCS health monitoring practice..
FAN spinning at full speed. Fan noise and higher than normal power
consumption.
Generally problems with “reading sensor data” that in turn can cause fans to
spin in safe mode (i.e. run at 100%) and general access problems and faults.
Error code from failed I2C misinterpreted as a blade removal event
Noisy PSU I2C bus misinterpreted as a blade removal event (flapping).
A failed PCA9541 disconnect command sequence can leave multiple PSU I2C
buses connected which can lead to an “out-of-spec electrical condition” on the
I2C bus. This can lead to additional failures.
It is essential to realize these PCA9541 errors can often be cleared by resetting
one or multiple components that have the 9541 chip.
Various issues that may arise due to I2C
congestion??
8. Fan & PSU I2C Issues
If the fans lock up intermittently, becomes unreadable, or spin to
high but safe speed (safe mode), one or more of the fans might
have a bad 9541 chip.
This type of problem includes failure to control fan speed and
failure to read fan sensor data like temperature, rotation speed
and FRU data. When this happens, log file data usually indicates
connection problems between the IOM and fan segment.
The file techsupport_detailed_iocard1/fsl-i2c.2/counters.out &
fsl-i2c.1/counters.out may show PSU and fan related 9541 errors
Ex: error_pca9541_per_device:
c.ms 6
p.psu0.fru 11538
p.psu0.psmi 13053
p.fan1.fru 11534
9. Fan & PSU I2C Issues
The file psreading.out from the Chassis techsupport file can also be used.
If the file shows N/A for all readings on both IOMs, then this indicates a 9541
problem.
Total Input Power consumption: -
1 Total Output Power consumption: -1
Power supply: 0 Voltage (210V) : N/A Voltage (12V) : N/A Voltage (3V) : N/A Current (210V) : N/ Current (12V) : N/A
Current (3V) : N/A
Here is an example of the PSU segment with errors from the techsupport_detailed_iocard1/fsl-i2c.2/counters.out .
As with all the counters you have to check if they are increasing.
segment 4 psu
norxack 1
pca9541postio2 2
wait_gt_deadline 53
segment 4 psu
norxack 189
pca9541clrerrprs 156
pca9541seterr 22
pca9541postio2 2438
wait_gt_deadline 606
Note: wait_gt_deadline -
10. Other components that interface the I2C bus, like the SEEPROM, GPIO, Gilroy(mid plane).
There are two Chassis SEEPROMs.
The first SEEPROM is used to store FRU information and is read-only.
The second chassis SEEPROM is read-write and stores chassis UCSM supplied data and uBoot
diagnostic data.
UCS-A# connect local-mgmt a
(local-mgmt)# show cluster st
Cluster Id: 0xd3e9601eeeb711df-0xa232000573af4ac4
A: UP, PRIMARY
B: UP, SUBORDINATE
HA READY
Detailed state of the device selected for HA storage:
Chassis, serial: FOX1442GL18, state: active with errors
Fabric A, chassis-seeprom local IO failure:
FOX1442GL18 READ_FAILED, error: TIMEOUT, error code: 10, error count: 211
Warning: there are pending SEEPROM errors on one or more devices, failover may not complete
Or Description: Chassis FOX1422GJ59, error accessing SEEPROM
IOM-1 midplane 9541 errors:c.seeprom={SUCCESS=36494,ETIMEDOUT=9}
mac:log user$ grep -i "Chassis grab failed" obfl-cmc.log |wc 64 576 8541
SEEPROM IO error is usually due to chassis PCA9541 problem. This can be a transient
problem where two IOMs are contending for access. High error counts per hour may
indicate a faulty PCA9541
11. General Purpose Input/Output (GPIO)
GPIO is a generic pin on a chip whose behavior can be controlled by the user at run time.
GPIO expanders provide expansion for most microprocessor families allowing designers to
save the GPIOs on microprocessors for other important functions.
As more features and processing requirements, such as LED control, hardware control
monitors, and humidity sensors in the computing space are added to applications, the
limited numbers of GPIOs on microprocessors are becoming more valuable.
By implementing our I/O expanders, designers can utilize the microprocessor.
They are also ideal for monitoring system functions and accepting push-button inputs
There are 11 kinds of low-level I2C errors:
norxack, timeout, interrupted, unfinished,lostarbitration, nonmasterrestart, fixup, nores,
expirywait, pca9541clrerr, pca9541seterr
EX:::
i2.log excerpt:
c.gpio3={ENXIO=8}
i2c.log:c.gpio0={ENXIO=8}
i2c.log:c.gpio1={ENXIO=8}
i2c.log:c.gpio2={ENXIO=8}
i2c.log:c.gpio3={ENXIO=8}
'ENXIO', "No such device or address
12. I²C and SMBus Fault Codes
EBUSY --- Returned by SMBus adapters when the bus was busy for longer than allowed
EINVAL ---This rather vague error means an invalid parameter has been detected before any I/O
operation was started
ENODEV --- Returned by driver probe methods. This is a bit more specific than ENXIO, implying
the problem isn't with the address, but with the device found there
ENXIO --- Returned by I2C adapters to indicate that the address phase of a transfer didn't get
an ACK. While it might just mean an I2C device was temporarily not responding
ETIMEDOUT --- This is returned by drivers when an operation took too much time, and was
aborted before it completed.
EPROTO --- Returned when slave does not conform to the relevant I2C or SMBus (or chip-specific)
protocol specifications.
EOPNOTSUPP --- Returned by an adapter when asked to perform an operation that it doesn't, or
can't, support
my %errmap = (
-1 => ['EPERM', "Operation not permitted"],
-4 => ['EINTR', "Interrupted system call"],
-5 => ['EIO', "I/O error"],
-6 => ['ENXIO', "No such device or address"],
-11 => ['EAGAIN', "Try again"],
-12 => ['ENOMEM', "Out of memory"],
-16 => ['EBUSY', "Device or resource busy"], ("fan present but data not ready, returning -EBUSY");
-19 => ['ENODEV', "No such device"],
-22 => ['EINVAL', "Invalid argument"],
-110 => ['ETIMEDOUT', "Connection timed out"],
-512 => ['ERESTARTSYS', ""]
13. Show Tech Analysis and Collecting information via UCS CLI ??
Tech Support Files ::
IOCardcmclogobfl-cmc.log
IOCardcmclogi2c.log
IOM/cmc/log/thermal.log
IOCardx log you can find the following files : psreadings.out , thresholds.out , fancontrol.out,
cmclogplatform_ohms ,cmclogdmserver ,IOCardcmclogpwrmgrcli.log
fex-1# show platform software cmcctrl thermal status – Shows us the same output as
“thermal.log”
fex-1# show platform software cmcctrl ohms all – Same output as “ohms.log” with some
additional syslogs added
fex-1# show platform software cmcctrl obfl logs – Same output as “obfl-cmc.log”
fex-1# show platform software cmcctrl pstate – Shows us if there are any processes crashing
on the IOM
fex-1# show platform software cmcctrl cmc manager - current state of the IOM cluster
show platform software cmcctrl dmclient iom/chassisfru: this is just to get the live
information about the fru and sn
show platform software cmcctrl showi2c: This is the showi2c command (and i2c.log file)
PSU: show platform software cmcctrl power status
show platform software cmcctrl power redundancy : this will give you same output as
pwrmgrcli –r
show platform software cmcctrl dmclient psreadings
show platform software cmcctrl dmclient threshold : to check if there is anything crossing
threshold but not only for psu
14. I2C use case scenarios and suggested workarounds
w.r.t UCS
Implementing Workarounds for I2C Bus Issues
Make sure all servers have redundant paths for network and storage.
Fan Segment Issues
Remove the fan(s) showing errors and wait at least 30 seconds before reinserting.
If issue does not resolve, remove the fan and move it to the next fan over and see if the
alert follows the fan or the slot.
Power supply issues
Remove the power supplies one at time waiting 2 minutes before reinserting. Never
remove more than one power supply at a time.
IOM Issues
Reseat the IOM on one side at time, waiting at least 5 minutes prior to reinserting the
IOM. Never remove both IOM’s at the same time
Note : No maintenance window required as long as we have HA (fabric failover ,NIC
teaming /bonding ,multi-pathing in place)