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Sameh El-Ashry

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How to create SystemVerilog verification environment?
Chipions session 2021 - VLSI career
Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage
On Error Injection for NoC Platforms: A UVM-based Practical Case Study
A reusable verification environment for NoC platforms using UVM
verification_planning_systemverilog_uvm_2020
On the verification of configurable nocs in simulation and hardware emulation a uvm based tool
Functional verification techniques EW16 session
Code Management Workshop