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Timing notes 2006

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Timing notes 2006

  1. 1. 1 Timing and Clocking Issues ECE152B Prepared by Roopa Chari Based on the slides from Professor Tim Cheng Timing Parameters for Combinational Logic Physically implemented combinational circuits (NAND or NOR gates for example) exhibit certain timing characteristics. A “0” or “1” applied at the input to a combinational circuit does not result in an instantaneous change at the output because of various electrical constraints. Input-to- output delay in combinational circuits can be expressed with two parameters, propagation delay, tpd, and contamination delay, tcd. Propagation delay (tpd): The amount of time needed for a change in a logic input to result in a permanent change at an output, that is, the combinational logic will not show any further output changes in response to an input change after time tpd units. Contamination delay (tcd): The amount of time needed for a change in a logic input to result in an initial change at an output, that is, the combinational logic is guaranteed not to show any output change in response to an input change before tcd time units have passed. Combinational propagation delays are additive and so the propagation delay of a larger combinational circuit can be determined by adding the propagation delays of each of the circuit components along the longest path. In contrast, finding the contamination delay of the circuit requires identifying the shortest path of contamination delays from input to output and adding the delay values along this path. Timing Parameters for Sequential Logic When sequential circuits are physically implemented they exhibit certain timing characteristics that unlike combinational circuits, are specified in relation to the clock input.
  2. 2. 2 Latch vs. Flip-Flop A latch is level-sensitive while a flip-flop is edge triggered. A latch stores when the clock level is low and is transparent when the level is high. A flip-flop stores when the clock rises and is mostly never transparent. Since flip-flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive edge-triggered) or falling (for negative-edge triggered) clock edge. The following parameters specify sequential circuit behavior. Note that these are all for positive edge-triggered flip-flops unless otherwise specified, but are easily applied to negative edge triggered flip-flops as well. Propagation delay (tclk−q): The amount of time needed for a change in the flip-flop clock input D to result in a change at the flip-flop output Q. When the clock edge arrives, the D input value is transferred to output Q. After time tclk−q the output is guaranteed not to change value again until another clock edge trigger arrives. Contamination delay (tcd): This value indicates the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output Q. The output of the flip-flop maintains its initial value until time tcd has passed and is guaranteed not to show any output change in response to an input change until after tcd has passed. Note: delays can be different for both rising and falling transitions. Setup time (tsu): The amount of time before the clock edge that data input D must be stable the rising clock edge arrives. Hold time (thold): This indicates the amount of time after the clock edge arrives that data input D must be held stable in order for the flip-flop to latch the correct value. Hold time is always measured from the rising clock edge (for positive edge-triggered) to a point after the clock edge.
  3. 3. 3 Setup and hold times are restrictions that a flip-flop places on combinational or sequential circuitry that drives a flip-flop D input. The circuit has to be designed so the D input signal arrives at least tsu time units before the clock edge and does not change until at least thold time units after the clock edge. If either of these restrictions is violated for any of the flip-flops in the circuit, the circuit will not operate correctly. These restrictions limit the maximum clock frequency at which the circuit can operate. Determining the Maximum Clock Frequency for a Sequential Circuit Most digital circuits contain both combinational components (gates, muxes, adders, etc.) and sequential components (flip-flops). These components can be combined to form sequential circuits that perform computation and store results. By using combinational and sequential component parameters, it is possible to determine the maximum clock frequency at which a circuit will operate and generate correct results. This analysis can best be examined through use of an example. Example 1: For the circuit shown below, assume the delay through the register (tclk-q) is 0.6ns and the delay through each logic block is indicated inside the box. Assume that the positive edge-triggered registers have a set-up time tsu of 0.4ns. What is the minimum clock period? The first step is model the given circuit so that the datapath between flip-flops are characterized by the longest and shortest combinational delays between the flip-flops. direction of clock
  4. 4. 4 Let Tclk be the clock period. Then, Tclk ≥ tclk-q (register) + tpd logic (longest) + tsu (destination register) Tclk ≥ 0.6 ns + 8 ns + 0.4 ns Tclk ≥ 9 ns Delay Modeling Gate propagation delay (tPHL and tPLH): Gate propagation delay is measured from 50% input to 50% of the output. tPHL is measured from 50% of the rising edge of the input voltage to 50% of the rising edge of the output voltage. Similarly, tPLH is measured from 50% of the falling edge of the input voltage to 50% of the falling edge of the output voltage. Interconnect Delay: This is delay caused by wires. Interconnect introduces three types of parasitic effects – capacitive, resistive, and inductive – all of which influence signal integrity and degrade the performance of the circuit. After the signal frequencies of our interests (up to several GHz), we can ignore the effects of inductance of interconnect. When gate G1 drives gate G2, we can model the circuit as the one showing below in the right-hand side figure where Rout is the output resistance of G1, Rin and Cin are the interconnect resistance and capacitance, and CL is the input capacitance of G2. This model can be further simplified as the one shown in the right. Now if Vin (i.e. output of G1) switches from 0V to VDD, the waveform at Vout (i.e. input of G2) can be expressed as: Vout = VDD (1- e-t/RC ) Vin Vout (output of G1) (input of G2)R= Rout+Rint C=Cin+CL
  5. 5. 5 Definition: Rise time (Fall time) - The time it takes for a waveform to rise from 10% to 90% (90% to 10%) of its steady state value – as illustrated below. The time for the waveform Vout = VDD (1- e-t/RC ) to rise from 0.1VDD from 0.9VDD can be easily calculated: Note that the rise time is linearly proportional to the product of (Rout+Rin) and (Cin+CL). So, if the interconnect is long, Rin and Cin will be large, and, in turn, the rise time will be long. Similarly, if a gate drives a large number of gates, the rise time will be long too as CL, which is proportional to the number of driven gates, is large. Clock Trees If the number of flip-flops driven by the clock line is large, the clock rise time (also called slew rate) will be unacceptably long. The solution to this problem is to use a clock power up tree which means adding buffers into the clock tree. When designing a clock distribution network, the absolute delay from a central clock source to the clock elements is irrelevant, only the relative phase between two clock elements is important. When designing clock trees in this way, first determine the number of levels your clock tree can have. This will depend on the total number of flip-flops in the circuit and the number of fan outs (to flip-flops or buffers) that you are limited to. See the examples in the lecture slides. VOL VOH Rise time VOL VOH Fall time 90% 10% 90% 10% Rise Time ~= 2.2 * R * C
  6. 6. 6 Clock Skew and Clock Jitter Clock Skew (δ): The spatial variation in arrival time of a clock transition is known as clock skew. The clock skew between two points j and k is given by tj – tk, where tj – tk are the rising edge of the clock with respect to the reference. Clock skew is constant from cycle to cycle and does not cause clock period variation, but only phase shift. Clock skew might cause the race problem – illustrated in the lecture slides. Clock Jitter: Clock jitter refers to the temporal variation of the clock period, that is, the clock period can expand or reduce on a cycle-by-cycle basis. Variation of the pulse width is important for level sensitive clocking. Positive and Negative Clock Skew Positive Skew: Clock and data flow in the same direction. Minimum cycle time: Tclk + δ ≥ tclk-q + CriticalPathDelay+ tsu
  7. 7. 7 This means that clock skew has the potential to improve the performance of the circuit (minimum required clock period reduces!). However, increasing clock skew makes the circuit more susceptible to race conditions. Negative Skew: Clock and data flow in opposite directions Note: Receiving edge arrives before the launching edge On one hand, negative skew adversely impacts the performance (increase the clock period). On the other hand, negative skew implies that the system never has the race problem (since receiving edge happens before). Summary for Clock Skew Minimum Clock Period (Tclk) Worst case is when receiving edge arrives earl, i.e. negative δ. ) Tclk + δ >= tclk-q + CriticalPathDelay+ tsu
  8. 8. 8 Race Condition: Hold Time (Thold) constraint To avoid the race condition, use this equation above to calculate the maximum allowable positive or negative clock skew. Worst case is when receiving edge arrives late, which results in race between data and clock. Example 2: Assume tclk-q is 0.6ns, tsu is 0.4ns, and thold is 0.5ns. The first step once again is to re-model the circuit: direction of clock δ < tclk-q + tpd logic (shortest path) - thold
  9. 9. 9 (a) Determine the minimum clock period assuming a positive clock skew: δ = (tθ’ - tθ) = 1ns. Redraw the circuit to reflect this positive skew. If the clock is in the same direction as the data then (tpd logic–δ) is the “effective” delay and if the clock is in the opposite direction, then (tpd logic + δ) is the “effective” delay. With the new “effective” delay, we can now calculate the clock period in the way as no skew exists. The critical path has now 7ns. Then, Tclk ≥ tclk-q (source register) + tpd logic (longest) + tsu (destination register) Tclk ≥ 0.6 ns + 7 ns + 0.4 ns Tclk ≥ 8 ns (b) Repeat part (a), factoring in a positive clock skew: δ = 3. Here, the critical path is now 8ns. So, Tclk ≥ tclk-q (source register) + tpd logic (longest) + tsu (destination register) Tclk ≥ 0.6 ns + 8 ns + 0.4 ns Tclk ≥ 9 ns (c) Repeat part (a), factoring in a negative clock skew: δ = -2ns.
  10. 10. 10 The critical path is now 10ns. Tclk ≥ tclk-q (source register) + tpd logic (longest) + tsu (destination register) Tclk ≥ 0.6 ns + 10 ns + 0.4 ns Tclk ≥ 11 ns (d) Derive the maximum positive clock skew (i.e. tθ’ > tθ) that can be tolerated before the circuit fails. direction of clock The original circuit is shown above. To determine the maximum (or minimum) clock skews, you need to use the hold time constraint so that race conditions do not occur. tclk-q + tpd logic (shortest) > thold + δ [tpd logic (shortest) in direction of clock] δ < 0.6 ns + 4 ns – 0.5ns δ < 4.1ns (e) Derive the maximum negative clock skew (i.e. tθ’ < tθ) that can be tolerated before the circuit fails. tclk-q + tpd logic (shortest) > thold + δ [tpd logic (shortest) in opposite clock direction ] δ < 0.6 ns + 5 ns – 0.5 ns δ < 5.1 ns References J. M. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits, A Design Perspective (2nd Edition),” Prentice Hall, Electronics and VLSI Series.

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