1. 2004 351h Annual IEEE Power Electronics Specialists Conference Aachen. Germany. 2004
Output Capacitor Comparison for Low Voltage High Current Applications
Chongming Qiao, Jason Zhang, Parviz Parto and David Jauregui
International Rectifier
Email: mqiaol@,irf.com
Abstract: The digital IC such as microprocessor requires low
voltage, high current as well as very tight transient regulation.
This imposes strict requirement for the power supply -
typically a step down PWM converters with single phase or
multi-phase. The output capacitors play an important role in
the transient response. Many types of capacitors are available
in the market such as Aluminum electrolytic, Tantalum,
POSCAP, OSCON cap, Specialty polymer, as well as large
value of multi-layer ceramic capacitors. This paper derives a
basic equation to calculate the minimum number of capacitors
in order to meet the transient requirement. Based on this
information, a compromise between cost and performance can
be decided by engineers.
1. INTRODUCTION
r---------:
f----iL&PWMm n M W
Vdtaae
can- j m
Fiourc 1. A diagram of single-phasesynchmnous buck convertei
The trend of power supply for digital world such as
microprocessor, DSP is that the supply voltage keeps
decreasing and the supply current keeps increasing. The
voltage regulation window becomes much smaller as the
voltage goes down. In the meantime, the slew rate of load
transient current can go as fast as IOOOA/us. All these
requirements impose a challenge for power supply
designers.
Typically, a single-phase or multi-phase synchronous buck
converter is employed to supply the current for
microprocessor or other high-speed digital system such as
memory application [I]. A general diagram is shown in
Figure 1 and typical transient response for synchronous
buck converter is shown in Figure 2. For current
microprocessor, the voltage droop and overshoot
specification during the transient is very tight and it is
typically i5% of nominal output voltage with a IOOA step
load amd 100A/us slew rate. In order to meet the transient
requirement, the selection of inductor [2] and capacitors is
very critical. Suppose the inductor is chosen such that the
inductor current ripple is about 20%-40% of nominal
current, the voltage droop during the transient will be highly
dependent on the output capacitor performance. This paper
will discuss the impact of capacitor on the output voltage
performance during the load transient. Section 111. derives a
simple equation to illustrate the relationship among voltage
droop, output inductor, output capacitor capacitance and
ESR (equivalent series resistor). Section 111 calculates the
minimum number of capacitors to meet the voltage transient
requirement. Section IV. summarizes a comparison among
different capacitors. Section V. discusses “body brake”
technology proposed by International Rectifier to reduce the
overshoot. Simulation and experiment verification was
described in Section VI. and VII. . Finally a conclusion is
given in Section VIII. .
Figure 2. Typicaltransient responsewaveforms.
11. CALCULATION OF VOLTAGE OVERHSHOOT
DURING THE TRANSIENT
In Figure 2, at most of application, the input voltage is much
higher than the output and the typical duty ratio of PWM
converter is much less than 50%. The voltage droop or
overshoot is typically unsymmetrical. Voltage AV,,,,,, is
usually higher than AVdrmp.Therefore, this paper will
emphasize the analysis based on However, the
analysis approach can be applied to AVdrmp as well.
Suppose the load current changes from 102 to 101 at time
t=O, if we assume the bandwidth of the PWM controller
feedback loop is high enough, the synchronous switch will
07803-8399-0/04/$20.M) 02004 IEEE. 622

2. 2004 3Sth Annual IEEE Power ElecrronicsSpecialists Conference Aachm. Germany,2004
be tumed on after t=o. The equivalent circuit is shown in
Figure 3 (a). This will represent the ideal case and give us
minimum voltage overshoot. and minimum capacitors
requirement.
L
T m'02vout-
Load Current
Indudor Current il
(b)
Figure 3. (a). Equivalent circuit (PO+) when the load current goes from
high current 102 to low current 101. (b)Operation waveforms.
Assuming the synchronous switch has very low impedance
and the voltage drop across the switch is neglected. The
inductor voltage will be equal to the output voltage
d4 (2)-Vo(t)=L 1-
dt
If the output voltage droop is much less than the nominal
output voltage, which is true if a tight regulation is required
(e.g. 5% regulation during the transient), the following
approximation exists
where vo,NoM,is the steady nominal DC output voltage.
Suppose the load current is defined as follows
The inductor current can be estimated as
The inductor current will almost linearly decrease. The
current flowing into the capacitor equals inductor current
minus output current. Then after PO+, we have
where hl = Io, -Io, and hl refers to the current step
during the transient.
AAer PO+,, the output voltage can be represented as
Vo(t)=R, .i,(t)+-.lic(t)dt1 _______._____(5)
CO,
Right after t=O, the load current changes to lo1 and the
inductor current can not change instantaneously. Therefore,
At t=O+, we have the following initial condition
i, (t= o+)=
~ c ( t = ~ + ) = ~ o ( N o M j
i,(t=O+)=I,, -r0, =AI
Vo(t = 0+)= Vc(t=0+)+i,(t =0 +).R,
_______ (6)
1-
- 'O(N0M) + R C 'hl
Combination of equation (4) (5) and (6) yields
V O ( t ) = V O ( N O M , +RC.hl+
It is a second order system. It is found that the peak voltage
occurs either at t=O+ or at the time when
which can be exuressed as
dt
Overall, the overshoot can be estimated as
-A'o"ers*,m, -
R, .CO, L 0when --
L.AI
vO(NOM I
If we define system critical frequency
The physical meaning of Fc is how fast the system
recovers during the transient. The higher Fc is, the system
recovers faster. Fzc is the zero frequency caused by ESR
623

3. 2004 35lh Annual IEEE Power Electronics Specialisfs Conference Aachen, Germany. 2004
of the capacitor and it is only determined by the 111. CALCULATION OF MINIMUM NUMBER OF
characteristics of the output capacitor.
The equation (9) can be rewritten as
AVovrrrhmr
OUTPUT CAPACITORS
Suppose the output capacitor is chosen by multiple
capacitors in parallel and the connection between these
capacitors are perfect without any parasitic. The total ESR
and capacitance is given by
I when F, SFzc
The above equation indicates that if the low frequency
capacitor such as electrolytic capacitor is chosen,
F, >Fzc is valid and the overshoot during the transient is
only dependent on the total ESR of output capacitor and
current drops. However, if the high frequency capacitor
such as ceramic capacitor (high F,) is employed, the
overshoot will not only dependent on the ESR, but also the
total capacitance.
Systemdelay
Load
current
Inductor
102
current ,lo1 I , " V
i ;
I ,
idea~w~iajs
I 1 overstcot
Figure 4. The effect ofovenhoot by lhe systemdelay
In practical, the control switch of synchronous buck
converter is not turned off right after the transient. There is
some system delay, which can be caused by system
bandwidth, the load transient timing, parasitic, etc. For the
low frequency capacitor with F, >Fzc, the total output
capacitance is usually very large and the extra overshoot is
not significant. However, for high frequency capacitor such
as ceramic capacitor with F, IFzc, the extra overshoot
caused by system delay can be significant because the total
output capacitance is small. This becomes more critical for
the multiphase condition because each channel will have a
fixed phase delay. From this point of view, it is desirable to
have as fast output voltage loop response as possible if the
high frequency capacitor is employed.
and CO,, = N .C,
ESR,
N
R, =-
R, .CO,,=ESR .C ------------------(13)
where ESR, is the equivalent series resistance for each
output capacitor and C, is the capacitance for each output
capacitor. In order to meet the transient specification, we
should have
E E
Avovwshm, AKron-spm
Combination of the equation (13) and (12) results in the
minimum number of capacitors to meet the transient
specification.
[ when Fc 5Fzc
Un
phase1
Phase2
624

4. 2004 35th Annul IEEE Power Electronics Specialirls Conference Aachen. Germany,2004
Leff=L/m
vo
f -m--
Vin
Outputcurrent 100A
Maximum load c m n t IOOA
transient AI
Load CUR^^ slew rate 2OOA/"S
Output voltage regulation 5% or A v,,_,,=50my
during transient
Number of phase 4
CURCMper phase 2SA
Inductor current ripple far 40%
each phase
Switching frequency for each 2OOkHz
(b)
Figure 5. (a), Multiphasebuck converter. (b)Equivalentcircuit for multi-
phase buck convener during the transient (load current fmm high to low).
The above analysis can be easily applied to multiphase
configuration as shown in Figure 5. For a multiphase
converter, during the transient for load current from high to
low, if the system voltage loop and current loop has infinite
bandwidth, all the synchronous switches for each channel
will be turned on right after the load current changes from
high to low. Assuming all the phases employ inductor with
same inductance, the equivalent circuit shown in Figure 5 is
similar as Figure 3 except the inductor. The inductor is
replaced by effective inductance LCr=x,where m is
the total number of phases. Therefore, for multiphase
applications, replacement of L in equation (14) with
Leu =%will result in the minimum number of output
capacitors for multiphase applications. For the converter
with voltage position approach, the number of minimum
capacitors is reduced because the effective voltage droop
specification is "increased". The above analysis and
calculation results can be also applied by simply modifying
the voltage droop specification. However, it is not discussed
here for simplicity.
IV. COMPARISON OF DIFFERENTOUTPUT
CAI'ACI I ORS ANI) SIMULATION VERIFICA'I'ION
Based on the calculation. several different output
capacitor.; arc choscn for cumpansun. 'I'hc system
requirement is shown in Table 1.
1 ~nputvoltage 1 12v
Table I . A example of low voltage high currentsystem specification with
multi-phaseconfiguration.
Based on 40%of ripple, the output inductor is chosen by
-L 2 (T"- V J V , -
c, .40% .I,,,, .Fs
=0.46p.H
(12 - 1). 1
12.40%. 25.200k~~ ~~
Select L=O.SuH. A comparison for different capacitor is
shown in Table 2. Simulation verification using PSIM5.O is
shown in Table 3. A system level comparison is shown in
Table 4. Based on the Table 2, the designer can select the
right capacitors in term of cost, space, etc. For ceramic
capacitors, because the total number of capacitors is
dominant by the capacitance, if the switching frequency
increases, the required inductor to main certain current
ripple (e.g. 40%) will be smaller. .The total minimum
number of capacitor will also be reduced based on equation
(15).
minimum numberof ceramic Capacitors vs
witching frequency
140
f 120
e
t 100
e o
- 0 802 .:
:$ 60
E 40
L
._
g 20
0
0 200 400 600 800
Switching frequency (kHr)
Figure 6. Calculated minimum numberofceramic capacitor versus
switching frequency.
Figure 6 shows a relationship between minimum ceramic
capacitor versus switching frequency. High switching
frequency requires smaller number of ceramic capacitors.
For electrolytic capacitors, high frequency does not
necessary reduce number of capacitors because the voltage
droop is mainly caused by ESR. Therefore, for ceramic
capacitors, higher switching frequency is preferred.
However, for ceramic capacitors, the analysis does not
625

5. 2004 35th Annual IEEE Power Electronics Specialists Conference Aachen. Germany, 2004
Number of
:apaCiloK due to
ESR
Dominant
SIMII
include ESL (equivalent series inductance) of capacitor and In addition, efficiency will be also reduced at high
layout parasitic factors. In reality, the higher number of
capacitors will be required because of these parasitic effects.
frequency.
Number of Total number of
capacitance
capacitors due to capacitors
Small Small
Dominant Large and
switching
frequency
dependent
Table 2. Comparison of different capacitors to meet the transient responsespecification
Space and Height
Large
Small
limulation results
Output ripple or Overall cost
noise
Large LOW
Small High
I
Aluminum
electrolytic or
OSCON
Special polymer
or ceramic
25 OSCON 82OuF. 12 m n ESR
Load current
. ~ o m
8om
a m .....
.....
4 phab indu'ctorcurrent
porn
ulrn ..................................
I......................
......................
......................i...........
124 ceramic, IOOuF I d 2 ESR each
1v O"lp"1 voltage
..............
..
Table 3. Simulation verification for OSCON and ceramic Cap8CilOK with IOOA transient response
Table 4. System comparison for output capacitors
626

6. 2004 35rhAnnual IEEE Power Elecironics Specialisis Conference Aachen, Germany, 2004
P
pBom
V. REDUCE THE OVERSHOOT WITH BODY BRAKE
International Rectifier Inc. has a trademark “body brake”
concept [3], which can significantly reduce the overshoot for
a step load from high current to low current. The concepj is
to turn off the synchronous FET as soon as the transient load
current starts from high to low. The equivalent diagram is
shown in Figure 7.
f-mw?%Bodydiodeo ~
synchrorous FET
Figure 7. The equivalent diagramwith body brake during the load transient
(current fmm high to low).
During the time period before inductor current goes to 101,
the voltage across the inductor is given as
di
L.-- -V,,,,, +V, (Body diode voltage drop)-(17)
dt
Since at low voltage application (e.g. Iv), the body diode
voltage drop is similar scale as output voltage, the inductor
current decreases almost as two times fast as the case
without body brake concept as shown in Figure 3 (a). As a
result, the voltage overshoot is greatly reduced. Replacing
the V,,,,,, with V,,,,,, cV, in equation (12) will give the
estimated overshoot with body brake concept as shown in
equation (1 8).
A VuVe”hmr
(R,.Al when Fc >Fzc
....... :I .......... :.......;........:_.......
i i j ii jijiiiiiii::::::::::::::::::;:::::::...........................
Figure 8. Operation waveform of the body brake concept implementation.
The implementation of body brake concept is simple. One
comparator is added to compare the output of voltage error
amplifier output and the body brake threshold, which is set
to be slightly lower than the minimum voltage of oscillator
ramp. During the load transient, when the load current
changes from high to low, the output voltage will start to
increase, the voltage feedback loop will respond and the
output of voltage compensator or error amplifier will start to
decrease rapidly. Once the output voltage of voltage
compensator is certain voltage lower than the minimum
voltage of PWM oscillator ramp, the comparator will disable
the synchronous FET driver and allow the output inductor
current flowing through the body diode of synchronous
FET. Assuming the body diode voltage drop is 0.7V, for the
case in.Section IV, 124 IOOuF ceramic capacitor, with body
brake concept, the overshoot when load current from IOOA
to OA will result in 30mV according to equation (IS), which
is about 40% improved comparing with 50mV result shown
in Table 3. The simulation verification is shown in Figure 9.
Loadcurrent
.....;........;........;........4........
::::::::::::::::I::::::::::::::::::::::::
.......................,......................_ L ........ _........_,.................
%re 1 SynchronousFE1driver
._ ~~ .,D. ........L ........C... .....,..................
. ......... .....,m
<m ........................................
n s
..,.........*.......I . ,
.’.
.,e (.?,I‘“. 3,s 11. 1 1 1
nnrln.,
Figure 9. Simulationresults for transient response with body brake forthe
case in Section IV.
VI. CASE OF MIXED OUTPUT CAPACITORS
If the output capacitors are more than one type, such as
combination of ceramic and OSCON capacitors, the analysis
is slightly difficult. One of possible solutions is to do a
simple simulation as shown in Figure IO.The set up for the
two current sources are defined in Figure 11. The voltage
shown in the output will give a good estimate of the voltage
overshoot during the transient.
Output voltage
Figure IO. Simple simulation schematic for transient load with mixed
output capacitors.
627

7. 2004 3.5rh Annual IEEE Power Elecrronics Specialists Conference Aachen, Germany, 2004
Output currentsource
(Load current )
lo1
lnp"tcurrentso102
(Inductor current)
wt=O At t l
At=Len*AlNarm
Figure II.Simulation setup for two currentsources.
VU. EXPERIMENTAL VERIFICATION
International Rectifier introduced iPOWlR technology
which is a breakthrough in power density, efficiency and
simplicity for power conversion. The following experiment
shows a 4-phase application using IP2001 devices. The
'stem requirement is summarized in the following table.
........I..... .................................................................................................
imWtfhlemslEkkfMqriim
!
i...,........................
Figure 12. Internal Blockdiagram oflPZ00I.
Table 5. System specification
In reality, the ceramic capacitor is not ideal; the resistance
caused by layout is not negligible compare with the ESR of
ceramic. In addition, the previous analysis neglects the
output voltage ripple. In fact, the ripple ofthe output voltage
can contribute to the overall the voltage regulation
specification. More important, for multiphase application,
each channel has a phase delay referring to the other
channel. During the transient, it is impossible that all the
control switches will be turned off at same time. This delay
will cause more voltage droop or overshoot during the
transient. Therefore, the selected output ceramic capacitors
are more than the minimum capacitance. In this application,
the total capacitors are about 2000uF.
T s k m 1.00MSfs 33 Aces
r - 4
A:27.6mV
. . . .
. . .
. . . . . . . . . . . . . . .+ . . . . . . . . . . . . .
i . . . :. .
. .
: i : : :. .
i
. . . . . . I . . . . . .. . . .
. .
. . . . . . . . . . . . : . . T . . : . . . . . . . . . . .
. . .
. .
. . .
. ., , . ~: : i
M 5 0 . 0 ~ 1chl I I .35 9 Mar2002
10:04:56
Figure 13. Expenmental waveforms for output voltage ai 54A load current
transient.
VIII. CONCLUSION
The high-speed digital processor requires strict
requirement on the voltage regulator. In this paper, based on
a simplified circuit diagram, the relationship between
voltage overshoot, output inductor and output capacitors are
derived. Furthermore, an equation is derived to calculate the
minimum number of capacitors in order to meet the transient
specification. It shows that the minimum number of
capacitors is not only dependent on the ESR of capacitor,
but also the total capacitance. A comparison among
aluminum electrolytic, OSCON, polymer and ceramic
capacitors is given in details. Analysis along with
simulation verification is provided. This paper provides a
general guideline to choose the output capacitors based on
the system requirement.
ACKNOWLEDGMENT
The author would like to thank for the advise of professors
Keyue Smedley, Franco Maddaleno and the help of
colleagues Mark Yabut, Veng Tang, etc.
REFERENCES:
[I] Peng Xu; Jia Wei; Kaiwei Yao; Yu Meng; Lee, F.C.;
Investigation of candidate topologies for 12 V VRM Applied
Power Electronics Conference and Exposition. 2002. APEC
2002. Seventeenth Annual IEEE , Volume: 2 , 10-14 March
2002 Pa&): 686 -692 vol.
Pit-Leong Wong; Lee, F.C.; Peng Xu; Kaiwei Yao. Critical
inductance in voltage regulator modules; Applied Power
Electronics Conference and Exposition, 2002. APEC 2002.
Seventeenth Annual IEEE , Volume: 1 , 10-14 March 2002
Page($): 203 -209 v0l.l
[2]
131 1133086datasheet..
628