Low power in vlsi with upf basics part 2

Low Power in VLSI with UPF
Basics - Part 2
G.Sunodh Kumar
Front End DV Engineer

How can we verify our Low Power
Design with power management cells ?

Low Power Verification : Power Intent
• All the power management and reduction techniques listed in the previous
section are solely based on direct manipulation of voltage, in terms of supply
power connectivity and voltage area or power network distributions on the
chip.
• Nevertheless, none of these were sufficient to understand and reflect the
power aware verification plan or power intent to start power or voltage aware
verification at the register transfer level (RTL) or even after gate-level
synthesis.
• Usually, RTL in Verilog,VHDL, or SystemVerilog, are the golden reference
design, and it is totally unconventional to add supply networks and their
corresponding connectivity to these references.

Low Power Verification : Power Intent
• Eventually, it is also impossible to distribute certain instances of a design
hierarchy to specific voltage areas unless the design reaches the floor-planning
stage of design implementation.
• Evidently the industry was facing the absence of a methodology that can help
to verify power connectivity, voltage distributions in a design.
• So, In early 2007, the Accellera Systems Initiative introduced the Unified
Power Format (UPF), also known as UPF 1.0 that allows users to define and
manage power for designs without any direct interference with the golden
HDL reference design.

UPF : IEEE STANDARD
• In 2009, the IEEE Standard Organization published the IEEE-1801-2009 or
UPF 2.0, the first standard methodology for implementing power intent, truly
for any design abstraction level.
• An Evolving Standard
• Accellera UPF in 2007 (1.0) : 32 commands.
• IEEE 1801-2009 UPF (2.0) : 88 commands: 49 Power Intent and 39 Query
commands.
• IEEE 1801-2013 UPF (2.1) : 86 commands: 46 Power Intent, 6 Power Management,
and 34 Query commands
• IEEE 1801a-2014 UPF (2.2) : fixed technical and editorial errors identified in UPF 2.1
• IEEE 1801-2015 UPF (3.0) : 62 commands: 51 Power Intent, 6 Power Management,
and 5 Query commands

UPF : What does it do ?
s
• The UPF is used to partition a design into power domains, where each power
domain is powered by a supply network of supply ports, power switches, and
supply nets.
• Various strategies can be applied to power domains to control logic values when
the domains are being switched off and on.
• Isolation strategies are used to ensure undefined outputs from powered-down
design elements do not drain power from those design elements that are not
powered down.
• They also ensure a specific logic value is driven from the power domain’s
outputs.
• Retention strategies specify which objects in a domain need to be retained while
powered down. Level shifter strategies translate signal values from an input
voltage swing to a different output voltage swing.

UPF : What does it do ? conti...
• The backbone of UPF, as well as the similar Common Power Format (CPF), is
the Tool Control Language (TCL), a scripting language originally created to
provide a way to automate the control of design software.
• The attraction of TCL is that command-line commands can be used as
statements in a script. Most Tcl implementations are specific to an individual
tool. However, the CPF and UPF definitions are unusual in that they are meant
to be used with all tools in a power-aware flow – the tools themselves have to
determine whether the commands supplied in the Tcl script are relevant to
them or not.

s
• UPF is designed to reflect the power intent of a design at a relatively high level.
• So TCL power specification commands written in UPF script describe
 Which power rails should be routed to individual blocks,
 When blocks are expected to be powered up or shut down,
 How voltage levels should be shifted as signals cross from one power
domain to another and
 Whether measures should be taken to retain register and memory-cell
contents if the primary power supply to a domain is removed.

• The TCL command “create_power_domain”, for example, is used by UPF-aware
tools to define a set of blocks in the design that are treated as one power domain
that is supplied differently to other blocks on the same chip.
• The idea behind this type of command is that power-aware tools read in the
description of which blocks in a design can be powered up and down
independently. The tools can use that information to determine, for example, how
a simulation will behave under different conditions.
• So power specification commands provided in a UPF file can be used by
simulation, synthesis, equivalence checking, physical design and physical
verification.

• For example, a testbench written in SystemVerilog may identify to the
simulator that a particular block should be powered down to ensure that other
blocks do not access it without checking on power status first.
• A transistor-level simulation may use the power definitions to see what
happens when supply voltages or substrate bias voltages change. Do all the
necessary logic paths meet expected timing when the supply voltage to one
block is lowered to save power while others are running at their maximum
voltage? Similarly, a static analysis tool may check that the correct level
shifters are in place to determine whether blocks in different power domains
can communicate.

Low power Design
Environment that
Fully adopts
The design flow for a
multi-voltage,
power gating design
follows that of a standard
implementation with
a few exceptions.

IEEE Standard UPF Commands
 Setting scope
• The set_scope command specifies the instance to which the active UPF scope is
set. If no instance name is specified, the scope is that of the top level.
• Syntax :
 set_scope Module_Top/
 set_scope .. - the UPF scope is moved up one level in the design hierarchy.
 set_scope . - Current scope

 Defining Power Domains
• The create_power_domain command creates a power domain with the specified
name
• Syntax :
 create_power_domain PDA
- elements {U1 U2} - scope U_B1
 create_power_domain PDB
- elements {U3 U4} - scope U_B1
 set_scope U_B2
 create_power_domain PDC
- elements {U5 U6 U7}

 Defining Power Domains
• The create_power_domain another example
• Syntax :
 create_power_domain PD_TOP - include_scope
# PD_TOP includes all elements at top and its children.
 create_power_domain PD_SW
- elements {U2/U3 U2/U4 U2/RR}

 Defining Power Connectivity
• The creating_supply_port for each power domain that is defined, supply and
ground ports must be specified
• Syntax : # VDD supply ports:
 create_supply_port PVDDTop1 - domain PDTOP
 create_supply_port PVDD - domain PDA
 create_supply_port PVDDB - domain PDB
 create_supply_port PVDD - domain PDC

• The creating_supply_port for each power domain that is defined, supply and
ground ports must be specified
• Syntax : # ground ports:
 create_supply_port PVSS - domain PDTOP
 create_supply_port PGND - domain PDA
 create_supply_port PGND - domain PDB
 create_supply_port PGNDC - domain PDC

• The create_supply_net command is used to connect the supply ports created.
• Syntax :
 create_supply_net GND_NET - domain PDTOP
 create_supply_net VDDTop1 - domain PDTOP
 create_supply_net GND - domain PDA
 create_supply_net VDDB - domain PDB
Note:
• Once a net is created, the - reuse option can be used for any subsequent creations of that net in different domains
within the same scope. There is also no need to create the subdomain ports or connect to them. Creating a supply net
with - reuse in a lower domain automatically creates the port and connects it up in that power domain.

• The connect_supply_net command is used to connect the supply net to one or
more supply ports..
• Syntax :
 connect_supply_net GND_NET
-ports {PDA/PGND PDB/PGND PDC/PGNDC PVSS}
 connect_supply_net VDDTop1
-ports {PVDDTop1 PDA/PVDD}
 connect_supply_net VDDTop2
-ports {PVDDTop2 PDB/PVDDB}
 connect_supply_net VDDB
-ports PVDDB - domain PDB

 Primary Supplies of a Domain
• This is specified using the set_domain_supply_net command. It specifies one
primary power and ground connection for every power domain.
• Syntax :
 set_domain_supply_net PDB
- primary_power_net VDDB
- primary_ground_net GND

 Creating a Power Switch
• The create_power_switch command creates a power switch in the specified domain.
A power switch has an input supply port and an output supply port. It also has a
control port and specification of what control signal causes the switch to turn on.
• Syntax :
 create_power_switch PD_GPU_SW
- domain PD_GPU
- input_supply_port {VDDI VDD_DV}
- output_supply_port {VDDO VDD_DV_SW}
- control_port {SLEEPI PWRCTL_SLEEP}
- control_sense high
- ack_port {SLEEPO PWRCTL_ACK}
- ack_delay {SLEEPO 1}
- on_state{on_state VDD_DV !PWRCTL_SLEEP}
- off_state {off_state PWRCTL_SLEEP}

 Mapping the Power Switch
• This command specifies which cell to use from a technology library for a power
switch.
• Syntax :
 map_power_switch PD_GPU_SW
- domain PD_GPU
- lib_cells PMK/HEADBUF16

 Power State Table to Supply Port
• A power state table is used to define the legal combination of states that can exist
in a design. PST also captures all possible operating modes of the design in terms
of power supply levels.

 Power State Table to Supply Port
• The add_port_state command adds state information to a supply port. It specifies the list of
possible states of a port. Each state is specified as a state name and a voltage level. The
state name is used to de fi ne all possible operating states later. The voltage level can be a
single value, two values (minimum and maximum) or a set of three values (minimum,
nominal, and maximum) or off
• Syntax :# Define the states of the ports first:
 add_port_state VDDG
- state {S0p8 0.8}
 add_port_state VDD_ON
- state {S1p0 1.0}
- state {S1p2 1.2}
 add_port_state VDD_SW
- state {S1p0 1.0}
- state {S1p2 1.2}
- state {sw_off off}

 Power State Table
• The create_pst command creates a power state table called PST_Z with the list of four
ports.
• The add_pst_state command defines the combination of port or net state values for each
power state.
• Syntax :
 create_pst PST_Z - supplies {VDDG VDD_ON VDD_SW}
 add_pst_state PST1 - pst PST_Z - state {S0p8 S1p0 S1p0}
 add_pst_state PST2 - pst PST_Z - state {S0p8 S1p2 S1p2}
 add_pst_state PST3 - pst PST_Z - state {S0p8 S1p0 sw_off}
 add_pst_state PST4 - pst PST_Z - state {S0p8 S1p2 sw_off}
Note:
• The order of entries in the - state option is the same as the list of states in the create_pst command, which
means that for PST1 state S0p8 is a value of the state of port VDDG, S1p0 is a value of the state of port
VDD_ON and VDD_SW

 Level Shifter Specification
• The set_level_shifter command is used to specify the strategy for inserting level
shifters. Level shifters are inserted on all nets that have their source and
destination at different voltages (which have their source and destination in
different power domains).
• Syntax : set_level_shifter strategy_name
- domain_name domain_name
- element port_pin_list
[specifies the list of pins and ports in the domain to which the level shifter strategy is being applied.]
- applies_to inputs | outputs | both
- threshold float
[defines the voltage, in Volts, for determining when to insert level shifters. If the difference between
two domains is greater than the threshold, level shifters are inserted. The default is 0V]

 Level Shifter Specification conti...
 set_level_shifter strategy_name
- domain_name - element - applies_to inputs | outputs | both - threshold float
- rule low_to_high | high_to_low | both
[specifies to insert level shifters when going from low to high voltage or high to low or both which implies
adding level shifters either when going from low to high voltage or when going from high to low voltage.]
- location self | parent | fanout | automatic
[ specifies where to place the level shifters
• self value indicates to put the LS inside the domain whose pins are being level shifted
• parent value speci fi es placing the level shifter in the parent domain
• fanout value specifies the placement of the level shifter within all sink (or fanout) domains of the port or
pin
• automatic value specifies that the tool is free to choose any location]

• Strongly recommended that level shifters be used on all power domain interfaces where an up
shift is required, since this prevents crowbar currents and improves edge rates and therefore
timing.
• In general, level shifters be used on all power domain interfaces where a down shift is required.
It is safe to overdrive the input in the lower voltage domain. However, the timing
characteristics of the destination cell will assume a correctly driven input signal operating at
the same voltages the output driver of the cell. There will be an error in calculating the delay if
a level shifter is not used. Thus, we recommend -rule both.
• The placement of the level shifters is important. The output driver for a level shifter requires
more supply current than the input stage. For this reason, we recommend placing the level
shifter in the destination domain – the domain that the level shifter output drives. This assures a
high quality power connection to the output stage of the level shifter cell.

• When the voltage difference between the two power domains is less than the threshold
voltage then level shifters are not strictly required. However, when making this decision,
the tolerance of the power supplies should be considered.
• It may be the case that when both power domains are being powered by ideal supplies that
the voltage difference is tolerable, however when worst case variation between the power
supplies is considered, the difference may be too great and level shifting required.
• So Using the default -threshold of 0V is a safe initial value. If timing across critical
interfaces becomes a problem, we can revisit this issue and specify a different value.

a
Level shifter strategy that applies to the inputs of a power domain.
 set_level_shifter LS_INPUTS
- domain PD_SHUTDOWN
- applies_to inputs
- rule high_to_low
- location self
Here is an example that describes a level shifter strategy for outputs.
 set_level_shifter LS_OUTPUTS
- applies_to outputs
- rule low_to_high
- location parent

 Mapping Level Shifter cell conti...
• This command specifies which cell to use from a technology library for a level
shifter.
• Syntax :
 map_level_shifter_cell Level_Shift_name
- domain domain_name
- lib_cells library_list

 Isolation Strategy
• The set_isolation command is used to define an isolation strategy for a power
domain.
• Syntax :
 set_isolation isolation_ strategy_name
- domain power_domain [The domain for which this strategy is applied]
- isolation_power_net iso_power_net_name
- isolation_ground_net iso_ground_net_name
[a single power net, a single ground net, or both. If only an isolation power net is specified, then the primary
ground serves as the isolation ground. If only an isolation ground net is specified, then the primary power
net serves as the isolation power.]
- clamp_value { 0 | 1 | latch}
[The value to which the input or output shall be clamped. The default is 0.]

 Isolation Strategy conti...
• Syntax :
 set_isolation isolation_ strategy_name
- domain < > - isolation_power_net < >
- clamp_value { 0 | 1 | latch}
[The value to which the input or output shall be clamped. The default is 0.]
- applies_to { inputs | outputs | both}
[Whether the domain’s input ports, output ports, or both are isolated. The default is outputs.]
- elements objects
[A list of design elements, input ports/pins, output ports/pins, and nets to which this strategy is
applied.]
- no_isolation
[Specifies that isolation cells shall not be inserted on the specified ports.]

• The set_isolation_control command contains the specification of the isolation
control signal.
• Syntax :
 set_isolation_control isolation_strategy_name
- domain power_domain
- isolation_signal isolation_signal
[ The isolation_signal can only be a net; cannot be a port or a pin]
- isolation_sense {low | high}
[ specifies the logic state of isolation cells in isolation mode.]
- location { self | parent}

a
Syntax :
 set_isolation ISO_OUTPUT
- isolation_power_net VDDG
- isolation_ground_net VSS
- clamp_value 0
- applies_to outputs
 set_isolation_control ISO_OUTPUT
- isolation_signal ISOLATE_CTRL
- isolation_sense low
- location parent

 Mapping Isolation cell conti...
• This command specifies which cell to use from a technology library for a
Isolation cell.
• Syntax :
 map_isolation_cell ISOLATION_STAG_NAME
- lib_cells lib_cell_name
- lib_cell_type lib_cell_type
- lib_model_name lib_cells_name
- elements objects

 Output Isolation vs. Input Isolation
• For an output signal that goes to multiple different power domains, only one isolation cell
is required with output isolation. With input isolation, each destination would require its
own isolation cell.
• With output isolation, all the isolation cells in a domain share a common control signal.
With input isolation, a block may require multiple isolation control signals – one from each
domain from which it gets an isolated signal.
• Output isolation has one drawback, which is that custom isolation cells are required.
Although they function as AND or OR gates, isolation cells require always-on power. Most
standard cells connect power and ground through abutment. But in a power gated domain,
one of the supplies connected by abutment is switched. Therefore (output) isolation cells
require special physical design to accommodate connection to the always on supply

 Retention Strategy
• The set_retention command specifies which registers in the power domain are to be
implemented as retention registers and identifies the save and restore signals.
• Syntax :
 set_retention retention_strategy_name
- retention_power_net ret_power_net_name
- retention_ground_net ret_ground_net_name
- elements objects

 Retention Strategy conti...
• Every retention strategy must have a corresponding set_retention_control
command. This command allows the specification of the retention control signal and
its sense.
• Syntax :
 set_retention_control ret_strategy_name
- save_signal {save_signal_name high | low}
- restore_signal {restore_signal_name high | low}

 Mapping Retention cell conti...
• This command specifies which cell to use from a technology library for a
Retention cell.
• Syntax :
 map_retention_cell ret_strategy_name
- lib_cells lib_cells
- lib_cell_type lib_cell_type
- lib_model_name lib_cells_name
- elements objects

 Retention cell conti...
• Syntax :
 set_retention UP_RET_POLICY
- domain PD_UP
- retention_power_net VDDG
- retention_ground_net VSS
 set_retention_control UP_RET_POLICY
- domain PD_UP
- save_signal {NSAV low}
- restore_signal {RETN high}
 map_retention_cell MULT_RET
- domain PD_UP
- lib_cells RSDFF_X8T40

Now we will take a real time design
and write UPF script

UPF Commands Example
• The example design has four power domains
1. PD_MYCHIP : 1.0 V, always-on, associated with logic in top-level MYCHIP .
2. PD_CPU : 0.9 V, always-on, associated with logic in module instance U_CPU .
3. PD_COP : 1.1 V, shutdown, associated with logic in module instance U_COP .
4. PD_DSP : 1.1 V or 0.9 V, externally switched, associated with logic in module
instance U_DSP .

• Table 8.3 : The power controller is a module at the top level that provides the various
control signals for handling the power switching & generates the necessary control signals
to control the power domains.
• Table 8.2 : describes the power mode table, that is, the various power operating modes(ex
: active-PM1, standby-PM2, sleep-PM3, deep sleep-PM4 modes) of the design.

Note:
• Once a net is created, the - reuse option can be used for any subsequent creations of that net in different
domains within the same scope. There is also no need to create the subdomain ports or connect to them.
Creating a supply net with - reuse in a lower domain automatically creates the port and connects it up in
that power domain.
VDD1P0
VDDdsp
VDD0p9
GND
VDD1P0_SW

VDD1P0
VDDdsp
VDD0p9
GND
VDD1P0_SW

EDA tools help to verify Power Intent design
a
• EDA offers designers the much-needed infrastructure and tools for enabling power
management throughout the flow.The Key EDA vendors are
• Synopsys provides an automated, end-to-end power management solution that
delivers the low power implementations. It ensures consistent correlation from RTL
to silicon, enabling design teams to benefit from reduced iterations and improved
productivity. The Synopsys' solution utilizes industry standards such as Unified
Power Format (UPF)
• Cadence Low Power Flow : Cadence has developed a complete solution for the
design, verification, and implementation of low power SoCs. The low power solution
combines a number of technologies from several Cadence platforms. Each of these
advanced products also leverages the Common Power Format (CPF)
Note : For more information related to tools go to refererence link[9] slide

Summary
a
• How can we achieve low power in chip ?
 By implementing low power techniques like reducing switching activity,
having multi voltage domain in system level.
• How can we Implement low power techniques ?
 By using power management cell like level shifter, isolation cell etc...
• How can we Integrate cells or verify our design in Power perspective ?
 By writing power intent UPF script and using EDA tools

References
a
[1]. Michael Keating, David Flynn, Robert Aitken, Alan Gibbons and Kaijian Shi, "Low Power Methodology Manual For
System-on-Chip Design [M]", Springer: Synopsys Inc. & ARM, 2007.
[2]. Rakesh Chadha, J Bhasker, - ”An ASIC Low Power Primer Analysis, Techniques and Specifications”, Springerlink,
[3]. Multi-Domain Verification: When Clock, Power and Reset Domains Collide by Ping Yeung, Erich Marschner Design &
Verification Technology Mentor Graphics, Fremont, U.S.A.
[4]. Unified Power Format, “1801-2013 IEEE Standard for Design and Verification of Low-Power Integrated Circuits”.
[5]. Progyna Khondkar, - ”Low-Power Design and Power-Aware Verification”, Springer International Publishing AG 2018
[6]. https://semiengineering.com/an-introduction-to-reducing-dynamic-power/
[7]. https://www.ti.com/logic-circuit/voltage-level-translation/overview.html
[8]. https://e2e.ti.com/blogs_/b/analogwire/archive/2016/09/22/how-level-shifters-enable-the-transition-to-low-voltage-processors-in-
industrial-environments
[9]. https://www.eetimes.com/low-power-design-techniques-design-methodology-and-tools/
[10].https://chipress.co/2019/05/08/why-is-isolation-cell-required-in-power-aware-design/

References
a
[11]. https://semiengineering.com/power-verification-x-marks-spot/
[12]. https://www.research.ibm.com/haifa/conferences/hvc2008/present/The_challenges_of_low_power_design.pdf
[13]. https://www.embedded.com/minimize-leakage-power-in-embedded-soc-designs-with-multi-vt-
cells/#:~:text=To%20minimize%20leakage%20power%2C%20Multi,used%20at%20timing%2Dcritical%20places.
[14]. http://emicroelectronics.free.fr/onlineCourses/VLSI/ch07.html
[15]. https://www.edn.com/reducing-ic-power-consumption-low-power-design-techniques/
[16]. https://www.socionext.com/en/products/customsoc/design/low-power.html
[17]. https://www.synopsys.com/glossary/what-is-low-power-design.html
[18]. https://www.cadence.com/en_US/home/solutions/low-power-solution/power-aware-implementation.html
[19]. http://www.kunyuanic.com/upload/20191225091147_573.pdf
[20]. https://rtldigitaldesign.blogspot.com/2014/05/upf-unified-power-format.html
[21]. https://www.eetimes.com/upf-3-0-is-now-official/
[22]. http://fresnostate.edu/engineering/faculty-research/astill/documents/Shylesh_Umapathy_Thesis_Report.pdf

Thank You
Have a Happy Learning
For any query please contact to
Email ID : Sunodh.kumar005@gmail.com
( Feedback is appreciated , Your Valuable feedback helps us to do more )

Low power in vlsi with upf basics part 2

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