presentation about the metastability in digital logic design

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o flip-flops are subject to a problem called metastability.
o due to this metastability the output data is corrupted.
o this metastability will occur due to setup and hold time violations.

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o At the end of the of metastable state the flip-flop settle down either 0 or 1.

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o In metastable state the flip-flop output will oscillate around the 0 and 1.
o But it will settle after some time to 0 or 1.
ohow much it takes to settle is depend upon the technology of the flip-flop.

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o Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous input signals to the flip-flop.
o Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous input signals to the flip-flop.

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Stable point
Metastable point
Stable point

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As we have seen that whenever setup and hold violation time occurs, metastability occurs, so we have to see when signals violate this timing requirement:
I.When the input signal is an asynchronous signal.
II.When the clock skew/slew is too much (rise and fall time are more than the tolerable values).
III.When interfacing two domains operating at two different frequencies or at the same frequency but with different phase.
IV.When the combinational delay is such that flip-flop data input changes in the critical window (setup+hold window)

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o how to avoid this metastable state…….
o we can use the cascading the flip-flops.

9. THANK YOU
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