This document contains a university question bank for the subject EC 2354-VLSI Design. It includes questions from previous years' exams divided into multiple parts. Part A contains short answer questions covering topics like non-ideal I-V effects in MOS transistors, layout design rules, body effect, CMOS and BICMOS technology comparison, MOS transistor I-V characteristics, operating regions, and more. Part B includes longer questions requiring explanations about CMOS process enhancements, I-V characteristics, body effect, DC transfer characteristics, CMOS inverter layout, and other topics. The document covers 5 units - non-ideal effects and layout design rules, transistor sizing and interconnect modeling, sequential circuits, testing techniques,

1. Omsakthi
Adhiparasakthi Engineering College, Melmaruvathur
Department of Electronics and Communication Engineering
EC 2354-VLSI Design - University Question Bank
Unit-1
Part- A
1. What are the non-ideal I-V effects?( April 2014)
2. Discuss any two layout design rules. ( April 2014)
3. What is meant by body effect?(Nov 2014)
4. What is the need for design rules? (Nov 2014)
5. List the various issues in technology CAD. (May 2013)
6. Define the lambda layout rules.(May 2013)
7. Compare CMOS and BICMOS technology. ( Nov 2013)
8. Draw the DC transfer characteristics of CMOS inverter. (Nov 2013)
9. Draw the IV characteristics of MOS transistor.(May 2012)
10. Brief the different operating regions of MOS system. (May 2012)
11. Why the tunneling current is higher for NMOS transistors than PMOS transistors
with silica gate? (Nov 2012)
12. What is the objective of layout rules? (Nov 2012)
13. Draw the energy band diagrams of the components that make up the MOS system.
(April 2011)
14. What is body effect coefficient? (April 2011)
15. Determine whether an NMOS transistor with a threshold voltage of 0.7 V is
operating in the saturation region if Vgs=2V and Vds =3V.(Nov 2011)
16. Write down the equation for describing the channel length modulation effect in
NMOS transistors. (Nov 2011)
Part- B
1. Discuss the C-V characteristics and DC transfer characteristics of the CMOS. (April
2014)
2. Briefly discuss about the CMOS process enhancements and layout design rules.
(April 2014)
3. (i) Derive drain current of MOS device in different operating regions. (10) (Nov 2014)
(ii) Describe with neat diagram the well and channel formation in CMOS process.(6)
4. (i) Describe on CMOS process enhancements. (8) (Nov 2014)
(ii) With the processing steps involved, explain copper dual damascene interconnect.
5. Explain in detail about the ideal I-V characteristics and non-ideal I-V characteristics
of NMOS and PMOS devices.(May 2013)
6. (i) Explain in detail about the body effect and its effect in NMOS and PMOS
devices.(8) (May 2013)
(ii) Derive the expression for DC transfer characteristics of CMOS inverter. (8)
7. Derive an expression for Vin of a CMOS inverter to achieve the condition vin=vout.
What should be the relation for βn= βp. (Nov 2013)

2. 8. Explain the electrical properties of MOS transistor in detail. (Nov 2013)
9. Discuss in detail about (i) Full- Custom mask layout design (ii) CMOS inverter
layout design. (May 2012)
10. (i) With a neat diagram discuss in detail about DC transfer characteristics of CMOS.
(ii) Write a note on the following along with the mask view a) Oxide related
capacitance b) Junction capacitance. (May 2012)
11. (i) Explain the different steps involved in N-well CMOS fabrication process with
neat diagrams. (10) (Nov 2012)
(ii) Draw the CMOS inverter and discuss its DC characteristics. Write the conditions
for the different regions of operation. (6)
12. (i) Explain the principle of SOI technology with neat diagrams. Discuss its
advantages and disadvantages. (8) (Nov 2012)
13. (i) Explain in detail with a neat diagram the fabrication process of the NMOS
transistor. (April 2011)
(ii) Discuss in detail with a neat layout, the design rules for a CMOS inverter.
14. (i)Discuss in detail with necessary equations the operation of MOSFET and its
current-voltage Characteristics.
(ii) Explain briefly CMOS process enhancements. (April 2011)
15. (i)Draw and explain the DC transfer characteristics of a CMOS inverter with
necessary conditions for the different regions of operation.(8) (Nov-2011)
16. (i) Explain the gate, source/drain formation and isolation steps of CMOS fabrication
process with neat diagrams. (8) (Nov-2011)
(ii) Give a brief note on the different process techniques to enhance the performance
of CMOS transistors.(8)
Unit- 2
Part-A
1. Define transistor sizing problem. ( April 2014)
2. What do you mean by design margin? ( April 2014)
3. Give the expression for Elmore delay and state the various parameters associated
with it. (Nov 2014)
4. List different types of scaling. (Nov 2014)
5. What is meant by design margin? (May 2013)
6. How do you define the term “device modeling”? (May 2013)
7. Define power dissipation. (Nov 2013)
8. Define scaling. Mention the types of scaling. (Nov 2013)
9. Brief about the variation of the fringing field factor with the interconnect geometry.
(May 2012)
10. Draw the equivalent circuit structure of the level 1 MOSFET model in SPICE. (May
2012)
11. Give the effect of supply voltage and temperature variation on the CMOS system
performance. (Nov 2012)
12. What are the factors that cause static power dissipation in CMOS circuits? (Nov
2012)
13. What is the influence of voltage scaling on power and delay? (April 2011)

3. 14. Express T PHL and TPLH in terms of Cload. (April 2011)
15. Write the expressions for the logical effort and parasitic delay of n input NOR gate.
(Nov 2011)
16. Why does interconnect increases the circuit delay? (Nov 2011)
Part-B
1. Explain the following (i) device models and device characterizations. (10)
(ii) power dissipation in CMOS circuits. (6) ( April 2014)
2. (i) Describe the simulation of circuit interconnects. (8) ( April 2014)
(ii) Write about SPICE based circuit simulation. (8)
3. (i) Derive expressions for effective resistance and capacitance estimation using RC delay
models.(8) (Nov 2014)
(ii) Discuss on transistor and interconnect scaling. (8)
4. (i) Derive the final expression and explain path logical effort, path electrical effort, path
effort and path branching effort.(8) (Nov 2014)
(ii) Size the transistors of CMOS three input NOR gate for logic ratio of 1/3. (8)
5. (i) Explain in detail about the scaling concept and reliability concept. (8)
(ii)Describe in detail about the transistor sizing for the performance in combinational
networks. (8)(May 2013)
6. Discuss in detail about the resistive and capacitive delay estimation of a CMOS inverter
circuit. (May 2013)
7. Derive an expression for the rise time, fall time and propagation delay of a CMOS
inverter. (Nov 2013)
8. Explain the various ways to minimize the static and dynamic power dissipation. (Nov
2013)
9. (i) Obtain an expression for level-2 model equation of MOSFET in the SPICE. (May
2012)
(ii) Discuss in detail about a) variation of mobility with electric field b) variation of
channel length in saturation modes. c) saturation of carrier velocity.
10. (i) How do the SPICE MOSFET model account for the parasitic device capacitances?
(ii) Explain the characterization of circuits. (May 2012)
11. (i) Explain the different factors that affect the reliability of CMOS chips. (Nov 2012)
(ii) Discuss the principle of constant field and lateral scaling. Write the effects of the
above scaling methods on the device characteristics.
12. (i) Discuss the mathematical equations that can be used to model the drain current and
diffusion capacitances of MOS transistors. (8) (Nov 2012)
(ii) Give a brief note on logical effort and transistor sizing. (8)
13. Explain in detail about (i) Channel length modulation (ii) constant field scaling (iii)
Constant voltage scaling. (April 2011)
14. With necessary equations, explain in detail about: (i) Short current effect (ii) Narrow
channel effect. (April 2011)
15. (i) Explain the static and dynamic power dissipation in CMOS circuits with necessary
diagrams and expressions. (10) (Nov-2011)

4. (ii) Discuss the principle of constant field scaling and also write its effect on device
characteristics. (6)
16. (i) Explain the different reliability problems related to the design of reliable CMOS
chips.(10) (Nov-2011)
(ii) Give a brief account on design margin. (6)
Unit-3
Part-A
1. What are synchronizers? ( April 2014)
2. State any two criteria for low power logic design? ( April 2014)
3. What is complementary pass transistor logic? State its advantages over CVSL. (Nov
2014)
4. Differentiate Latch and Flip-Flop. (Nov 2014)
5. List the various power losses in CMOS circuits. (May 2013)
6. Enumerate the features of synchronizers. (May 2013)
7. Implement 2:1 multiplexer using pass transistors. (Nov 2013)
8. Design a 1 bit dynamic register using pass transistors. (Nov 2013)
9. Compare CMOS combinational logic gates with reference to the equivalent MOS
depletion load logic with reference to the area requirement. (May 2012)
10. What are the disadvantages of using a pseudo NMOS gate instead of a full- CMOS
gate? (May 2012)
11. State the reasons for the speed advantage of CVSL family. (Nov 2012)
12. Mention the qualities of an ideal sequencing method. (Nov 2012)
13. Draw the circuit diagram of a CMOS bistable element and its time domain behavior.
(April 2011)
14. Write a note on CMOS transmission gate logic. (April 2011)
15. Draw a pseudo NMOS inverter. (Nov 2011)
16. What is the advantage of differential flip flops? (Nov 2011)
Part-B
1. Explain the methodology of sequential circuit design of latches and flip-flops. ( April
2014)
2. Briefly discuss about the classification of circuit families and comparison of the circuit
families. ( April 2014)
3. (i) Compare static and dynamic logic circuit with example. (8) (Nov 2014)
(ii) Explain the dynamic and static power reduction in low power design of VLSI
circuits. (8)
4. (i)What are klass semidynamic flip-flops? Explain their logic circuits. (8)
(ii) Discuss on skew tolerant Domino circuits.(8) (Nov 2014)
5. Explain in detail about the pipeline concepts used in sequential circuits. (May 2013)
6. Discuss the design techniques to reduce switching activity in a static and dynamic
CMOS circuits. (May 2013)
7. (i) Implement Y = (A+B) (C+D) using the standard CMOS logic. (Nov 2013)

5. (ii) Implement NAND gate using pseudo-nMOS logic.
8. (i) Implement D- flip flop using transmission gate.(8) (Nov 2013)
9. (i) For a two input NAND gate derive an expression for the drain current.(8) (May 2012)
(ii) Draw a CMOS NOR2 gate and its complementary operation with necessary
equations.(4)
(iii) Obtain a CMOS logic design realizing the Boolean function Z= A(D+E)+BC.(4)
10. (i) Draw a circuit diagram of the CMOS SR latch and explain in detail. (8) (May 2012)
(ii) Along with the necessary input and output waveforms of the CMOS DFF negative
triggered master slave D flip-flop. (8)
11. (i) Describe the different methods of reducing static and dynamic power dissipation in
CMOS circuits. (Nov 2012)
(ii) Explain the domino and dual rail domino logic families with neat diagrams.
12. (i) Draw and explain the operation of conventional CMOS, pulsed and resettable latches.
(ii) Write a brief note on sequencing dynamic circuits. (Nov 2012)
13. Explain in detail about pseudo-NMOS with neat circuit design. (8) (April 2011)
14. (i)Design a transistor level schematic of the one bit full adder circuit and explain.
(ii) Discuss in detail the characteristics of CMOS transmission gate. (April 2011)
15. (i) Compare the sequencing in traditional domino and skew tolerant domino circuits
with neat diagrams. (10) (Nov-2011)
(ii) Write the basic principle of low power logic design. (6)
Unit-4
Part-A
1. What is the need for testing? ( April 2014)
2. What do you mean by test fixtures? ( April 2014)
3. What is Tester, Test Fixture and Handler? (Nov 2014)
4. Mention the different types of CMOS testing techniques. (Nov 2014)
5. List the basic types of CMOS testing. (May 2013)
6. What is meant by logic verification? (May 2013)
7. What is the need for testing? (Nov 2013)
8. What is the principle behind logic verification? (Nov 2013)
9. What are the factors that cause timing failures? (May 2012)
10. What are the advantages of single stuck-at fault? (May 2012)
11. Distinguish testers and test fixtures. (Nov 2012)
12. What are the stages at which a chip can be tested? (Nov 2012)
13. Write a note on partition and MUX technique. (April 2011)
14. List the design guidelines for IDDQ testing. (April 2011)
15. State the objective of functionality test. (Nov 2011)
16. What are the test fixtures required to test a chip? (Nov 2011)
Part-B
1. Discuss the need for testing and explain about the silicon debugging principles. ( April
2014)
2. Explain the method of boundary scan test in detail. (April 2014)

6. 3. (i) List the manufacturing test principles and explain them. (8)
(ii) Explain Built-in Self-Test. (8) (Nov 2014)
4. (i) Discuss on the Test Logic architecture and test access port. (8)
(ii)Explain on the scan design strategy of testing. (8) (Nov 2014)
5. Explain the design for testability (DFT) concepts. (May 2013)
6. Explain the following (i) Silicon debug principles (ii) Boundary scan techniques.(May
2013)
7. Describe in detail, the various manufacturing test in CMOS testing. (Nov 2013)
8. Explain in detail boundary scan testing. (Nov 2013)
9. (i) Explain in detail about partition and MUX testing with necessary diagram. (8)
(ii) Explain the principle of silicon debug.(8) (May 2012)
10. (i) Elaborate the scan based techniques.(8) (May 2012)
(ii) Discuss in detail about a) pseudo random pattern generator b) Output response
analyser. (May 2012)
11. Explain the following (i) silicon debug principles (ii) Fault models. (Nov 2012)
12. (i) Describe the principle and applications of built-in self test. (12) (Nov 2012)
(ii) Explain how to detect a stuck at fault with example. (4)
13. Explain in detail the sequence of Scan-based technique. (April 2011)
14. (i) What is main purpose of test bench?
(ii) With the essential circuit modules, explain in detail the BIST technique. (April 2011)
15. Explain the manufacturing test principles in detail. (Nov-2011)
16. Describe the adhoc testing and scan based approaches to design for testability in detail.
(Nov-2011)
Unit- 5
Part-A
1. What are procedural assignments in verilog? ( April 2014)
2. What is a switch level modeling? ( April 2014)
3. State the format for procedural assignment in verilog. (Nov 2014)
4. What is RTL modeling in verilog? (Nov 2014)
5. Give the comparison between structural and switch level modeling. (May 2013)
6. What are Gate primitives? (May 2013)
7. Differentiate blocking and non-blocking assignments. (Nov 2013)
8. Mention the possible values which are allowed in verilog HDL. (Nov 2013)
9. With component instantiation, write a VHDL program for a half-adder. (May 2012)
10. Write a note on transport delay. (May 2012)
11. Write the verilog module for a 1 bit full adder. (Nov 2012)
12. Give an example for implicit continuous assignment. (Nov 2012)
13. What is transport delay model? (April 2011)
14. What is Sub program overloading? (April 2011)
15. Write the verilog module for an half –adder. (Nov 2011)
16. What are the delay specifications available in verilog HDL for modeling a logic gate?
(Nov 2011)

7. Part-B
1. Explain the following in verilog with a suitable example (i) Timing controls and
conditional statements. (ii) behavioral and Gate level modeling. ( April 2014)
2. Write the verilog code for (i) priority encoder (ii) Equality detector. ( April 2014)
3. (i) Explain the verilog Gate Primitives along with their function maps. (8) (Nov 2014)
(ii) Write the verilog description for NAND latch with time delay of 2 units for each
NAND gates. (8)
4. (i) Explain blocking and non-blocking assignments in verilog with examples. (8)
(ii) Illustrate in verilog the construction of 4 input multiplexer from three 2 input
multiplexers. (8) (Nov 2014)
5. Design and develop the HDL project to realize the function of a priority encoder using
structural model. (May 2013)
6. (i) Write a data-flow model verilog HDL program for the two input comparator circuit.
(8) (May 2013)
(ii) Write a behavioral level verilog HDL program for the 1x8 multiplexer circuits.
7. Write a Verilog HDL for an 8-bit Ripple carry adder using structural model. (Nov 2013)
8. Write a Verilog HDL for a positive edge-triggered D flip- flop. Using that implement an
8-bit shift register in structural model. (Nov 2013)
9. Using mixed level mode write a VHDL program for a (i) comparator (ii) D flip flop.
(May 2012)
10. With all the 3 types of modeling, write a VHDL program for a (i) Decoder (ii) Full adder.
(May 2012)
11. (i) Draw an active high 2/4 decoder using NOR gates and write the verilog gate level
description.(Nov 2012)
(ii) Describe the three ways of specifying delays in continuous assignment statements.
12. (i) Write the data flow modeling for a 4 to 1 MUX using verilog HDL. (Nov 2012)
(ii) Explain the different timing controls available in verilog HDL.
13. (i) How is component instantiations found? Explain it using a one-bit full adder circuit?
(ii) What is incremental binding Explain with an example. (5)
(iii) Explain Gate level modeling with a suitable example. (April 2011)
14. (i) Write a note on waveform generation? (April 2011)
(ii) Write VHDL coding for a decoder circuit in data flow model, behavioral model.
15. (i) Draw the 3 input CMOS NOR and NAND gates and write the verilog switch level
modeling for both. (10) (Nov-2011)
(ii) Explain the continuous and implicit continuous assignment with two suitable
examples for each. (6)
16. (i) Draw the logic diagram of a 4 to 1 MUX using NAND gates and write the gate level
modeling using verilog HDL. (8) (Nov-2011)
(ii) Give a brief note on the looping statements available in verilog HDL and write a
verilog code for D latch. (8)