Three-dimensional (3D) VLSI provides advantages over traditional two-dimensional (2D) VLSI by reducing chip size, power consumption, and signal delay through shorter, more direct interconnects between functional blocks stacked in three dimensions. While 3D VLSI faces challenges such as thermal management and difficulties in design and fabrication, its potential to continue increasing circuit density and transistor counts as predicted by Moore's Law makes it a promising long-term solution as 2D approaches its physical scaling limits.

1. Three-dimensional VLSI Matthew Johnson Seminar: Engineering Frontiers March 7, 2001

2. Contents Traditional (2D) VLSI origins scientific background manufacturing process 3D VLSI origins advantages over 2D VLSI challenges solutions

3. Contents Influential participants Marketing information Impact societal semiconductor industry

4. VLSI Very Large Scale Integration design/manufacturing of extremely small, complex circuitry using modified semiconductor material integrated circuit (IC) may contain millions of transistors, each a few  m in size applications wide ranging: most electronic logic devices

5. Origins of VLSI Much development motivated by WWII need for improved electronics, especially for radar 1940 - Russell Ohl (Bell Laboratories) - first p-n junction 1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - first transistor 1956 Nobel Physics Prize Late 1950s - purification of Si advances to acceptable levels for use in electronics 1958 - Seymour Cray (Control Data Corporation) - first transistorized computer - CDC 1604

6. Origins of VLSI 1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components on 9 mm 2 1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated circuit 1968 - Noyce, Gordon E. Moore found Intel 1971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300 transistors on 9 mm 2 Since then - continued improvement in technology has allowed for increased performance as predicted by Moore’s Law

7. Moore’s Law Gordon E. Moore - Chairman Emeritus of Intel Corporation 1965 - observed trends in industry - number of transistors on ICs vs. release dates Noticed number of transistors doubling with release of each new IC generation release dates (separate generations) were all 18-24 months apart Moore’s Law - The number of transistors on an integrated circuit will double every 18 months Semiconductor industry has followed this prediction with surprising accuracy

8. Moore’s Law From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond Relative sizes of ICs in graph

9. Limits of Moore’s Law? Growth expected until 30 nm gate length (currently: 180 nm) size halved every 18 mos. - reached in 2001 + 1.5 log 2 ((180/30) 2 ) = 2009 what then? Paradigm shift needed in fabrication process

10. Scientific principles Semiconductors Crystalline solids Impurities element groups n-type material p-type material p-n junctions

11. Semiconductors A material whose properties are such that it is not quite a conductor, not quite an insulator Some common semiconductors elemental Si - Silicon (most common) Ge - Germanium compound GaAs - Gallium arsenide GaP - Gallium phosphide AlAs - Aluminum arsenide AlP - Aluminum phosphide InP - Indium Phosphide

12. Crystalline Solids “ In a crystalline solid, the periodic arrangement of atoms… is repeated over the entire crystal.” [Bhatt] Silicon crystal - “diamond lattice”

13. Impurities Silicon crystal in pure form is good insulator - all electrons are bonded to silicon atom Replacement of Si atoms can alter electrical properties of semiconductor Group number - indicates number of electrons in valence level (Si - Group IV)

14. Impurities Replace Si atom in crystal with Group V atom substitution of 5 electrons for 4 electrons in outer shell extra electron not needed for crystal bonding structure can move to other areas of semiconductor current flows more easily - resistivity decreases many extra electrons --> “donor” or n-type material Replace Si atom with Group III atom substitution of 3 electrons for 4 electrons extra electron now needed for crystal bonding structure “ hole” created (missing electron) hole can move to other areas of semiconductor if electrons continually fill holes again, current flows more easily - resistivity decreases electrons needed --> “acceptor” or p-type material

15. P-N Junction Also known as a diode One of the basics of semiconductor technology - Created by placing n-type and p-type material in close contact Diffusion - mobile charges (holes) in p-type combine with mobile charges (electrons) in n-type

16. P-N Junction Region of charges left behind (dopants fixed in crystal lattice) Group III in p-type (one less proton than Si- negative charge) Group IV in n-type (one more proton than Si - positive charge) Region is totally depleted of mobile charges - “depletion region” Electric field forms due to fixed charges in the depletion region Depletion region has high resistance due to lack of mobile charges

17. P-N Junction Reverse bias: positive voltage placed on n-type material electrons in n-type move closer to positive terminal, holes in p-type move closer to negative terminal width of depletion region increases allowed current is essentially zero (small “drift” current)

18. P-N Junction Forward bias: positive voltage placed on p-type material holes in p-type move away from positive terminal, electrons in n-type move further from negative terminal depletion region becomes smaller - resistance of device decreases voltage increased until critical voltage is reached, depletion region disappears, current can flow freely

19. P-N Junction - V-I characteristics Voltage-Current relationship for a p-n junction (diode)

20. Manufacturing Crystal growth Photolithography (masks, patterning) Doping Packaging/assembly Manufacturing environment

21. Crystal Growth Czochralski method Silicon must be crystal to be used in ICs Crystal growth - the process of creating crystalline silicon Seed crystal (solid piece of crystalline silicon) “brought into contact with the surface of the same material in liquid phase, and then pulled slowly from the melt” [Neaman] Liquid cools, solidifies following crystal form

22. Crystal Growth Ingot cut to uniform diameter, then sliced into wafers Wafers machined into uniformed thickness Chemically and mechanically smoothed during “lapping” and “polishing” phases Completed silicon wafer is known as the substrate material Unmodified ingots

23. Photolithography Lithography - process of applying circuitry patterns to substrate Photolithography - most common lithography technique wafer covered with photoresist (light sensitive chemical) light shown through a mask onto the photoresist coating exposure to light alters properties of photoresist (“hardening”), giving it resistance to certain chemicals non-hardened photoresist washed away allows for patterns of insulation (SiO 2 ), interconnection (Al), or doping many masks/photolithography steps used for complex circuits

24. Doping “ The technique of adding impurity atoms (dopants) to a semiconductor in order to alter its conductivity” [Neamen] Ratio of Si atoms to dopant atoms ranges from 10 4 :1 to 10 9 :1 low level of impurity has large impact on conductivity of substrate Impurity diffusion substrate placed in high temp. (~1000 C) gaseous atmosphere temp. lowered, impurities remain Ion implantation beam of impurity ions accelerated to high energy, directed at surface of substrate

25. Testing/Packaging Each circuit on wafer tested, then cut apart Circuits are encapsulated in plastic or ceramic molding, retested Packages created with leads that allow IC to be attached to printed circuit board

26. Three Dimensional VLSI The fabrication of a single integrated circuit whose functional parts (transistors, etc) extend in three dimensions The vertical orientation of several bare integrated circuits in a single package

27. Advantages of 3D VLSI Speed - the time required for a signal to travel between the functional circuit blocks in a system (delay) reduced. Delay depends on resistance/capacitance of interconnections resistance proportional to interconnection length

28. Advantages of 3D VLSI Noise - “unwanted disturbances on a useful signal” [Al-sarawi] reflection noise (varying impedance along interconnect) crosstalk noise (interference between interconnects) electromagnetic interference (EMI) (caused by current in pins) 3D chips fewer, shorter interconnects fewer pins

29. Advantages of 3D VLSI Power consumption power used charging an interconnect capacitance P = fCV 2 power dissipated through resistive material P = V 2 /R capacitance/resistance proportional to length reduced interconnect lengths will reduce power

30. Advantages of 3D VLSI Interconnect capacity (connectivity) more connections between chips increased functionality, ease of design

31. Advantages of 3D VLSI Printed circuit board size/weight planar size of PCB reduced with negligible IC height increase weight reduction due to more circuitry per package/smaller PCBs estimated 40-50 times reduction in size/weight

32. 3D VLSI - Challenges and Solutions Challenge: Thermal management smaller packages increased circuit density increased power density Solutions: circuit layout (design stage) high power sections uniformly distributed advancement in cooling techniques (heat pipes)

33. 3D VLSI - Challenges and Solutions Challenge: lack of software to deal with complexity of 3D development Solution: same as with increasing 2D complexity - design of improved software Challenge: industry’s resistance to change ($) Solution: time/research - if proven to be most promising way to continue Moore’s Law growth, investment will be made

34. Influential Participant - Academia Georgia Tech’s Low Cost Electronics Packaging Research Center $40 million facility headed by Dr. Rao R. Tummala former IBM semiconductor researcher goals: To carry out research, development and prototype manufacturing To transfer this knowledge to industry. To train future leaders in electronic package engineering

35. Influential Participants - Industry Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others... high density memories AT&T high density “multiprocessor” Many other applications/participants

36. Ball Semiconductor, Inc. Unique approach to 3D VLSI applying 2D VLSI technologies to surface of 1 mm sphere three-dimensional layout tool, called ABLE (Advanced Ball Layout Editor) traditional techniques for long rectangle adapted to spherical surface over 60% of surface covered

37. Ball Semiconductor, Inc. Computer Simulation

38. Ball Semiconductor, Inc Product Developed

39. Ball Semiconductor, Inc. Complex circuitry achieved with ball stacking “ Cubic VLSI by Clustering”

40. Market Electronics market - $668 billion 3D VLSI can influence market only with high quality products improved quality/low cost will sell Little immediate impact expected more research and small scale development needed expensive change of fabrication process required long time-to-market Long term impact - today’s will likely be leaders in any 3D IC sales 3D VLSI will not likely change semiconductor market, only what is sold

41. Impact - Society Performance improvements will occur even without 3D VLSI increased influence of computers, cell phones, other common electronic devices solution to possible Moore’s Law roadblock Size reductions drastic compared to 2D VLSI Public - ignorant of causes, observant of improvements

42. Impact Semiconductor Industry 3D VLSI requires major paradigm shift in industry Initial participants - large capital risk to modify fabrication process Success of one company will require shift in industry as a whole (competition) ECE/CS improvements in hardware open software and application possibilities

43. Three Dimensional VLSI Moore’s Law approaching physical limit Increased performance expected by market Paradigm shift needed - 3D VLSI many advantages over 2D VLSI economic limitations of fabrication overhaul will be overcome by market demand Three Dimensional VLSI may be the savior of Moore’s Law

44. End