4. 4
Growth Rate
• 53% compound annual growth rate over 50
years
– No other technology has grown so fast so long
• Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society
[Moore65]
Electronics Magazine
5. 5
Annual Sales
• >1019 transistors manufactured in 2008
– 1 billion for every human on the planet
6. 6
Invention of the Transistor
• Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable
• 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– See Crystal Fire
by Riordan, Hoddeson
AT&T Archives.
Reprinted with
permission.
7. 7
Transistor Types
• Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls large
currents between emitter and collector
– Base currents limit integration density
• Metal Oxide Semiconductor Field Effect
Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration
9. 9
Moore’s Law: Then
• 1965: Gordon Moore plotted transistor on
each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine
13. 13
Introduction
• Integrated circuits: many transistors on one chip.
• Very Large Scale Integration (VLSI): bucketloads!
• Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
• Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
• Rest of the course: How to build a good CMOS
chip
14. 14
Silicon Lattice
• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four
neighbors
Si Si
Si
Si Si
Si
Si Si
Si
15. 15
Dopants
• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts
poorly
• Adding dopants increases the conductivity
• Group V: extra electron (n-type)
• Group III: missing electron, called hole (p-
type)
As Si
Si
Si Si
Si
Si Si
Si
B Si
Si
Si Si
Si
Si Si
Si
-
+
+
-
16. 16
p-n Junctions
• A junction between p-type and n-type
semiconductor forms a diode.
• Current flows only in one direction
p-type n-type
anode cathode
17. 17
nMOS Transistor
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
– Even though gate is
no longer made of metal*
* Metal gates are returning today!
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
Body
18. 0: Introduction 18
nMOS Operation
• Body is usually tied to ground (0 V)
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
19. 19
nMOS Operation Cont.
• When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
20. 20
pMOS Transistor
• Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
SiO2
n
Gate
Source Drain
bulk Si
Polysilicon
p+ p+
21. 21
Power Supply Voltage
• GND = 0 V
• In 1980’s, VDD = 5V
• VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
22. 22
Transistors as Switches
• We can view MOS transistors as electrically
controlled switches
• Voltage at gate controls path from source to
drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
29. 29
3-input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0
A
B
Y
C
30. 30
CMOS Fabrication
• CMOS transistors are fabricated on silicon
wafer
• Lithography process similar to printing press
• On each step, different materials are
deposited or etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
31. 31
Inverter Cross-section
• Typically use p-type substrate for nMOS
transistors
• Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
32. 32
Well and Substrate Taps
• Substrate must be tied to GND and n-well to
VDD
• Metal to lightly-doped semiconductor forms
poor connection called Shottky Diode
• Use heavily doped well and substrate contacts
/ taps
n+
p substrate
p+
n well
A
Y
GND VDD
n+
p+
substrate tap
well
tap
n+ p+
33. 33
Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
34. 34
Detailed Mask Views
• Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
35. 35
Fabrication
• Chips are built in huge factories called fabs
• Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
36. 36
Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
37. 37
Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
38. 38
Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
p substrate
SiO2
Photoresist
40. 40
Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been
exposed
p substrate
SiO2
Photoresist
41. 41
Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step
p substrate
SiO2
42. 42
n-well
• n-well is formed with diffusion or ion
implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2
43. 43
Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of
steps
p substrate
n well
44. 44
Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon
layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well
45. 45
Polysilicon Patterning
• Use same lithography process to pattern
polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
46. 46
Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-
well contact
p substrate
n well
47. 47
N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks
diffusion
• Polysilicon is better than metal for self-aligned
gates because it doesn’t melt during later
processing
p substrate
n well
n+ Diffusion
48. 48
N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion
n well
p substrate
n+
n+ n+
50. 50
P-Diffusion
• Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p substrate
n well
n+
n+ n+
p+
p+
p+
51. 51
Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Contact
52. 52
Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal
53. 53
Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
• Feature size f = distance between source and drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules
• Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
55. 55
Inverter Layout
• Transistor dimensions specified as Width /
Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long
56. 56
Summary
• MOS transistors are stacks of gate, oxide, silicon
• Act as electrically controlled switches
• Build logic gates out of switches
• Draw masks to specify layout of transistors
• Now you know everything necessary to start
designing schematics and layout for a simple
chip!
58. 58
Complementary CMOS
• Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
– a.k.a. static CMOS
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
59. 59
Series and Parallel
• nMOS: 1 = ON
• pMOS: 0 = ON
• Series: both must be ON
• Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
1
1 0 1
a
b
0 0
a
b
0
a
b
1
a
b
1
1 0 1
a
b
g1 g2
60. 60
Conduction Complement
• Complementary CMOS gates always produce 0 or
1
• Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS
• Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
A
B
Y
61. 61
Compound Gates
• Compound gates can do any inverting function
• Ex: (AND-AND-OR-INVERT, AOI22)
Y A B C D
A
B
C
D
A
B
C
D
A B C D
A B
C D
B
D
Y
A
C
A
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
63. 63
Signal Strength
• Strength of signal
– How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• nMOS pass strong 0
– But degraded or weak 1
• pMOS pass strong 1
– But degraded or weak 0
• Thus nMOS are best for pull-down network
64. 64
Pass Transistors
• Transistors can be used as switches
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
1
g
s d
g
s d
65. 65
Transmission Gates
• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
68. 68
Tristate Inverter
• Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN
70. 70
Gate-Level Mux Design
•
• How many transistors are needed? 20
1 0 (too many transistors)
Y SD SD
4
4
D1
D0
S Y
4
2
2
2 Y
2
D1
D0
S
71. 71
Transmission Gate Mux
• Nonrestoring mux uses two transmission gates
– Only 4 transistors S
S
D0
D1
Y
S
72. 72
Inverting Mux
• Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
• Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S
73. 73
4:1 Multiplexer
• 4:1 mux chooses one of 4 inputs using two
selects
– Two levels of 2:1 muxes
– Or four tristates
S0
D0
D1
0
1
0
1
0
1
Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
74. 74
D Latch
• When CLK = 1, latch is transparent
– D flows through to Q like a buffer
• When CLK = 0, the latch is opaque
– Q holds its old value independent of D
• a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latch
D
CLK
Q
75. 75
D Latch Design
• Multiplexer chooses D or old Q
1
0
D
CLK
Q
CLK
CLK
CLK
CLK
D
Q Q
Q
77. 77
D Flip-flop
• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop
Flop
CLK
D Q
D
CLK
Q
78. 78
D Flip-flop Design
• Built from master and slave D latches
QM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latch
Latch
D Q
QM
CLK
CLK
80. 80
Race Condition
• Back-to-back flops can malfunction from clock
skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
D
Q1
Flop
Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2
81. 81
Nonoverlapping Clocks
• Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
• We will use them in this class for safe design
– Industry manages skew more carefully instead
1
1
1
1
2
2
2
2
2
1
QM
Q
D
82. 82
Gate Layout
• Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
• Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
83. Engineered for Tomorrow
MOS circuits are formed on four basic layers:
N-diffusion
P-diffusion
Polysilicon
Metal
•These layers are isolated by one another by thick or thin silicon dioxide insulating
layers.
•Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.
MOS layers
84. Stick diagrams
• Stick diagrams may be used to convey layer information through the use
of a color code.
• For example:
n-diffusion --green
poly -- red
blue -- metal
yellow --implant
black --contact areas
97. 97
Example: NAND3
• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 VDD rail at top
• Metal1 GND rail at bottom
• 32 l by 40 l
98. 98
Stick Diagrams
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
c
A
VDD
GND
Y
A
VDD
GND
B C
Y
INV
metal1
poly
ndiff
pdiff
contact
NAND3
99. 99
Wiring Tracks
• A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
• Transistors also consume one wiring track
100. 100
Well spacing
• Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
101. 101
32 l
40 l
Area Estimation
• Estimate area by counting wiring tracks
– Multiply by 8 to express in l
102. 102
Example: O3AI
• Sketch a stick diagram for O3AI and estimate area
–
Y A B C D
A
VDD
GND
B C
Y
D
6 tracks =
48 l
5 tracks =
40 l
105. 105
Coping with Complexity
• How to design System-on-Chip?
– Many millions (even billions!) of transistors
– Tens to hundreds of engineers
• Structured Design
• Design Partitioning
106. 106
Structured Design
• Hierarchy: Divide and Conquer
– Recursively system into modules
• Regularity
– Reuse modules wherever possible
– Ex: Standard cell library
• Modularity: well-formed interfaces
– Allows modules to be treated as black boxes
• Locality
– Physical and temporal
107. 107
Design Partitioning
• Architecture: User’s perspective, what does it
do?
– Instruction set, registers
– MIPS, x86, Alpha, PIC, ARM, …
• Microarchitecture
– Single cycle, multcycle, pipelined, superscalar?
• Logic: how are functional blocks constructed
– Ripple carry, carry lookahead, carry select adders
• Circuit: how are transistors used
– Complementary CMOS, pass transistors, domino
• Physical: chip layout
– Datapaths, memories, random logic
109. 109
MIPS Architecture
• Example: subset of MIPS processor architecture
– Drawn from Patterson & Hennessy
• MIPS is a 32-bit architecture with 32 registers
– Consider 8-bit subset using 8-bit datapath
– Only implement 8 registers ($0 - $7)
– $0 hardwired to 00000000
– 8-bit program counter
• You’ll build this processor in the labs
– Illustrate the key concepts in VLSI design
111. 111
Instruction Encoding
• 32-bit instruction encoding
– Requires four cycles to fetch on 8-bit datapath
format example encoding
R
I
J
0 ra rb rd 0 funct
op
op
ra rb imm
6
6
6
6
5 5 5 5
5 5 16
26
add $rd, $ra, $rb
beq $ra, $rb, imm
j dest dest
114. 114
Fibonacci (Binary)
• 1st statement: addi $3, $0, 8
• How do we translate this to machine
language?
– Hint: use instruction encodings below
format example encoding
R
I
J
0 ra rb rd 0 funct
op
op
ra rb imm
6
6
6
6
5 5 5 5
5 5 16
26
add $rd, $ra, $rb
beq $ra, $rb, imm
j dest dest
121. 121
HDLs
• Hardware Description Languages
– Widely used in logic design
– Verilog and VHDL
• Describe hardware using code
– Document logic functions
– Simulate logic before building
– Synthesize code into gates and layout
• Requires a library of standard cells
122. 122
Verilog Example
module fulladder(input a, b, c,
output s, cout);
sum s1(a, b, c, s);
carry c1(a, b, c, cout);
endmodule
module carry(input a, b, c,
output cout)
assign cout = (a&b) | (a&c) | (b&c);
endmodule
a b
c
s
cout carry
sum
s
a b c
cout
fulladder
123. 123
Circuit Design
• How should logic be implemented?
– NANDs and NORs vs. ANDs and ORs?
– Fan-in and fan-out?
– How wide should transistors be?
• These choices affect speed, area, power
• Logic synthesis makes these choices for you
– Good enough for many applications
– Hand-crafted circuits are still better
124. 124
Example: Carry Logic
• assign cout = (a&b) | (a&c) | (b&c);
a
b
a
c
b
c
cout
x
y
z
g1
g2
g3
g4
Transistors? Gate Delays?
a b
c
c
a b
b
a
a
b
cout
cn
n1 n2
n3
n4
n5 n6
p6
p5
p4
p3
p2
p1
i1
i3
i2
i4
125. 125
Gate-level Netlist
module carry(input a, b, c,
output cout)
wire x, y, z;
and g1(x, a, b);
and g2(y, a, c);
and g3(z, b, c);
or g4(cout, x, y, z);
endmodule
a
b
a
c
b
c
cout
x
y
z
g1
g2
g3
g4
126. 126
Transistor-Level Netlist
a b
c
c
a b
b
a
a
b
cout
cn
n1 n2
n3
n4
n5 n6
p6
p5
p4
p3
p2
p1
i1
i3
i2
i4
module carry(input a, b, c,
output cout)
wire i1, i2, i3, i4, cn;
tranif1 n1(i1, 0, a);
tranif1 n2(i1, 0, b);
tranif1 n3(cn, i1, c);
tranif1 n4(i2, 0, b);
tranif1 n5(cn, i2, a);
tranif0 p1(i3, 1, a);
tranif0 p2(i3, 1, b);
tranif0 p3(cn, i3, c);
tranif0 p4(i4, 1, b);
tranif0 p5(cn, i4, a);
tranif1 n6(cout, 0, cn);
tranif0 p6(cout, 1, cn);
endmodule
127. 127
SPICE Netlist
.SUBCKT CARRY A B C COUT VDD GND
MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P
MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P
MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P
MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P
MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P
MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P
MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P
MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P
MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P
MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P
CI1 I1 GND 2FF
CI3 I3 GND 3FF
CA A GND 4FF
CB B GND 4FF
CC C GND 2FF
CCN CN GND 4FF
CCOUT COUT GND 2FF
.ENDS
133. 133
Pitch Matching
• Synthesized controller area is mostly wires
– Design is smaller if wires run through/over cells
– Smaller = faster, lower power as well!
• Design snap-together cells for datapaths and
arrays
– Plan wires into cells
– Connect by abutment
• Exploits locality
• Takes lots of effort
A A A A
A A A A
A A A A
A A A A
B
B
B
B
C C D
134. 134
MIPS Datapath
• 8-bit datapath built from 8 bitslices
(regularity)
• Zipper at top drives control signals to datapath
135. 135
Slice Plans
• Slice plan for bitslice
– Cell ordering, dimensions, wiring tracks
– Arrange cells for wiring locality
136. 136
Area Estimation
• Need area estimates to make floorplan
– Compare to another block you already designed
– Or estimate from transistor counts
– Budget room for large wiring tracks
– Your mileage may vary; derate by 2x for class.
137. 137
Design Verification
• Fabrication is slow & expensive
– MOSIS 0.6mm: $1000, 3 months
– 65 nm: $3M, 1 month
• Debugging chips is very hard
– Limited visibility into operation
• Prove design is right before building!
– Logic simulation
– Ckt. simulation / formal verification
– Layout vs. schematic comparison
– Design & electrical rule checks
• Verification is > 50% of effort on most chips!
Specification
Architecture
Design
Logic
Design
Circuit
Design
Physical
Design
=
=
=
=
Function
Function
Function
Function
Timing
Power
138. 138
Fabrication & Packaging
• Tapeout final layout
• Fabrication
– 6, 8, 12” wafers
– Optimized for throughput,
not latency (10 weeks!)
– Cut into individual dice
• Packaging
– Bond gold wires from die I/O pads to package
139. 139
Testing
• Test that chip operates
– Design errors
– Manufacturing errors
• A single dust particle or wafer defect kills a die
– Yields from 90% to < 10%
– Depends on die size, maturity of process
– Test each part before shipping to customer
