Microelectronics Basics

ECCDLO 5011 MICROELECTRONICS
ECCDLO 5011
Microelectronics
BY
Prof. Abhishek Ajit Kadam
Email id: kadam.abhishek@siesgst.ac.in
Mob No: 9730032260
14-11-2018
SIES GST, Electronics & Tele Communication Department 1

Syllabus
14-11-2018

Course Outcome
1. Define basic fabrication process of MOS Transistors.
2. Analyse MOS characteristics and Second order
effects in MOS Transistors.
3. Understand Integrated circuit biasing using MOSFET.
4. Design and implement active load MOS amplifier.
5. Design and implement active load differential
amplifier
6. To understand implementation of passive
components in ICs.
14-11-2018

Text Books
• A. Sedra, K. Smith, adapted by A. Chandorkar “Microelectronic
Circuits-Theory and Application”
• D. Neamen, “Electronic Circuits Analysis and Design” , McGraw Hill
Education, 3rd Edition
• B. Razavi, “Design of Analog Integrated Circuits”, McGraw Hill
Education, Indian Edition
• ***B. Razavi, “Microelectronics”, Wiley India
• B. Razavi, “R F Microelectronics”, Pearson Publication, 2nd Edition
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ECCDLO 5011 MICROELECTRONICS14-11-2018

Chronology
Austro-Hungarian physicist, Julius E. Lilienfeld, moved to the US and in 1926
filed a patent for a “Method and Apparatus for Controlling Electric Currents”
in which he described a three-electrode amplifying device
using copper-sulfide semiconductor material.

• Because of their poor reliability and large power consumption, by the late 1930’s engineers at
American Telephone and Telegraph knew that vacuum-tube circuits would not meet the
company’s rapidly growing demand for increased phone call capacity.
• Using improved semiconductor materials developed for radar detectors during the war, in early
1945 Shockley experimented with a field-effect amplifier, similar in concept to those patented
by Heil and Lilienfeld, but it failed to work as he intended.
• Physicist John Bardeen suggested that electrons on the semiconductor surface might be
blocking penetration of electric fields into the material.
• Under Shockley’s direction, together with physicist Walter Brattain, Bardeen began researching
the behavior of these “surface states.”
• On December 16, 1947, their research culminated in a successful semiconductor amplifier.
Bardeen and Brattain applied two closely-spaced gold contacts held in place by a plastic wedge
to the surface of a small slab of high-purity germanium. On December 23 they demonstrated
their device to lab officials and in June 1948, Bell Labs publicly announced the revolutionary
solid-state device they called a “transistor.”
• Realizing that the point-contact structure had serious limitations, and spurred by professional
jealousy as he resented not being involved with its discovery, Shockley worked alone to
conceive a more reliable and reproducible device. Introduced in 1952, Shockley’s bipolar
junction transistor, which was made from a solid piece of semiconductor material and no point
contacts, dominated the industry for the next 30 years.
Chronology

Chronology
John Bardeen, William Shockley and
Walter Brattain in 1948, Courtesy of Bell
Telephone Laboratories
First Point Contact Transistor

Chronology
The ideas of Lilienfeld and Heil and Shockley’s failed early experiments finally bore fruit
in 1959 when, working for Egyptian engineer Martin M. (John) Atalla on the study of
semiconductor surfaces at Bell Labs, Korean electrical engineer Dawon Kahng built
the first successful field-effect transistor (FET) comprising a sandwich of layers of
metal (M – gate), oxide (O – insulation), and silicon (S – semiconductor).
Martin M. Atalla (1924 – 2009),
Courtesy of the Atalla Family
Dawon Kahng (1931 – 1992),
Courtesy NEC Corporation

Voltage

Moor’s Law
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7)

Chapter 1
Basics of MOSFETs
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• Physics Of Semiconductor Devices (A review)
𝑁(𝐸) is Density of states
𝐹(𝐸) is Fermi Dirac Probability Function
𝑛𝑖 𝑎𝑛𝑑 𝑝𝑖 are intrinsic Carrier Concentration
𝑛 = 𝑁𝑐 𝐸 . 𝐹 𝐸 𝑑𝐸 𝑝 = 𝑁𝑣 𝐸 . 1 − 𝐹 𝐸 𝑑𝐸
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Insertion of Donor Impurity like Prosperous (P) or Arsenic (As)
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Insertion of Donor Impurity like Boron(B), Aluminium(Al) or Gallium (Ga)
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• P-N Junction
𝜓 𝑏𝑖 is Built in potential 0.7 V in Si
𝜙 𝑛 =
𝑘𝑇
𝑞
ln(𝑁 𝐷/𝑛𝑖) is difference
between 𝐸 𝐹 𝑎𝑛𝑑 𝐸𝑐
𝜙 𝑝 =
𝑘𝑇
𝑞
ln(𝑁𝐴/𝑛𝑖) is difference
between 𝐸 𝐹 𝑎𝑛𝑑 𝐸 𝑣
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• Energy Band Diagram of Ideal MIS structure (n type)
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• Energy Band Diagram of Ideal MIS structure (P type)
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Basic Building Block “MOSFET”
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Symbol
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MOSFET with gate voltage
formation of depletion region, formation of channel.

• Threshold Voltage
The semiconductor/oxide surface is inverted when VGS is greater than the
Threshold voltage (VTH). The threshold voltage VTH is given by
𝑉𝑇 = 𝑉𝑇𝐻0 + 𝛾( 2𝜙 𝐹 + 𝑉𝑆𝐵 − |2𝜙 𝐹|)
Where 𝑉𝑇𝐻0 = 𝜙 𝑀𝑆 + 2𝜙 𝐹 +
𝑄 𝑑𝑒𝑝
𝐶 𝑜𝑥
Where 𝜙 𝑀𝑆 is difference between work function of polysillicon gate and
substrate. It is given by
𝜙 𝐹 =
𝑘𝑇
𝑞
ln[
𝑁𝑠𝑢𝑏
𝑛𝑖
]
Where
𝑞 is charge on electron given by 𝑒 = 1.6 ∗ 10−19
𝑐𝑜𝑢𝑙𝑜𝑚𝑏𝑠
𝑁𝑠𝑢𝑏 is doping concentration
𝑄 𝑑𝑒𝑝 is Depletion region charge given by (4𝑒𝜖 𝑠𝑖 𝜙 𝐹 𝑁𝑠𝑢𝑏)
𝐶 𝑜𝑥 is oxide capacitance per unit area given by
𝜖 𝑠𝑖
𝑡 𝑜𝑥
𝛾 is called as Body coefficient given by
2𝑒𝜖 𝑠𝑖 𝑁 𝑠𝑢𝑏
𝐶 𝑜𝑥
14-11-2018

𝐼 𝐷 − 𝑉𝐺 𝑎𝑛𝑑 𝐼 𝐷 − 𝑉𝐷 𝑐ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑓𝑜𝑟 𝑐ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝐿𝑒𝑛𝑔𝑡ℎ
𝐼 𝐷 − 𝑉𝐺 𝑎𝑛𝑑 𝐼 𝐷 − 𝑉𝐷 𝑐ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑓𝑜𝑟 𝑐ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝑜𝑥𝑖𝑑𝑒 𝑇ℎ𝑖𝑐𝑘𝑛𝑒𝑠𝑠

Derivation of I/V characteristics

𝐼 𝑑 𝑣𝑠 𝑉𝑑𝑠 𝑐𝑢𝑟𝑣𝑒

Transistor operating in Deep Triode region 𝑉𝐷𝑆 ≪ (𝑉𝐺𝑆 − 𝑉𝑇)

Pinch off Behaviour

Find the region of operation if 𝑉𝑇 = 0.4V

MOS I-V Characteristics summery
SIES GST, Electronics & Tele Communication Department
• Triode Region
• Deep Triode Region
VDS ≪ 2(VGS − VT)
𝑅 𝑜𝑛 = 1/(𝜇 𝑛 𝐶 𝑜𝑥
𝑊
𝐿
𝑉𝐺𝑆 − 𝑉𝑇)
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46

MOS I-V Characteristics summery
•Saturation Region
When pinch off condition occurs
Further when device enters in Saturation region where Drain
current is given by
𝐼 𝐷 =
𝜇 𝑛 𝐶 𝑜𝑥
𝑊
𝐿
2
𝑉𝐺𝑆 − 𝑉𝑇
2
𝐼 𝐷 =
𝛽 𝑛
2
𝑉𝐺𝑆 − 𝑉𝑇
2 𝑎𝑛𝑑 𝑅 𝑜𝑛 = ∞
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47

Transconductance
Transconductance is defined as ratio of change in Id and Vgs
𝑔 𝑚 =
𝛿 𝐼 𝐷
𝛿(𝑉𝐺𝑆)
Where is referred as overdrive voltage
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48

• MOS Transconductance as function of 𝑉𝑜𝑣 & 𝐼 𝐷

MOSFET SCALING
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Moors Law

Types of scaling
• Constant Field Scaling or Full scaling
• Constant Voltage Scaling
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Constant Field Scaling
• Magnitude of internal electric fields is kept
constant.
• Only lateral dimensions are changed.
• Threshold voltage is also effected.
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Consequences of Constant Field Scaling
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Consequences of Constant Field Scaling
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• Most significant reduction :
– Power dissipation is reduced by a factor of S² as P´= P/S²
– Power density remains unchanged.
– Gate oxide capacitance is scaled down as Cg´ = Cg/S
– Overall performance improvement.

Constant Voltage Scaling :
• More preferred.
• All dimensions are scaled down except power supply
and terminal voltages.
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Cons of Constant Voltage Scaling :
• Increase in drain current density and power
density by a factor of S³ adversely effecting device
reliability.
• Causes problems like :
– Electro Migration
– Hot Carrier Degradation
– Gate Oxide Breakdown
– Electrical Over-stress
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• Scaling Trends

Consequences of Scaling
• Second order Effects
 Channel Length Modulation
 Body Effect
 CMOS Latch-up
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Consequences of Scaling
• Short Channel Effects
 Mobility Degradation
 Sub threshold Conduction
 Drain Induced Barrier Lowering
 Drain Punch Through
 Hot Carrier Effect
 Surface states and interface trapped charges
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Channel Length Modulation
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Output Dynamic resistance
Output dynamic resistance is defined as ratio of change in 𝑉𝐷𝑆 and 𝐼 𝑑
Where is Early voltage
Where is channel length modulation parameter
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64

Body Effect
• 𝑉𝑇 = 𝑉𝑇𝐻0 + 𝛾( 2𝜙 𝐹 + 𝑉𝑆𝐵 − |2𝜙 𝐹|)
• If negative 𝑉𝐵 is provided, holes are attracted towards substrate
connection leaving behind larger negative charge in form of Depletion
Region
• As 𝑉𝑇𝐻0 = 𝜙 𝑀𝑆 + 2𝜙 𝐹 +
𝑄 𝑑𝑒𝑝
𝐶 𝑜𝑥
thus as 𝑉𝐵 drops 𝑄 𝐷 increases thus 𝑉𝑇
increase.
• This effect is called as “Body Effect” or “Backgate Effect”
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Body trans-conductance (𝑔 𝑚𝑏)
• The substrate potential changes 𝑉𝑇 which causes
changes in 𝐼 𝐷. This dependence of 𝑉𝐵𝑆 on 𝐼 𝐷 is
given by Body Transconductance
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Thus

Velocity Saturation
• The electron velocity is related to the electric field
through the mobility: 𝑣 = −𝜇 𝑛 𝐸 = −𝜇 𝑛(
𝑑𝑉
𝑑𝑥
)
• For Long channel we assume the mobility 𝜇 𝑛 as a
constant, independent of the value of the electric
field Ε.
• At high electric field carriers fail to follow this
linear model. This is due to the velocity saturation
effect.
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Velocity Saturation
• When the electric field reaches a critical value 𝐸𝑐,
(1.5 𝜇𝑉/𝑚 for p-type silicon) the velocity of the
carriers tends to saturate (105
m/s for silicon) due
to scattering effects.
14-11-2018

Velocity Saturation
• Holes in a n-type silicon saturate at the same velocity,
although a higher electrical field is needed to achieve
saturation. Velocity-saturation effects are hence less
pronounced in PMOS transistors.
• The velocity as a function of the electrical field can be
approximated by following expression
• 𝑣 =
𝜇 𝑛 𝐸
1+𝐸/𝐸 𝐶
for 𝐸 ≤ 𝐸𝑐
• 𝑣 = 𝑣 𝑠𝑎𝑡 for 𝐸 ≥ 𝐸𝑐
• For a short-channel, device enters saturation before
𝑉𝐷𝑆 reaches 𝑉𝐺𝑆 − 𝑉𝑇. Short-channel devices
therefore experience an extended saturation.
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• The saturation current 𝐼 𝐷 𝑆𝐴𝑇 displays a linear dependence with
respect to the gate source voltage 𝑉𝐺𝑆, which is in contrast with the
squared dependence in the long channel device. This reduces the
amount of current a transistor can deliver for a given control
voltage.

Subthreshold Conduction
• We assume 𝐼 𝐷 = 0 for 𝑉𝐺𝑆 < 𝑉𝑇
• In reality the MOS transistor is already partially
conducting for voltages below the threshold voltage. This
effect is called subthreshold or weak-inversion
conduction.
• The transition from the on to the off condition is thus not
abrupt, but gradual.
• The current in this region can be approximated by the
expression
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14-11-2018
𝐼 𝐷 𝑣𝑠 𝑉𝐺𝑆 𝑜𝑛 𝐿𝑜𝑔𝑎𝑟𝑖𝑡ℎ𝑚𝑖𝑐 𝑆𝑐𝑎𝑙𝑒

14-11-2018
• The (inverse) rate of decline of the current with respect to
𝑉𝐺𝑆 below 𝑉𝑇 hence is a quality measure of a device. It is
often quantified by the slope factor (S)
• It measures by how much 𝑉𝐺𝑆 has to be reduced for the
drain current to drop by a factor of 10.
• 𝑆 = 𝑛
𝑘𝑇
𝑒
ln(10) is expressed in mV/decade
• For an ideal transistor with the sharpest possible roll off, n
= 1 and
𝑘𝑇
𝑒
ln(10) evaluates to 60 mV/decade at room
temperature
• For normal transistor it is 90 mV/decade

Drain Induced Barrier Lowering
• The source and drain depletion regions can intrude into the channel
even without Gate bias, as these junctions are brought closer
together in short channel devices. This effect is called charge
sharing since the source and drain in effect take part of the channel
charge, which would otherwise be controlled by the gate.
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Drain Induced Barrier Lowering
• As the drain depletion region continues to increase with
the bias, it can actually interact with the source to
channel junction and hence lowers the potential barrier.
This problem is known as Drain Induced Barrier Lowering
(DIBL). When the source junction barrier is reduced,
electrons are easily injected into the channel and the gate
voltage has no longer any control over the drain current.
• Due to DIBL, Threshold voltage of transistor lowers down.
• DIBL effect is reduced by decreasing the gate oxide
thickness. The thickness reduction makes the gate more
effective in controlling the channel region.
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Hot Carrier Effects
• During the last decades transistors dimensions were scaled
down, but not the power supply.
• The resulting increase in the electric field strength causes an
increasing energy of the electrons.
• Some electrons are able to leave the silicon and tunnel into
the gate oxide. Such electrons are called “Hot carriers”.
• Electrons trapped in the oxide change the 𝑉𝑇 of the
transistors. This leads to a long term reliability problem.
• For an electron to become hot an electric field of 104 V/cm
is necessary.
• This condition is easily met with channel lengths below
1μm.
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Hot Carrier Effects
14-11-2018
Changes in MOSFET Characteristics after running it for 100 min

Capacitance of MOS Devices
 Any two conductors separated by an insulator have capacitance
 Gate to channel capacitor is very important
 Creates channel charge necessary for operation (intrinsic
capacitance)
 Source and drain have capacitance to body (parasitic
capacitance)
 Across reverse-biased diodes
 Called diffusion capacitance because it is associated with
source/drain diffusion
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Gate Capacitance
 When the transistor is off, the channel is not
inverted
Cg = Cgb = ∈ 𝑜𝑥WL/tox = CoxWL
 Let’s call CoxWL = C0
 When the transistor is on, the channel extends
from the source to the drain (if the transistor is
unsaturated, or to the pinchoff point otherwise)
Cg = Cgb + Cgs + Cgd
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Gate Capacitance
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In reality the gate overlaps source and drain. Thus, the gate capacitance should include
not only the intrinsic capacitance but also parasitic overlap capacitances:
Cgs(overlap) = Cox W LD
Cgs(overlap) = Cox W LD

Gate Capacitance
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Capacitances in n-MOSFET
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85

Small Signal Model of n-MOSFET
Basic Model
Channel Length Modulation represented by dependent current source /
resistor
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86

Small Signal Model of n-MOSFET
Body effect represented by dependent current source .
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87

Complete Small Signal Model
of n-MOSFET
Considering various parasitic capacitances.
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88

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