Looking for Full-time opportunities after graduation in December'19. Interested in Hardware Engineer roles and Embedded Systems roles. Experienced in Computer Architecture, Embedded Systems, Digital Design, Digital Testing and Design Verification.

1. Shubhankar Anil Pawade
spawade@andrew.cmu.edu | 412-320-9137 | www.linkedin.com/in/shubhankarpawade | Full-Time
EDUCATION
Carnegie Mellon University December 2019
Master of Science in Electrical and Computer Engineering GPA: 3.78/4
Selected Coursework: Modern Computer Architecture (18740), Digital Systems Testing and Testable Design (18765), Real-time
Embedded Systems (18648), Hardware Security (18632), ULSI Technology (18664), How to write fast code (18645)
Birla Institute of Technology and Science, Pilani May 2018
Bachelor of Engineering (Honors) in Electronics and Instrumentation GPA: 9.04/10
Selected Coursework: Computer Architecture, Analog and Digital VLSI Design, Analog Electronics, Embedded Systems Design
SKILLS
Programming Languages –C, Verilog, System Verilog (Beginner), CUDA, OPENMP, Hadoop (Map-Reduce), Python, Bash
Application Software – Gem5, McPAT, RAMULATOR, MATLAB, Cadence Virtuoso, Eagle
PROFESSIONAL EXPERIENCE
NVIDIA Graphics Pvt. Ltd. Bangalore, India
GPU Design Verification Intern July-December 2017
• Assisted in memory management unit verification by resolving bugs for GPU fullchip using System Verilog test cases
• Developed an audio-controller transactor using Verilog for performance analysis of GPU units
• Aided in development of reset checker for validation of proper functioning of all reset signals in system
ACADEMIC PROJECTS
Carnegie Mellon University Pittsburgh, PA
Impact of various Branch Predictors on Processor Performance using Gem5 Simulator Fall 2019
• Designed and implemented global history, local history, tournament and perceptron-based branch predictors with
prediction accuracy greater than 95%
• Evaluated branch predictors for its accuracy, performance impact and energy using SPEC benchmarks
Design space exploration of Superscalar Out-of-Order processors in Gem5 and McPAT
• Explored the relationship between queues(Issue, Load, Store), ROB and their impact on performance, power and energy
• Designed and synthesized Reorder Buffer (ROB) and Issue Queue in System Verilog to find the target frequency
Fault Collapser and Imply Check Routine for SSL ATPG System Fall 2019
• Developed fault collapser that derives equivalence and dominance relationships among SSL Faults
• Implemented imply and check routine used in test generation algorithms like D-Algorithm, PODEM, FAN etc
Software Managed Memory Access Reorder Buffer (Research Project – Prof. James Hoe) May 2019-Present
• Setting up software infrastructure to access Sparse memory addresses by row-buffer locality to minimize row-buffer misses
• Having helper threads to achieve computation and memory accesses simultaneously with prefetching capabilities
K-means clustering algorithm and AES encryption using CUDA programming on NVIDIA’s GTX 1080 Spring 2019
• Achieved 6x speedup for AES encryption of large files and 10x speedup for k-means clustering algorithm
• Targeted optimizations to improve memory throughput by use of shared memory of the GPU, launching multiple blocks of
threads depending on cluster/block size and optimizing memory copies between host and device
SoC Design for Interactive Touchscreen Projector Fall 2018
• Evaluated trade-offs of choosing Technology node, memory hierarchy, GPU, CPU organization and thermal considerations
• Executed performance simulations on McPAT and memory simulations on Sniper (Cache) and Ramulator
Developed a real-time kernel capable of admission control, task scheduling and synchronization Fall 2018
• Implemented context swap with IRQ interrupts by storing context in TCB and scheduled tasks through RMS scheduling
• Added support for Mutexes and Highest Locker Priority (HLP)
Birla Institute of Technology and Science, Pilani Goa, India
16-bit CISC and RISC Processor Spring 2018
• Built a 5-stage pipelined CISC and RISC processor with dynamic detection of data and control hazards in Verilog
• Executed instructions with forwarding and stalling mechanism and various addressing modes for CISC processor
TEACHING ASSISTANTSHIP – Modern Computer Architecture (Course Dev - Summer 2019), ULSI Technology (Fall 2019)