1. 1138 west 27th
street
Los Angeles CA 90007 HARI KRISHNA VETSA
(667) 228-7354
vetsa@usc.edu
2 Years’ Experience in RTL Design
SUMMARY
 Over 2 years of experience in RTL Design, involved in timing analysis, verification, testing, debugging, and Logic
minimization.
 Sound Knowledge in Tomasulo Processor (Out of Order Execution), PCI, UART, AXI4 Protocol, SPI Protocol, I2C
Protocol, Cache Coherency, DDR3, Slack Borrowing, Time Stealing, Non Linear Pipeline, Wave Pipelining, Timing
Analysis.
 Sound knowledge in ATPG (D-algorithm, PODEM), Deductive Fault Simulation, Parallel Fault Simulation.
 Worked on various Xilinx FPGA’s such as Kintex 7, Virtex 6, Virtex 2 Pro, Artix 7.
 Worked in a Team Environment as well as individual Contributor.
EDUCATION
 Masters in Electrical Engineering (VLSI Design & Computer Architecture) GPA: 3.9
University of Southern California August 2015 - May 2017
Courses: Diagnosis and Design of Reliable Digital Systems(EE658), Digital System Design(EE560), Network Processor
Design and Programming (EE533), MOS VLSI Circuit Design (EE577A), VLSI System Design (EE477), Computer System
Organization (EE457).
LANGUAGES AND TECHNOLOGIES
Programming Languages VHDL, Verilog, C, C++, PERL, Python.
IDE/Tools Xilinx ISE, Vivado, Chipscope, Cadence Virtuoso, NC sim, Synopsys Design Compiler,
Cadence Encounter, Hspice, Model sim, Matlab.
WORK EXPERIENCE
RTL Design Engineer Uurmi Systems Pvt Ltd July 2013 – August 2015
 Implemented Verilog and VHDL codes for Amplitude Modulation, Frequency Modulation, Squelch and GPMC (General
Purpose Memory Controller) modules using XILINX ISE and verified on Kintex 7 FPGA.
 Implemented clock domain crossing and validated on Kintex 7 FPGA.
 Was one of the four-member team involved in the development of IF (Intermediate Frequency) module for
waveforms, integration of PHY (Physical Layer) with IF on SDR (Software Defined Radio) platform.
 SDR Board bring up by configuring ADC (ADS4249), DAC (AD9747) Chips using SPI Protocol.
 Designed & Integrated Amplitude Modulation(AM) and Frequency Modulation(FM) modules for SDR Platform and
validated.
PROJECTS
 Design and Implementation of 32 bit Tomasulo Processor with Out of Order Execution and In-order Completion in
VHDL.
- Designed and Implemented a 32 bit Tomasulo Processor with Out of Order Execution and In-Order Completion on
Nexys 4 Artix 7 FPGA board. Implemented 4 issue queue units such as Load/Store queue, Integer queue, Division
queue, Multiplication queue for Out of Order Execution and also Reorder Buffer(ROB) for In-order Completion.
- Implemented Copy Free Check Pointing for Speculative Execution beyond the branch instructions and also to
reduce the use of FPGA resources.
- Implemented 2 stage Dispatch Unit for accommodating the delay of BRAM as well as Implemented Issue unit for
issuing instructions to avoid any collision on Common Data Bus(CDB).
 Design and implementation of Single Core Dual Threaded Pipelined Processor with re-configurable FIFO in Verilog.
- Implemented and Tested a Single Core Dual Threaded Custom Network Processor with support for R-Type, Load
Word, Store Word, Branch and Immediate Instructions.
- A reconfigurable FIFO was designed, which would perform as FIFO to collect incoming packets and also act as
Data Memory, that the processor could access to perform data operations on the network data.

2. - Successfully ran various programs like Bubble Sort, swapping etc. on real time network data by deploying the
custom processor on DETER Network Environment.
 Detection and Prevention of DDOS attacks implementation. Implemented 8 bit RSA based Encryption System
Completely on Hardware. The Encryption and Decryption were handled by Encryption Hardware Accelerators and
Custom Network Processor.
- Implemented Network Address Translator at Gateway which would provide security to a private network from
public network.
- Implemented voluminous DDOS attack prevention by keeping a track of IP addresses and blocking them after a
certain limit.
- Hardware Accelerators were designed to accelerate network address translation and crypto operations.
 AXI Interconnect Implementation for SOC: Designed AXI compliant Master and Slave interfaces for routing
transaction between network of Master and Slaves. Requests from different Masters are completed Out of Order
while requests coming from same Master are completed in order
 MIPS 5 stage Pipeline CPU Design with BRAM in VHDL: Implemented 5 stage MIPS pipeline Architecture with early
branch. Data path design along with Hazard Detection Units and Forwarding Units for handling structural, data and
control Hazards. The project was simulated in Xilinx Virtex 2P FPGA and implemented on NETFPGA.
 Design and Implementation of Single Clock and Two Clock FIFO: Designed and implemented single clock FIFO with N
bit pointers and N+1 bit pointers as well as Two Clock FIFO with N + 1 bit pointers.
 Divider with Cache: Designed and Implemented divider along with cache. Behavioral simulation is done using Model
Sim while synthesis implementation is done on Nexys-4 DDR Artix 7 FPGA.
 Physical Design of a General Purpose Microprocessor using Software and Hardware Components: Designed and
implemented a 5 stage pipeline with support for 18 instructions such as Load, Store, Multiplier, Adder, XOR etc. both
schematic and layout in cadence.
- Power optimization, Area optimization have been taken care by implementing dynamic logic, clock gating and
power gating. Perl was used to automate the entire flow and solve the dependencies.
- Back end Perl scripting was done to verify the results.
 Network Intrusion Detection Engine Design on FPGA: A custom intrusion detection hardware was implemented on
Xilinx using Bloom Filter in Verilog.
- This module was introduced into the Reference Router available as part of NetFPGA Spartan 6 boards and was
tested for matching suspicious patterns.
- The router was deployed in DETER environment and tested for about 1000 malicious patterns which were
successfully dropped.
 Full Custom SRAM Design: Implemented a 1024 bit 6T SRAM in Cadence Virtuoso in both schematic and layout and
used Perl Scripting for generation of vector files. Achieved a clock period of 1.5ns along with reduced area.
 Design of a Traffic Signal Controller: Design and implementation of Traffic Signal Controller in Cadence (Virtuoso) to
control traffic movement in a traffic crossing. The notable feature of this controller is duration of the clock for which
the signal is going to be active can be set dynamically using a user input signal. In-depth analysis is done to get
Minimum area delay product as well as maximum frequency.
 Design and implementation of 6-bit Multiplier: Designed and implemented 6 bit 2’s complement multiplier both in
schematic and layout and automated design using Perl scripting with Lagged Fibonacci generator generated values.
 Implementation of one-bit 1T DRAM cell in Hspice using 7nm FinFET technology: One Bit IT DRAM was implemented
in HSPICE using 7nm FinFET Technology. The variation Power w.r.t Fin number and Capacitance was observed.