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Mentor vlsi lab btech_4_1

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Vijay Kannamalla
Vijay Kannamalla

The document outlines an ASIC design flow using Mentor Graphics tools and describes 10 experiments for digital and analog circuit design. The design flow involves using Pyxis Schematic for circuit design, Pyxis Layout for layout, and Calibre for verification. The 10 experiments include designing basic gates, adders, latches, counters, static RAM cells, and differential amplifiers. The goal is to take students through the full ASIC design flow from circuit design to tapeout.

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VLSI Laboratory Manual B. Tech- ECE JNTU Kakinada
Preface: Introduction to ASIC Design Flow: Typical ASIC Design Flow by Using Mentor Graphics Tools is given below. Pyxis Schematic: Pyxis Schematic interacts seamlessly with other solutions in the Pyxis Custom IC Design Platform to create, develop, simulate, verify, optimize and implement even the most challenging full custom analog and mixed-signal IC designs quickly and accurately—the first time. As a designer, you enjoy a consistent look and feel in single environment, whether creating schematics, block diagrams, symbols, or HDL representations. Additionally, Mentor’s foundry partners provide certified design kits for use with Pyxis Custom IC Design Platform solutions.
Pyxis Layout: Pyxis Layout supports an extensive set of editing functions for efficient, accurate polygon editing. This gives the design engineer full control of circuit density and performance, while improving productivity by as much as 5X. Hierarchy and advanced window management allows multiple views of the same cell and provides the capability to edit both views. Additionally, design engineers can create matched analog layouts quickly by editing using a half-cell methodology. Calibre: Debugging the error results of physical and circuit verification is costly, both in time and resources. Calibre RVE provides fast, flexible, easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule. Better yet, Calibre RVE easily integrates into all popular layout environments, so no matter which design environment you use, Calibre RVE provides the debugging technology you need for fast, accurate error resolution. List of Experiments: 1. Design and Implementation of an Inverter 2. Design and Implementation of Universal Gates 3. Design and Implementation of Full Adder 4. Design and Implementation of Full Subtractor 5. Design and Implementation of RS -Latch 6. Design and Implementation of D - latch 7. Design and Implementation of Asynchronous Counter 8. Design and Implementation of Static SRAM Cell 9. Design and Implementation of Differential Amplifier 10.Design and Implementation of Ring Oscillator
Experiment No : 01 Design and Implementation of an Inverter AIM: To design and Implementation of an Inverter TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: PROCEDURE: 1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool 2. Enter into Simulation mode. 3. Setup the Analysis and library. 4. Setup the required analysis.
5. Probe the required Voltages 6. Run the simulation. 7. Observe the waveforms in EZ wave. 8. Draw the layout using Pysis Layout. 9. Perform Routing using IRoute 10. Perform DRC, LVS, PEX. Result:
Layout: Result Verification Environment:
Experiment No : 02 Design and Implementation Universal Gates Aim: To design and implementation of universal gates Tools: Mentor Graphics-Pyxis, AMS, Calibre (i). NAND Gate: PROCEDURE: 1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool 2. Enter into Simulation mode. 3. Setup the Analysis and library. 4. Setup the required analysis. 5. Probe the required Voltages 6. Run the simulation. Circuit Diagram:
7. Observe the waveforms in EZ wave. Testbench:
NOR Gate: Result:
Testbench:
Experiment No : 03 Design and Implementation of Full Adder AIM: To design and Implementation of an Fulladder TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
Page 12 Result:
Experiment No : 04 Design and Implementation of Full Subtractor AIM: To design and Implementation of an Full-subtractor TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
Page 14
Experiment No : 05 Design and Implementation of RS-Latch AIM: To design and Implementation of RS Latch TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
Page 16 Result: Experiment No : 06 Design and Implementation of D-Latch
AIM: To design and Implementation of an D-Latch TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
Page 18 Result:
AIM: Deploy System Pvt Ltd Page 19 Experiment No : 07 Design and Implementation of Asynchronous Counter To design and Implementation of an Asynchronous Counter TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. transistor dimensions: PMOS: 0.52U NMOS : 0.25U CIRCUIT DIAGRAM: Testbench:
Result:
Experiment No : 08 Design and Implementation of Static-Ram Cellnd Implementation of Static Ram Cell TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Test:
Result:
Experiment No : 09 Design and Implementation of Differential Amplifier AIM: To design and Implementation of an Differential Amplifier TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
Result:
Experiment No : 10 Design and Implementation of an Ring Counternd Implementation of Ring Counter TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. transistor dimensions: PMOS: 0.52U NMOS : 0.25U CIRCUIT DIAGRAM: Result:

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Mentor vlsi lab btech_4_1

  • 1. VLSI Laboratory Manual B. Tech- ECE JNTU Kakinada
  • 2. Preface: Introduction to ASIC Design Flow: Typical ASIC Design Flow by Using Mentor Graphics Tools is given below. Pyxis Schematic: Pyxis Schematic interacts seamlessly with other solutions in the Pyxis Custom IC Design Platform to create, develop, simulate, verify, optimize and implement even the most challenging full custom analog and mixed-signal IC designs quickly and accurately—the first time. As a designer, you enjoy a consistent look and feel in single environment, whether creating schematics, block diagrams, symbols, or HDL representations. Additionally, Mentor’s foundry partners provide certified design kits for use with Pyxis Custom IC Design Platform solutions.
  • 3. Pyxis Layout: Pyxis Layout supports an extensive set of editing functions for efficient, accurate polygon editing. This gives the design engineer full control of circuit density and performance, while improving productivity by as much as 5X. Hierarchy and advanced window management allows multiple views of the same cell and provides the capability to edit both views. Additionally, design engineers can create matched analog layouts quickly by editing using a half-cell methodology. Calibre: Debugging the error results of physical and circuit verification is costly, both in time and resources. Calibre RVE provides fast, flexible, easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule. Better yet, Calibre RVE easily integrates into all popular layout environments, so no matter which design environment you use, Calibre RVE provides the debugging technology you need for fast, accurate error resolution. List of Experiments: 1. Design and Implementation of an Inverter 2. Design and Implementation of Universal Gates 3. Design and Implementation of Full Adder 4. Design and Implementation of Full Subtractor 5. Design and Implementation of RS -Latch 6. Design and Implementation of D - latch 7. Design and Implementation of Asynchronous Counter 8. Design and Implementation of Static SRAM Cell 9. Design and Implementation of Differential Amplifier 10.Design and Implementation of Ring Oscillator
  • 4. Experiment No : 01 Design and Implementation of an Inverter AIM: To design and Implementation of an Inverter TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: PROCEDURE: 1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool 2. Enter into Simulation mode. 3. Setup the Analysis and library. 4. Setup the required analysis.
  • 5. 5. Probe the required Voltages 6. Run the simulation. 7. Observe the waveforms in EZ wave. 8. Draw the layout using Pysis Layout. 9. Perform Routing using IRoute 10. Perform DRC, LVS, PEX. Result:
  • 7. Experiment No : 02 Design and Implementation Universal Gates Aim: To design and implementation of universal gates Tools: Mentor Graphics-Pyxis, AMS, Calibre (i). NAND Gate: PROCEDURE: 1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool 2. Enter into Simulation mode. 3. Setup the Analysis and library. 4. Setup the required analysis. 5. Probe the required Voltages 6. Run the simulation. Circuit Diagram:
  • 8. 7. Observe the waveforms in EZ wave. Testbench:
  • 11. Experiment No : 03 Design and Implementation of Full Adder AIM: To design and Implementation of an Fulladder TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
  • 13. Experiment No : 04 Design and Implementation of Full Subtractor AIM: To design and Implementation of an Full-subtractor TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
  • 15. Experiment No : 05 Design and Implementation of RS-Latch AIM: To design and Implementation of RS Latch TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
  • 16. Page 16 Result: Experiment No : 06 Design and Implementation of D-Latch
  • 17. AIM: To design and Implementation of an D-Latch TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
  • 19. AIM: Deploy System Pvt Ltd Page 19 Experiment No : 07 Design and Implementation of Asynchronous Counter To design and Implementation of an Asynchronous Counter TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. transistor dimensions: PMOS: 0.52U NMOS : 0.25U CIRCUIT DIAGRAM: Testbench:
  • 21. Experiment No : 08 Design and Implementation of Static-Ram Cellnd Implementation of Static Ram Cell TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Test:
  • 23. Experiment No : 09 Design and Implementation of Differential Amplifier AIM: To design and Implementation of an Differential Amplifier TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. CIRCUIT DIAGRAM: Testbench:
  • 25. Experiment No : 10 Design and Implementation of an Ring Counternd Implementation of Ring Counter TOOLS: Mentor Graphics - Pyxis, AMS, Calibre. transistor dimensions: PMOS: 0.52U NMOS : 0.25U CIRCUIT DIAGRAM: Result: