JOEL AMZALLAG
                                             SUMMARY

Professional Applications Engineer dedicated to customer’s success. Reduced development costs and
improved product competitiveness by partnering with hardware engineers and IC designers. Technical
evangelist building and presenting demos, and aiding the sales team. Track record in driving the adoption
of new technologies: analog and digital simulation, synthesis, signal integrity, and analog test benches.
Created innovative solutions in the promotion and integration of products and flows. Enhanced
knowledge of industry trends through continuing education opportunities.

•   Extensive experience in EDA tools for IC, ASIC / FPGA and High-Speed board designs.
•   10+ years in technical applications roles providing pre and post sales support.
•   Hands on experience with test equipment for in lab analysis: signal generators, oscilloscopes, etc.
•   Directed projects including Development Kit and Test Benches with teams in Europe, USA and Asia.
•   International customer facing experience. Fluent in French and English.

                                            EXPERIENCE

Field Applications Engineer, Solido design Automation, San-Jose, CA                      2010 – present
EDA startup addressing operating range and process variation for nanometer transistor-level design.

Won and increased usage at Tier 1 accounts.
• Introduced and educated customers to use statistical data analysis in IC design: 28nm, 20nm.
• Defined and collaborated with customer a new Power tool estimation for mobile devices.

Senior Product Engineer, Xoomsys, Cupertino, CA                                          2008 – 2009
EDA startup that developed products to handle large analog designs and speed up SPICE simulations.

Implemented new product features and enhancements and interfaced with partners and customers.
• Designed, coded, and tested accuracy, capacity, and speed of interpolation method utilized in Verilog-
   A vs. CMI interface with Spectre-Hspice resulting in a simulation speed increase up to 5x.
• Orchestrated and executed Cadence (Spectre and APS) simulation benchmarks during the Mergers &
   Acquisitions (M&A) process. Worked closely with engineering for bug fixes, workarounds, and
   simulation speed up improvement. Presented final results to support the M&A decision.

Analog Mixed Signal Applications Engineer, Knowlent, Santa Clara, CA              2006 – 2008
EDA startup focused on automation and reuse of analog tests for SERDES and analog blocks. The
technology was acquired by Cadence.

Revamped regression system to improve the quality assurance, wrote specifications for new product Test
Bench Builder (GUI to develop, reuse and automate analog tests), and was primary technical interface
with customers, sales, and engineering.
• Conceived simulation test benches in TCL for the electrical compliance verification of LVDS, HDMI,
    SATA2, SAS6G, and ADC during competitive benchmarks. Added UMC foundry as a customer.
• Successfully implemented unit tests and flow tests in the regression system resulting in 100%
    improvement in the quality of the simulation framework Opal and Test Bench Builder.
• Translated the Physical Layer’s Electrical Specification of HDMI into simulation test benches, then
    led the China team for the execution and tested the product to insure the compliance with HDMI
    specification. Worked with customers to refine the tests. Sold a copy to UMC.
• Created Test Bench Builder. Worked with customers to collect market and application requirements,
    then designed and wrote specifications documents to drive innovation into Test Bench Builder. This
    product was sold to Cadence to be included in ADE.
JOEL AMZALLAG                                                                              PAGE TWO

Consultant, Sunnyvale, CA                                                                   2003 – 2006
Consultation services at Altera for 3 projects. Tested the implementation of new features and improved
the quality of 2 DSP IPs and delivered one Development Kit.
• Automated test procedures for verification of new features added to Color Space Converter (CSC)
    and Finite Impulse Response (FIR) Compiler across huge parameter sets. Saved time in reporting
    problems resulting in greater coverage, improving the speed and the quality of the IPs.
• Delivered on time, as project manager, the DSP Development Kit Cyclone II DSP edition. Reviewed
    the PCB layout, supervised and interacted with worldwide technical teams of 8 engineers for the
    delivery of the reference designs, and interfaced with engineers and managers by providing schedule
    updates and roadmap plans. Wrote and reviewed technical documentation, implemented the Factory
    Design for the “Getting Started User Guide”, used laboratory equipment to debug the boards, and
    validated all the reference designs.

Senior Applications Consultant, Synopsys and Viewlogic Mountain View, CA                   1997 – 2003
Ensured customer satisfaction and needs to increase accounts penetration. Technical leader successfully
engaging and building trust with customer’s base.
• Supported Design Compiler, Primetime, and Physical Compiler as SOC implementation specialist.
   Optimized customer's scripts to reduce power consumption and analyzed critical paths.
• FPGA specialist working with customers during tool evaluation, benchmarks and technical support.
• Rebuilt the business for Northern California, as the one and only Viewlogic applications engineer
   supporting all tools and customers: $12M bookings the first year.
• Worked with signal integrity engineers and hardware engineers at major accounts (Cisco, Brocade,
   Intel, HP, Agilent, Altera) to get their boards released on time.
• Provided technical and project leadership to junior applications engineers.
• Lead AE for analog, mixed signal and signal integrity demonstrations, benchmarks and conferences.
   Won new major accounts.

                                       ADDITIONAL EXPERIENCE

•   Pioneered Viewlogic Southern Europe organization: $12M bookings achieved in 1997, staff of 8
    reporting engineers.

                                                EDUCATION

•   RFIC Design, San Jose State University: Built from the ground up - design and circuit optimization -
    a LNA and a Gilbert Mixer with a 90nm CMOS library. Used Cadence tools for the design,
    simulation and the layout.
•   Electronic Engineer (BSEE/MSEE Equivalent) CNAM, Conservatoire National des Arts et Metiers,
    Paris 3ieme – France, Major: Electronic (Thesis: DC-DC resonant converter).

                                             TECHNICAL SKILLS

•   EDA / CAD tools from Viewlogic, Synopsys, Cadence, Mentor, Altera (Viewdraw, DxDesigner,
    XTK, HSPICE, DC, PT, VCS, IC5.1 & IC6.1, Spectre, SpectreRF, Eldo, Modelsim, Quartus).
•   Languages: SPICE, Verilog, Perl, Tcl, Python, Shell Scripts, Octave / Matlab. programming and data
    analysis skills (Python, JMP, Matlab).
•   Computers: Solaris, Linux, Windows as well as networking, system administration and Flexlm
    license administration.

Joel Amzallag

  • 1.
    JOEL AMZALLAG SUMMARY Professional Applications Engineer dedicated to customer’s success. Reduced development costs and improved product competitiveness by partnering with hardware engineers and IC designers. Technical evangelist building and presenting demos, and aiding the sales team. Track record in driving the adoption of new technologies: analog and digital simulation, synthesis, signal integrity, and analog test benches. Created innovative solutions in the promotion and integration of products and flows. Enhanced knowledge of industry trends through continuing education opportunities. • Extensive experience in EDA tools for IC, ASIC / FPGA and High-Speed board designs. • 10+ years in technical applications roles providing pre and post sales support. • Hands on experience with test equipment for in lab analysis: signal generators, oscilloscopes, etc. • Directed projects including Development Kit and Test Benches with teams in Europe, USA and Asia. • International customer facing experience. Fluent in French and English. EXPERIENCE Field Applications Engineer, Solido design Automation, San-Jose, CA 2010 – present EDA startup addressing operating range and process variation for nanometer transistor-level design. Won and increased usage at Tier 1 accounts. • Introduced and educated customers to use statistical data analysis in IC design: 28nm, 20nm. • Defined and collaborated with customer a new Power tool estimation for mobile devices. Senior Product Engineer, Xoomsys, Cupertino, CA 2008 – 2009 EDA startup that developed products to handle large analog designs and speed up SPICE simulations. Implemented new product features and enhancements and interfaced with partners and customers. • Designed, coded, and tested accuracy, capacity, and speed of interpolation method utilized in Verilog- A vs. CMI interface with Spectre-Hspice resulting in a simulation speed increase up to 5x. • Orchestrated and executed Cadence (Spectre and APS) simulation benchmarks during the Mergers & Acquisitions (M&A) process. Worked closely with engineering for bug fixes, workarounds, and simulation speed up improvement. Presented final results to support the M&A decision. Analog Mixed Signal Applications Engineer, Knowlent, Santa Clara, CA 2006 – 2008 EDA startup focused on automation and reuse of analog tests for SERDES and analog blocks. The technology was acquired by Cadence. Revamped regression system to improve the quality assurance, wrote specifications for new product Test Bench Builder (GUI to develop, reuse and automate analog tests), and was primary technical interface with customers, sales, and engineering. • Conceived simulation test benches in TCL for the electrical compliance verification of LVDS, HDMI, SATA2, SAS6G, and ADC during competitive benchmarks. Added UMC foundry as a customer. • Successfully implemented unit tests and flow tests in the regression system resulting in 100% improvement in the quality of the simulation framework Opal and Test Bench Builder. • Translated the Physical Layer’s Electrical Specification of HDMI into simulation test benches, then led the China team for the execution and tested the product to insure the compliance with HDMI specification. Worked with customers to refine the tests. Sold a copy to UMC. • Created Test Bench Builder. Worked with customers to collect market and application requirements, then designed and wrote specifications documents to drive innovation into Test Bench Builder. This product was sold to Cadence to be included in ADE.
  • 2.
    JOEL AMZALLAG PAGE TWO Consultant, Sunnyvale, CA 2003 – 2006 Consultation services at Altera for 3 projects. Tested the implementation of new features and improved the quality of 2 DSP IPs and delivered one Development Kit. • Automated test procedures for verification of new features added to Color Space Converter (CSC) and Finite Impulse Response (FIR) Compiler across huge parameter sets. Saved time in reporting problems resulting in greater coverage, improving the speed and the quality of the IPs. • Delivered on time, as project manager, the DSP Development Kit Cyclone II DSP edition. Reviewed the PCB layout, supervised and interacted with worldwide technical teams of 8 engineers for the delivery of the reference designs, and interfaced with engineers and managers by providing schedule updates and roadmap plans. Wrote and reviewed technical documentation, implemented the Factory Design for the “Getting Started User Guide”, used laboratory equipment to debug the boards, and validated all the reference designs. Senior Applications Consultant, Synopsys and Viewlogic Mountain View, CA 1997 – 2003 Ensured customer satisfaction and needs to increase accounts penetration. Technical leader successfully engaging and building trust with customer’s base. • Supported Design Compiler, Primetime, and Physical Compiler as SOC implementation specialist. Optimized customer's scripts to reduce power consumption and analyzed critical paths. • FPGA specialist working with customers during tool evaluation, benchmarks and technical support. • Rebuilt the business for Northern California, as the one and only Viewlogic applications engineer supporting all tools and customers: $12M bookings the first year. • Worked with signal integrity engineers and hardware engineers at major accounts (Cisco, Brocade, Intel, HP, Agilent, Altera) to get their boards released on time. • Provided technical and project leadership to junior applications engineers. • Lead AE for analog, mixed signal and signal integrity demonstrations, benchmarks and conferences. Won new major accounts. ADDITIONAL EXPERIENCE • Pioneered Viewlogic Southern Europe organization: $12M bookings achieved in 1997, staff of 8 reporting engineers. EDUCATION • RFIC Design, San Jose State University: Built from the ground up - design and circuit optimization - a LNA and a Gilbert Mixer with a 90nm CMOS library. Used Cadence tools for the design, simulation and the layout. • Electronic Engineer (BSEE/MSEE Equivalent) CNAM, Conservatoire National des Arts et Metiers, Paris 3ieme – France, Major: Electronic (Thesis: DC-DC resonant converter). TECHNICAL SKILLS • EDA / CAD tools from Viewlogic, Synopsys, Cadence, Mentor, Altera (Viewdraw, DxDesigner, XTK, HSPICE, DC, PT, VCS, IC5.1 & IC6.1, Spectre, SpectreRF, Eldo, Modelsim, Quartus). • Languages: SPICE, Verilog, Perl, Tcl, Python, Shell Scripts, Octave / Matlab. programming and data analysis skills (Python, JMP, Matlab). • Computers: Solaris, Linux, Windows as well as networking, system administration and Flexlm license administration.