1. This document provides an overview of the CMOS design flow using Mentor Graphics tools. It describes the basic steps of schematic design, simulation, physical design, and physical verification.
2. The key steps are: designing the schematic in Pyxis, simulating in ELDO, creating the layout in Pyxis Layout, and performing DRC, LVS, and parasitic extraction in Calibre.
3. The document walks through creating an inverter cell as an example, covering schematic creation, symbol generation, simulation, layout generation, and running the physical verification tools.
An application-specific IC (ASIC) can be either a digital or an analog circuit. As their name implies, ASICs are not reconfigurable; they perform only one specific function. For example, a speed controller IC for a remote control car is hard-wired to do one job and could never become a microprocessor. An ASIC does not contain any ability to follow alternate instructions.
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Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
An application-specific IC (ASIC) can be either a digital or an analog circuit. As their name implies, ASICs are not reconfigurable; they perform only one specific function. For example, a speed controller IC for a remote control car is hard-wired to do one job and could never become a microprocessor. An ASIC does not contain any ability to follow alternate instructions.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
In telecommunication, an eye pattern, also known as an eye diagram, is an oscilloscope display in which a digital signal from a receiver is repetitively sampled and applied to the vertical input, while the data rate is used to trigger the horizontal sweep. It is so called because, for several types of coding, the pattern looks like a series of eyes between a pair of rails. It is a tool for the evaluation of the combined effects of channel noise and intersymbol interference on the performance of a baseband pulse-transmission system. It is the synchronised superposition of all possible realisations of the signal of interest viewed within a particular signaling interval.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
A VLSI (Very Large Scale Integration) system integrates millions of “electronic components” in a small area (few mm2 few cm2).
design “efficient” VLSI systems that has:
Circuit Speed ( high )
Power consumption ( low )
Design Area ( low )
A fundamental introduction to Intellectual Property in VLSI domain. Starts from basics and includes types of IPs and their examples, life cycle of an IP and other few topics in brief in an interactive Q-A manner.
The material is also available at : https://wordpress.com/stats/day/vlsifundamentals.wordpress.com
In telecommunication, an eye pattern, also known as an eye diagram, is an oscilloscope display in which a digital signal from a receiver is repetitively sampled and applied to the vertical input, while the data rate is used to trigger the horizontal sweep. It is so called because, for several types of coding, the pattern looks like a series of eyes between a pair of rails. It is a tool for the evaluation of the combined effects of channel noise and intersymbol interference on the performance of a baseband pulse-transmission system. It is the synchronised superposition of all possible realisations of the signal of interest viewed within a particular signaling interval.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
A VLSI (Very Large Scale Integration) system integrates millions of “electronic components” in a small area (few mm2 few cm2).
design “efficient” VLSI systems that has:
Circuit Speed ( high )
Power consumption ( low )
Design Area ( low )
A fundamental introduction to Intellectual Property in VLSI domain. Starts from basics and includes types of IPs and their examples, life cycle of an IP and other few topics in brief in an interactive Q-A manner.
The material is also available at : https://wordpress.com/stats/day/vlsifundamentals.wordpress.com
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Slide 1: Title Slide
Extrachromosomal Inheritance
Slide 2: Introduction to Extrachromosomal Inheritance
Definition: Extrachromosomal inheritance refers to the transmission of genetic material that is not found within the nucleus.
Key Components: Involves genes located in mitochondria, chloroplasts, and plasmids.
Slide 3: Mitochondrial Inheritance
Mitochondria: Organelles responsible for energy production.
Mitochondrial DNA (mtDNA): Circular DNA molecule found in mitochondria.
Inheritance Pattern: Maternally inherited, meaning it is passed from mothers to all their offspring.
Diseases: Examples include Leber’s hereditary optic neuropathy (LHON) and mitochondrial myopathy.
Slide 4: Chloroplast Inheritance
Chloroplasts: Organelles responsible for photosynthesis in plants.
Chloroplast DNA (cpDNA): Circular DNA molecule found in chloroplasts.
Inheritance Pattern: Often maternally inherited in most plants, but can vary in some species.
Examples: Variegation in plants, where leaf color patterns are determined by chloroplast DNA.
Slide 5: Plasmid Inheritance
Plasmids: Small, circular DNA molecules found in bacteria and some eukaryotes.
Features: Can carry antibiotic resistance genes and can be transferred between cells through processes like conjugation.
Significance: Important in biotechnology for gene cloning and genetic engineering.
Slide 6: Mechanisms of Extrachromosomal Inheritance
Non-Mendelian Patterns: Do not follow Mendel’s laws of inheritance.
Cytoplasmic Segregation: During cell division, organelles like mitochondria and chloroplasts are randomly distributed to daughter cells.
Heteroplasmy: Presence of more than one type of organellar genome within a cell, leading to variation in expression.
Slide 7: Examples of Extrachromosomal Inheritance
Four O’clock Plant (Mirabilis jalapa): Shows variegated leaves due to different cpDNA in leaf cells.
Petite Mutants in Yeast: Result from mutations in mitochondrial DNA affecting respiration.
Slide 8: Importance of Extrachromosomal Inheritance
Evolution: Provides insight into the evolution of eukaryotic cells.
Medicine: Understanding mitochondrial inheritance helps in diagnosing and treating mitochondrial diseases.
Agriculture: Chloroplast inheritance can be used in plant breeding and genetic modification.
Slide 9: Recent Research and Advances
Gene Editing: Techniques like CRISPR-Cas9 are being used to edit mitochondrial and chloroplast DNA.
Therapies: Development of mitochondrial replacement therapy (MRT) for preventing mitochondrial diseases.
Slide 10: Conclusion
Summary: Extrachromosomal inheritance involves the transmission of genetic material outside the nucleus and plays a crucial role in genetics, medicine, and biotechnology.
Future Directions: Continued research and technological advancements hold promise for new treatments and applications.
Slide 11: Questions and Discussion
Invite Audience: Open the floor for any questions or further discussion on the topic.
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2. 2
Objective
Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the
Full Custom IC design cycle. You will finish the lab by running DRC, LVS and Parasitic
Extraction on the various designs. In the process you will create various components like
inverter, NAND gate, XOR gate, Full adder, Latch, SRAM register cell and PLL, differential
amplifier.
You will start the lab by creating a schematic and will attach the technology library called
“GDK 130nm( generic 13)”. Adding a technology library will ensure that you can do front to
back design.
You will create a new cell called “Inverter” with schematic view and hence build the inverter
schematic by instantiating various components. Once inverter schematic is done, symbol for
“Inverter” is generated. Now you will create a new cell view called “Inverter_sim”, where
you will instantiate “Inverter” symbol. This circuit is verified by doing various simulations
using ELDO. In the process, you will learn to use EZviewer, waveform window options,
waveform calculator, etc...
You will learn the Pyxis Layout Editor basics by concentrating on designing an “Inverter”
through automatic layout generation. Then you will go ahead with completing the other
layouts,generating GDSII file. After that, by taking GDSII file as reference you will run DRC,
LVS checkson the layout, Extract parasitic and back-annotate them to the simulation
environment.
3. 3
Introduction:
This document gives an overview of CMOS design using Mentor graphics Tools.
There are five basic steps:
1. Design the schematic in Pyxis schematic.
2. Simulate the schematic using ELDO / AMS.
3. Physical design using Pyxis Layout.
4. Perform Physical Verification using Calibre which includes DRC, LVS and PEX.
5. Back annotation of parasitics into the schematic for post layout simulation.
4. 4
Invoking Mentor tools:
• Right click on the desktop and select open in terminal
• Type csh and press enter.
• Type source /home/software/cshrc/ams_2009.cshrc which will invoke the mentor tools
environment.
• Type dmgr_ic & and press enter then pyxis project manager window will be invoked as
shown below.
5. 5
Creating a Project:
• To create a new project click on File new project which invokes the new project
window as shown
• Browse on the folder and specify the project path as shown below
6. 6
• After browsing the folder to the specific location give the project name as shown and
click on OK
• Next technology libraries have to be added to the project. In order to add the technology
files browse on the folder as shown
7. 7
• Navigate to /home/software/FOUNDRY/GDK/Pyxis_SPT_HEP
/ic_reflibs/tech_libs and select the generic13 file and click on OK
• Again click on OK then manage external/logic libraries window will pop up as shown
8. 8
• Click on the Add Standard Libraries
• Then the libraries will be added up as shown below and click on OK
• Then the pyxis project manager window will be shown where the technology
libraries are added to the project and are placed below the project name
10. 10
Creating a Library:
• To create a library right click on the project name and select new library or
click on the icon on the icon bar
• Then a new library window will pop up asking for the library name.
Next name the library and click on OK.
11. 11
Creating a Schematic cell view:
• To create a schematic cell view, a new cell has to be created in which new
schematic has to be defined. In order to create new cell right click on the
manual library below the project name and select new cell or select the library
and click on the icon in the icon bar.
• Then a new cell window will pop up asking for the cell name in which give the
cell name and click OK
• To create a schematic in the cell,right click on the cell name and select new
schematic or click on the new cell and select the icon in the icon bar
12. 12
• A window will pop up asking for the schematic name
Now name the schematic and click on OK which in turn leads to the pyxis schematic
editor window as shown
13. 13
Creating a Schematic:
In this section you will become familiar with placing primitive analog devices for a
inverter.
You’ll learn how to:
• place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• route devices
• edit device parameter values
• name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using Eldo
• view results
Creating an Inverter:
Placing devices:
• From the left icon bar press on add instance icon
or press 'I'
14. 14
• Then a file browser which contains entire libraries will pop up as shown
• Next click on the double click on generic13 in the library list
And then follow the path to select pmos from $generic13/symbols/pmos as shown
15. 15
• Select the pmos and click on OK to place the pmos on the workspace as
shown
16. 16
Changing device properties
In order to change the properties of the devices on the workspace click on the
then the corresponding device properties will be shown in the object editor as shown.
Now enter the prescribed value in the field provided and press enter .Then the value
will be changed .Here the width has been set to 0.15u and length to 0.13u.
• Similarly select the nmos and change the W=0.13u,L=0.15u and the
schematic would look as follows
17. 17
Adding the ports and connecting the devices
• In the similar way select the VDD and ground from the generic lib or click on the
library in the layer palatte window then layer palatte will be shown as ic library
window. Then select generic library and place VDD and ground
18. 18
• Place in IN and OUT ports in a similar way as above from the generic library
or click on the add ports icon in the left icon bar and connect the circuit
• Then the schematic would look as follows
For changing the port names click on the port and change the net name in the object
editor to the required name which is shown below.
19. 19
To change the name, enter the name in the field given for the net name and press
enter. Then the schematic will be as shown
• Next click on check/save icon in the icon bar
20. 20
This will result to an window which shows the error report where the errors and
warnings in the schematic can be seen
21. 21
Generating a symbol:
• To generate a symbol select Add in the menu bar and then select generate
symbol from pull down menu bar
Add --> generate symbol
• A generate symbol will pop up as shown
Here check activate symbol as shown above. If you want set shape of the symbol
select it from choose shape. Then click on OK which leads to the pyxis symbol
window.
22. 22
• Next click on check/save icon in the icon bar
Creating a Test bench
• To create a test bench close the pyxis schematic and symbol windows and go
back to pyxis project manager window. In the project manager window to
create new cell right click on the manual library below the project name and
select new cell or select the library and click on the icon
in the icon bar
• Then a new cell window will pop up asking for the cell name in which give the
cell name and click OK
23. 23
• Here the test bench cell name has been specified as inv_tb.
• Right click on the test bench cell and select new schematic which in turn opens
pyxis schematic editor window
• Now instantiate the new inverter symbol by selecting Add > Instance from the
left icon Palette or pressing the hot key i. Select the Symbol view of the
inverter cell from the inv cell of the manual library
24. 24
Place the symbol on the work space as shown
• Add the IN and OUT net as before by selecting the hot key i. Name the nets
with hot key “q”.
• Add VDD and Ground ports in a similar fashion.
25. 25
• Add a DC voltage source dc_v_source, from the MGC_IC_SOURCES_LIB.
Change the value of the DC property to be 3.3 V. Add PULSE voltage source
pulse_v_source and change the value of the pulse_value property to be 3.3 V
also change the delay to be 0S.
Finally the circuit looks like the following
• Next click on check/save icon in the icon bar
This will result to an window which shows the error report where the errors and
warnings in the symbol can be seen.
Simulating the schematic:
Simulating test bench
• When you have no errors select the Simulation icon from the left icon palette
to go into design context and simulate our design or select context in the
menu bar and select run simulation.
26. 26
• Click ok when this form appears. Now you are in the Design context and need to
setup the analysis type, plots and load in the Eldo models
• In the design context from menu bar select Simulation-> setup simulation
or click on setup simulation icon in the left icon palatte.
27. 27
• A set up simulation window will pop up as shown
28. 28
To set up analysis select analysis in the simulation panel and in the analysis
setup select the required analysis and set the values of the analysis in the beside
window as shown above
Here I have selected the transient analysis with the start time as 0ns, stop
time=100ns
and print timestep=5ns as shown.
After specifying the values click on apply
29. 29
• To probe the waveforms, click on the outputs in the selection panel ,then
select the input port of the schematic in the pyxis schematic window as shown.
• In the setup simulation window , click Add button then the port will be added
to the waveform as shown
similarly add all the waveforms required to see in the ezwave.
30. 30
• To add the power plot select the symbol in simulation schematic, click on
outputs it opens simulation setup. Here we have to select
Analysis -> TRAN
Task -> Plot
Type -> Power
• After adding the analysis, eldo models and probing waveforms minimize
the setup simulation window and run the simulator.To run the simulation
select from the left icon palette or select simulate-> run simulation
View the simulation results by selecting the plot results from latest run icon from
the left icon palatte. This will open EZWave for you with the output waveforms. This
is how the waveforms look like after zooming
31. 31
Click on Measurement tool in the icon bar which opens up the measurement
tool window where we can measure the different properties of your waveforms
Delay measurement :
In order to measure delay select the Measurement tool in Ezwave window and
select the Below options
Measurement -> Delay
Waveform(#1) -> select V(A) and add selected waveform
Waveform(#2) -> select V(Y) and add selected waveform
In Measurement setup select
Waveform(#2) Edge Relationship : Inverting
Enable the Find Closest reference edge option. and click ok.
This process shows you how to measure the delay between input and output.
32. 32
DC Analysis:
• For adding DC analysis click on Analysis button in palette pane of simulation
environment, enable the DC option as displayed below, click apply and ok.
• Now select the input and output nets in simulation schematic and click on
outputs button and select the following options for DC analysis outputs
Analysis -> DC
Task -> Plot
Type -> Voltage
then click on add button and click ok.
33. 33
After adding the outputs click on Run ELDO (the log should display netlist
completed successfully and Simulation completed successfully). Then click on
View waves to visualise the DC analysis results.
Now use Add Cursor option to visualise the switching voltage of the design.
34. 34
Creating a layout:
• To create a layout select inv cell ,right click on the cell and select new layout
• A new window named New layout will pop up, here name the layout as
shown and click Ok
35. 35
Pyxis layout window will be invoked with a new layout sub window in it nd keep the
settings as shown and click on OK
Click restore button and click on MGC --> setup and select left right tiling and click
ok
Restore
button
36. 36
Creating SDL:
• Make the Schematic window active by selecting it with the LMB. Select the
PMOS and press on the Pick & Place icon from SDL tool bar on the Icon bar.
The tool will place the device on the Workspace of IC layout window. Similarly
select the NMOS and place it on the workspace
Note: To make SDL toolbar active, goto setup->SDL.
Creating SDL:
• Make the Schematic window active by selecting it with the LMB.. Select PMOS schematic
and click on Inst option in palette area and place the automatically generated transistor layout
in layout window, similarly select the NMOS and place it on the workspace
• After adding the layouts of transistor, select any one of the net in schematic window and
click on inst and then on port, now move your cursor towards layout window and place
the ports one by one.
• now the layout window should look like below.
37. 37
• Now expand the layout window and draw the layout as specified below
1. select the layer POLYG from the layer Palette window and select Easyedit -> shape
from IC palette and connect the gates of NMOS and PMOS transistors as displayed
below.
2. Select the option Tools from the top row menu and select IRoute and interconnect
PMOS and NMOS transistor as displayed below ( press 'w' to change the width of the
metal track and specify width as 0.26).
38. 38
3. Connect the output port to the metal track using Iroute
4. Create VDD Plane and GND plane using Metal-1 layer . Select metal-1 in layer
palette and choose easyedit -> shape from ic palette and draw planes as shown below
and place the VDD and GND ports in the respective planes
5. Connect the Source of PMOS transistor to VDD plane and Drain of NMOS
transistor to GND plane using Iroute ( keep the width as 0.26).
39. 39
6. To connect the Input port to poly layer ( poly to metal contact) we have to follow
below steps
a. extend the poly region ( approx 0.5x0.5) and draw a contact to poly by
selecting CO layer on Layer palette and select easy edit and shape draw
exactly 0.16x0.16 of CO layer in the extended poly region.
b. now draw metal-1 layer over the CO layer to the input port as shown below
7. To add N-well contacts select the VDD plane in layout area, click on DLA Layout
in IC palette and click on via (right arrow) and select fill selected and select
"m1nwell" in IC device shape via window and click ok
8. To add P-well contacts select the GND plane in layout area, click on DLA Layout
in IC palette and click on via (right arrow) and select fill selected and select
"m1psub" in IC device shape via window and click ok
9. this finishes the layout for Inverter, Now select Add (from top row) and select add
text on ports and click ok. this should add the names on the I/O ports.
40. 40
Physical Verification of a Layout:
Now you can verify the layout by running DRC and LVS checks. we will run Calibre Interactive
Running Calibre Interactive DRC
• In the pyxis layout window, Select Tools Calibre Run DRC
• This will bring up the Calibre Interactive - DRC
Note: Make sure the tabs named Rules,Inputs,Outputs,Run control should be green in color as
shown above which ensures the paths specified are correct. Otherwise paths have to be changed .
• Select Run DRC in the Calibre Interactive window
• The Calibre RVE window will popup and you should see the following results
41. 41
Here the error is due to the percentage of the polysilicon. It requires polyarea coverage of
14%which is not possible in the smaller circuits. So you can ignore that error.
The error in the layout will be highlighted as shown in the fig once if you select on the error
42. 42
Running the LVS
• Select Run LVS in the caliber interactive window shown above
• Calibre RVE window will popup and you should see results similar to this
• If the comparison is wrong click on the comparison results in the RVE window, which
shows the results and select schematics then the netlists will be displayed as shown
• Select Tools > Calibre > Run LVS entry from the pull down menu.
• The Calibre Interactive - LVS window will popup. the Inputs and Netlist tabs are active
as shown.
43. 43
Click on the blocks of the Netlist of the schematic and layout which yields the circuits from you
can verify the connections and ports name and avoid the incorrect LVS
Running Calibre Interactive PEX
• Select Tools Calibre > Run PEX entery from the pull down menu
• The Calibre Interactive - PEX window will popup. Make sure Export from schematic
viewer is selected while the Inputs and Netlist ( if the netlist file is in red colour
browse and select inv.calibre.src.net file)tabs are active as shown
• Choose the output netlist to be in DSPF Format and extraction type to R+C as in the figure below
44. 44
• Save the Netlist file as inv.pex.dspf in any location of your computer
• Select start RVE from caliber interactive pex.
• Calibre RVE window will pop up select parasitics in the navigator then extraction
results will be shown as shown below
• Select Run PEX
• The PEX Netlist file windows will be invoked as shown
45. 45
• Double click on the port name then the parasitic values will be shown
• Double click on the value, then corresponding value will be highlighted in the layout
as shown
46. 46
• Open the test bench schematic and enter the simulation mode, then select the inverter
block
• A window named Add DSPF will pop up where browse on the folder to the saved Netlist
inv.pex.dspf and click OK as shown.
• After adding the .dspf file click on Run Eldo ( should get simulation completed successfully)
• Click on View waves to visulalise the post layout simulation.
48. 48
AIM: To design and simulate the CMOS NAND gate
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
50. 50
AIM: To design and simulate the CMOS NOR gate
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
52. 52
AIM: To design and simulate the CMOS EXOR gate
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
54. 54
AIM: To design and simulate the CMOS Latch
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
56. 56
AIM: To design and simulate the CMOS RAM cell
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
58. 58
AIM: To design and simulate the CMOS 1 Bit Full Adder.
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
60. 60
AIM: To design and simulate the Common Source Amplifier.
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
61. 61
AC ANALYSIS:
• Click on Simulation button form palette area and enter into simulation mode.
• Select the analysis option and specify the below options as given in image.
• Now select the input net and output net and click on Outputs button on palette area and
add the below parameters
Analaysis --> AC
Type --> Voltage
Task --> Plot
Modifier --> Magnitude (dB)
Click on OK
again add one more output parameter for phase as below
Analaysis --> AC
Type --> Voltage
Task --> Plot
Modifier --> Phase
Click ok
• click on run eldo and view waves to see the results
63. 63
AIM: To design and simulate the Differential Amplifier.
TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.
CIRCUIT DIAGRAM:
SIMULATION CIRCUIT:
64. 64
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
RESULTS:
AC Analysis result:
Transient Analysis result: